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[/] [lwrisc/] [trunk/] [RTL/] [device_box.v] - Blame information for rev 19

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`define HARD_CLOCK
 
 
`ifndef HARD_CLOCK
        `define SEG7_CLOCK_MODEL
`endif
 
 
module led_interface (
input clk,  rst,  wr, rd,
input [7:0] din,
output reg [7:0] dout,
output [7:0]led
);
reg [7:0] led_data;
assign led = led_data;
 
always @ (posedge clk)
if (rst)
led_data = 0;
else if (wr)
led_data=din;
 
always@ (posedge clk)
if (rd)
dout=led_data;
else dout = 0;
 
 
endmodule
 
 
module clock_seg7led_interface(
input clk,rst,
input [7:0]din,
output reg [7:0]dout,
input wr,rd ,
input [2:0]wr_addr,input [2:0]rd_addr,
output reg [7:0] seg7_sel,seg7_data
);
reg [7:0]buff[0:3];
always @ (posedge clk)
if (wr)
buff[wr_addr] = din;
 
always @(posedge clk)
if (rd)
dout = buff[rd_addr] ;
else dout=0;
 
        /*the main counter*/
    reg [31:0] seg7_cntr;
    always @(posedge clk)seg7_cntr=seg7_cntr+1;
    wire  [2:0]  sel =seg7_cntr[17:15] ;
        wire flash_bit = seg7_cntr[21];
    always @(posedge clk)
    case (sel[2:0])
        0:seg7_data=(buff[3][0]&flash_bit)?'hff:seg(buff[0][3:0]);
        1:seg7_data=(buff[3][1]&flash_bit)?'hff:seg(buff[0][3:0]);
        2:seg7_data=(buff[3][2]&flash_bit)?'hff:~8'b01000000;
        3:seg7_data=(buff[3][3]&flash_bit)?'hff:seg(buff[1][3:0]);
        4:seg7_data=(buff[3][4]&flash_bit)?'hff:seg(buff[1][3:0]);
        5:seg7_data=(buff[3][5]&flash_bit)?'hff:~8'b01000000;
        6:seg7_data=(buff[3][6]&flash_bit)?'hff:seg(buff[2][3:0]);
        7:seg7_data=(buff[3][7]&flash_bit)?'hff:seg(buff[2][3:0]);
    endcase
 
    always @(posedge clk) seg7_sel=~(1<<sel);
 
 
    function [7:0] seg;
        input [3:0] data;
        begin
            case(data)
                0: seg = ~8'b00111111;//b11111100;
                1: seg = ~8'b00000110;//01100000;
                2: seg = ~8'b01011011;//11011010;
                3: seg = ~8'b01001111;//11010010;
                4: seg = ~8'b01100110;//1100110;
                5: seg = ~8'b01101101;//10110110;
                6: seg = ~8'b01111101;//10111110;
                7: seg = ~8'b00000111;//11100000;
                8: seg = ~8'b01111111;//11111110;
                9: seg = ~8'b01101111;//11110110;
                10: seg = ~8'b01110111;//11101110;
                11: seg = ~8'b01111100;//00111110;
                12: seg = ~8'b01011000;//00011010;
                13: seg = ~8'b01011110;//01111010;
                14: seg = ~8'b01111001;//10011110;
                15: seg = ~8'b01110001;//10001110;
            endcase
        end
    endfunction
 
 
endmodule
 
 
module seg7led_interface(
input clk,rst,
input [7:0]din,
output reg [7:0]dout,
input wr,rd ,
input [2:0]wr_addr,
input [2:0]rd_addr,
output reg [7:0] seg7_sel,
output reg [7:0] seg7_data
);
reg [7:0]buff[0:7];
 
always @ (posedge clk)if (wr)buff[wr_addr] = din;
 
always @(posedge clk)if (rd)dout = buff[rd_addr] ;else dout=0;
 
reg  [22:0] cntr ;
always @ (posedge clk)
cntr = cntr +1;
reg  [2:0]sel ;
always @ (posedge clk)
sel= cntr[22:19];
 
always @(posedge clk)
  case (sel)
   0:seg7_data=buff[0];
   1:seg7_data=buff[1];
   2:seg7_data=buff[2];
   3:seg7_data=buff[3];
   4:seg7_data=buff[4];
   5:seg7_data=buff[5];
   6:seg7_data=buff[6];
   7:seg7_data=buff[7];
  endcase
  always @(posedge clk)
   seg7_sel = 1<<sel;
 
endmodule
 
 
module sw_interface(
input clk,rst,rd,
input [7:0]sw,
output reg[7:0] dout
);
reg [7:0]sw_r;
always @ (posedge clk)sw_r = sw;
always @ (posedge clk)if (rd)dout=sw_r;else dout =0;
endmodule
 
module key_interface(
input clk,rst,rd,
input [3:0]key,
output reg [7:0]dout
);
reg [3:0]key_r;
always @ (posedge clk)
key_r=key;
 
wire [3:0]w_key;
always @(posedge clk)
begin
dout[7:4]=0;
if (rd)dout[3:0] = w_key;else dout[3:0]=0;
end
 
`define KEY_FSM
`ifdef KEY_FSM
key_fsm ukey0(.clk(clk),.rst(rst),.key_i(key_r[0]),.key_o(w_key[0]),.rd(rd));
key_fsm ukey1(.clk(clk),.rst(rst),.key_i(key_r[1]),.key_o(w_key[1]),.rd(rd));
key_fsm ukey2(.clk(clk),.rst(rst),.key_i(key_r[2]),.key_o(w_key[2]),.rd(rd));
key_fsm ukey3(.clk(clk),.rst(rst),.key_i(key_r[3]),.key_o(w_key[3]),.rd(rd));
`else
        assign w_key = key_r;
`endif
endmodule
 
module beep_interface(
        input clk,rst,rd,wr,
        output reg [7:0]dout ,
        input [7:0]din,
        output  beep
        );
 
        reg beep_en;
        always @ (posedge clk)
                if (rst)beep_en=0;
                else if (wr)
                        beep_en=din[0];
 
        always @(posedge clk)
                if (rd)
                        dout ={7'b0, beep_en};
                else dout=0;
 
  BELL uu(
        .sys_clk(clk),
                    .beep(beep),
                    .beep_en(beep_en)
                    );
 
endmodule
 
`define ADDR_LED 8
`define ADDR_SEG 0
`define ADDR_SW  9
`define ADDR_KEY  10
`define ADDR_BEEP 11
`define ADDR_SECGEN 12
 
module devices_box(
input clk,rst,wr,rd,
input [7:0]din,
input [7:0]sw ,
input [3:0] key,
input [7:0]wr_addr,
input [7:0]rd_addr,
output  [7:0]dout ,
output  [7:0]seg7_sel,
output [7:0]seg7_data,
output [7:0]led
);
 
 
wire [7:0]dout_key;
wire sel_key_wr = wr_addr==`ADDR_KEY;
wire sel_key_rd = rd_addr==`ADDR_KEY;
key_interface u1(
 .clk(clk),
 .rst(rst),
 .rd(rd&sel_key_rd),
 .key(key),
 .dout(dout_key)
);
 
wire [7:0]dout_sw;
 
wire sel_sw_wr  = wr_addr==`ADDR_SW;
wire sel_sw_rd  = rd_addr==`ADDR_SW;
 sw_interface u2(
.clk(clk),
.rst(rst),
.rd(rd&sel_sw_rd),
.sw(sw),
.dout(dout_sw)
);
 
wire [7:0]dout_seg7led;
 
wire sel_seg7_wr = (wr_addr&(~7))== 0;
wire sel_seg7_rd = (rd_addr&(~7))== 0;
 
`ifdef HARD_CLOCK
hard_clock
`else
        `ifdef SEG7_CLOCK_MODEL
        clock_seg7led_interface
        `else
        seg7led_interface
        `endif
`endif
 
clock(
.clk(clk),
.rst(rst),
.din(din ),
.dout(dout_seg7led),
.wr(wr&sel_seg7_wr ),
.rd(rd&sel_seg7_rd ) ,
.rd_addr(rd_addr[2:0]),
.wr_addr(wr_addr[2:0]),
.seg7_sel(seg7_sel),
.seg7_data(seg7_data)
);
 
 
wire [7:0] dout_led;
wire sel_led_wr = rd_addr==`ADDR_LED;
wire sel_led_rd = wr_addr==`ADDR_LED;
led_interface u4(
.clk(clk),
.rst(rst),
.wr(wr&sel_led_wr),
.rd(rd&sel_led_rd),
.din(din),
.dout(dout_led),
.led(led)
);
 
wire [7:0]dout_beep;
 
wire sel_beep_rd = rd_addr==`ADDR_BEEP;
wire sel_beep_wr = wr_addr==`ADDR_BEEP;
 
beep_interface u5(
.clk(clk),
.rst(rst),
.rd(rd&sel_beep_rd),
.wr(wr&sel_beep_wr),
.dout(dout_beep) ,
.din(din),
.beep(beep)
);
 
wire [7:0] dout_secgen ;
wire sel_secgen_rd = rd_addr==`ADDR_SECGEN;
wire sel_secgen_wr = wr_addr==`ADDR_SECGEN;
 
second_gen secgen(
.clk(clk),
.rst(rst),
.rd(rd&sel_secgen_rd),
.din(din),
.wr(wr&sel_secgen_wr),
.dout(dout_secgen)
);
 
assign dout = dout_key | dout_sw |dout_seg7led | dout_led | dout_beep | dout_secgen;
 
endmodule
 
`define CLK_HZ 25000000
 
module second_gen(
        input clk,rst,
        input rd,
        input [7:0]din,
        input wr,
        output reg [7:0]dout
        );
reg [31:0] cntr;
wire time_out =  cntr==(`CLK_HZ-1);
 
wire clr = wr&(din[0]==0);
 
always @(posedge clk)
        if (rst)cntr=0;
        else
                if (time_out)
                        cntr=0;
                else
                        cntr=cntr+1;
 
reg int_req;
always @ (posedge clk)
        if (clr)
        int_req=0;
        else
                int_req = int_req|time_out  ;
 
always @ (posedge clk)
        if(rd)
                dout={7'b0,int_req};
        else dout=0;
 
endmodule
 
module hard_clock(
        input clk,
        input rst,
        input wr,
        input rd,
        input [2:0]rd_addr,
        input [2:0]wr_addr,
        output reg [7:0] seg7_data,
        output reg [7:0] seg7_sel,
        input [7:0]din,
        output reg[7:0]dout
        );
 
        `define CTL_ADDR  3
        `define HOUR_ADDR 2
        `define MIN_ADDR  1
        `define SEC_ADDR  0
 
        reg [7:0]hour;
        reg [7:0]min;
        reg [7:0]sec;
        reg [7:0]ctl;
 
        always @ (posedge clk)if (rst)hour=0; else if (wr&wr_addr==`HOUR_ADDR)hour=din;
        always @ (posedge clk)if (rst)min=0; else  if (wr&wr_addr==`MIN_ADDR)min=din;
        always @ (posedge clk)if (rst)sec=0; else if (wr&wr_addr==`SEC_ADDR)sec=din;
 
        always @(posedge clk)  if (rd)
                case  (rd_addr[2:0])
                        `SEC_ADDR:dout = sec;
                        `MIN_ADDR :dout = min;
                        `HOUR_ADDR:dout = hour;
                        `CTL_ADDR:dout = ctl;
                endcase  else dout=0;
 
        /*the main counter*/
    reg [31:0] seg7_cntr;
    always @(posedge clk)seg7_cntr=seg7_cntr+1;
    wire  [2:0]  sel =seg7_cntr[17:15] ;
        wire flash_bit = seg7_cntr[23];
    always @(posedge clk)
    case (sel[2:0])
        0:seg7_data=(ctl[0]&flash_bit)?'hff:seg(sec[3:0]);
        1:seg7_data=(ctl[1]&flash_bit)?'hff:seg(sec[7:4]);
        2:seg7_data=(ctl[2]&flash_bit)?'hff:~8'b01000000;
        3:seg7_data=(ctl[3]&flash_bit)?'hff:seg(min[3:0]);
        4:seg7_data=(ctl[4]&flash_bit)?'hff:seg(min[7:4]);
        5:seg7_data=(ctl[5]&flash_bit)?'hff:~8'b01000000;
        6:seg7_data=(ctl[6]&flash_bit)?'hff:seg(hour[3:0]);
        7:seg7_data=(ctl[7]&flash_bit)?'hff:seg(hour[7:4]);
    endcase
 
    always @(posedge clk) seg7_sel=~(1<<sel);
    function [7:0] seg;
        input [3:0] data;
        begin
            case(data)
                0: seg = ~8'b00111111;//b11111100;
                1: seg = ~8'b00000110;//01100000;
                2: seg = ~8'b01011011;//11011010;
                3: seg = ~8'b01001111;//11010010;
                4: seg = ~8'b01100110;//1100110;
                5: seg = ~8'b01101101;//10110110;
                6: seg = ~8'b01111101;//10111110;
                7: seg = ~8'b00000111;//11100000;
                8: seg = ~8'b01111111;//11111110;
                9: seg = ~8'b01101111;//11110110;
                10: seg = ~8'b01110111;//11101110;
                11: seg = ~8'b01111100;//00111110;
                12: seg = ~8'b01011000;//00011010;
                13: seg = ~8'b01011110;//01111010;
                14: seg = ~8'b01111001;//10011110;
                15: seg = ~8'b01110001;//10001110;
            endcase
        end
    endfunction
endmodule
 
 
`define KEY_ACTIVE_LEVEL 1
`define TIME_OUT_VALUE 25000000/2
 
module key_fsm(
        input clk,rst,
        input key_i,
        output reg key_o,
        input rd
        );
 
        reg [3:0]curr_state,next_state;
        reg [31:0] cntr ;
 
        always @ (posedge clk)
                if (rst)cntr =0;
                else if (curr_state==1)
                        cntr=cntr+1;
                else cntr=0;
 
        always @ (posedge clk)
                if (rst)curr_state=0;
                else
                        curr_state = next_state;
 
        always @*
           case (curr_state)
                   0:if (key_i==`KEY_ACTIVE_LEVEL&rd)
                           //read a active key value ,then we need delay for a period
                           next_state = 1;else next_state = 0;
                   1:if(cntr==`TIME_OUT_VALUE)
                           next_state = 0;else next_state = 1;
           endcase
 
always @*
        key_o=key_i&(~curr_state);
 
endmodule

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[/] [lwrisc/] [trunk/] [RTL/] [device_box.v] - Blame information for rev 19

Line No.	Rev	Author	Line
1	16	mcupro
2			`define HARD_CLOCK
3
4
5			`ifndef HARD_CLOCK
6			`define SEG7_CLOCK_MODEL
7			`endif
8
9
10			`module led_interface (`
11			`input clk, rst, wr, rd,`
12			`input [7:0] din,`
13			`output reg [7:0] dout,`
14			`output [7:0]led`
15			`);`
16			`reg [7:0] led_data;`
17			`assign led = led_data;`
18
19			`always @ (posedge clk)`
20			`if (rst)`
21			`led_data = 0;`
22			`else if (wr)`
23			`led_data=din;`
24
25			`always@ (posedge clk)`
26			`if (rd)`
27			`dout=led_data;`
28			`else dout = 0;`
29
30
31			`endmodule`
32
33
34			`module clock_seg7led_interface(`
35			`input clk,rst,`
36			`input [7:0]din,`
37			`output reg [7:0]dout,`
38			`input wr,rd ,`
39			`input [2:0]wr_addr,input [2:0]rd_addr,`
40			`output reg [7:0] seg7_sel,seg7_data`
41			`);`
42			`reg [7:0]buff[0:3];`
43			`always @ (posedge clk)`
44			`if (wr)`
45			`buff[wr_addr] = din;`
46
47			`always @(posedge clk)`
48			`if (rd)`
49			`dout = buff[rd_addr] ;`
50			`else dout=0;`
51
52			`/the main counter/`
53			`reg [31:0] seg7_cntr;`
54			`always @(posedge clk)seg7_cntr=seg7_cntr+1;`
55			`wire [2:0] sel =seg7_cntr[17:15] ;`
56			`wire flash_bit = seg7_cntr[21];`
57			`always @(posedge clk)`
58			`case (sel[2:0])`
59			`0:seg7_data=(buff[3][0]&flash_bit)?'hff:seg(buff[0][3:0]);`
60			`1:seg7_data=(buff[3][1]&flash_bit)?'hff:seg(buff[0][3:0]);`
61			`2:seg7_data=(buff[3][2]&flash_bit)?'hff:~8'b01000000;`
62			`3:seg7_data=(buff[3][3]&flash_bit)?'hff:seg(buff[1][3:0]);`
63			`4:seg7_data=(buff[3][4]&flash_bit)?'hff:seg(buff[1][3:0]);`
64			`5:seg7_data=(buff[3][5]&flash_bit)?'hff:~8'b01000000;`
65			`6:seg7_data=(buff[3][6]&flash_bit)?'hff:seg(buff[2][3:0]);`
66			`7:seg7_data=(buff[3][7]&flash_bit)?'hff:seg(buff[2][3:0]);`
67			`endcase`
68
69			`always @(posedge clk) seg7_sel=~(1<<sel);`
70
71
72			`function [7:0] seg;`
73			`input [3:0] data;`
74			`begin`
75			`case(data)`
76			`0: seg = ~8'b00111111;//b11111100;`
77			`1: seg = ~8'b00000110;//01100000;`
78			`2: seg = ~8'b01011011;//11011010;`
79			`3: seg = ~8'b01001111;//11010010;`
80			`4: seg = ~8'b01100110;//1100110;`
81			`5: seg = ~8'b01101101;//10110110;`
82			`6: seg = ~8'b01111101;//10111110;`
83			`7: seg = ~8'b00000111;//11100000;`
84			`8: seg = ~8'b01111111;//11111110;`
85			`9: seg = ~8'b01101111;//11110110;`
86			`10: seg = ~8'b01110111;//11101110;`
87			`11: seg = ~8'b01111100;//00111110;`
88			`12: seg = ~8'b01011000;//00011010;`
89			`13: seg = ~8'b01011110;//01111010;`
90			`14: seg = ~8'b01111001;//10011110;`
91			`15: seg = ~8'b01110001;//10001110;`
92			`endcase`
93			`end`
94			`endfunction`
95
96
97			`endmodule`
98
99
100			`module seg7led_interface(`
101			`input clk,rst,`
102			`input [7:0]din,`
103			`output reg [7:0]dout,`
104			`input wr,rd ,`
105			`input [2:0]wr_addr,`
106			`input [2:0]rd_addr,`
107			`output reg [7:0] seg7_sel,`
108			`output reg [7:0] seg7_data`
109			`);`
110			`reg [7:0]buff[0:7];`
111
112			`always @ (posedge clk)if (wr)buff[wr_addr] = din;`
113
114			`always @(posedge clk)if (rd)dout = buff[rd_addr] ;else dout=0;`
115
116			`reg [22:0] cntr ;`
117			`always @ (posedge clk)`
118			`cntr = cntr +1;`
119			`reg [2:0]sel ;`
120			`always @ (posedge clk)`
121			`sel= cntr[22:19];`
122
123			`always @(posedge clk)`
124			`case (sel)`
125			`0:seg7_data=buff[0];`
126			`1:seg7_data=buff[1];`
127			`2:seg7_data=buff[2];`
128			`3:seg7_data=buff[3];`
129			`4:seg7_data=buff[4];`
130			`5:seg7_data=buff[5];`
131			`6:seg7_data=buff[6];`
132			`7:seg7_data=buff[7];`
133			`endcase`
134			`always @(posedge clk)`
135			`seg7_sel = 1<<sel;`
136
137			`endmodule`
138
139
140			`module sw_interface(`
141			`input clk,rst,rd,`
142			`input [7:0]sw,`
143			`output reg[7:0] dout`
144			`);`
145			`reg [7:0]sw_r;`
146			`always @ (posedge clk)sw_r = sw;`
147			`always @ (posedge clk)if (rd)dout=sw_r;else dout =0;`
148			`endmodule`
149
150			`module key_interface(`
151			`input clk,rst,rd,`
152			`input [3:0]key,`
153			`output reg [7:0]dout`
154			`);`
155			`reg [3:0]key_r;`
156			`always @ (posedge clk)`
157			`key_r=key;`
158
159			`wire [3:0]w_key;`
160			`always @(posedge clk)`
161			`begin`
162			`dout[7:4]=0;`
163			`if (rd)dout[3:0] = w_key;else dout[3:0]=0;`
164			`end`
165
166			`define KEY_FSM
167			`ifdef KEY_FSM
168			`key_fsm ukey0(.clk(clk),.rst(rst),.key_i(key_r[0]),.key_o(w_key[0]),.rd(rd));`
169			`key_fsm ukey1(.clk(clk),.rst(rst),.key_i(key_r[1]),.key_o(w_key[1]),.rd(rd));`
170			`key_fsm ukey2(.clk(clk),.rst(rst),.key_i(key_r[2]),.key_o(w_key[2]),.rd(rd));`
171			`key_fsm ukey3(.clk(clk),.rst(rst),.key_i(key_r[3]),.key_o(w_key[3]),.rd(rd));`
172			`else
173			`assign w_key = key_r;`
174			`endif
175			`endmodule`
176
177			`module beep_interface(`
178			`input clk,rst,rd,wr,`
179			`output reg [7:0]dout ,`
180			`input [7:0]din,`
181			`output beep`
182			`);`
183
184			`reg beep_en;`
185			`always @ (posedge clk)`
186			`if (rst)beep_en=0;`
187			`else if (wr)`
188			`beep_en=din[0];`
189
190			`always @(posedge clk)`
191			`if (rd)`
192			`dout ={7'b0, beep_en};`
193			`else dout=0;`
194
195			`BELL uu(`
196			`.sys_clk(clk),`
197			`.beep(beep),`
198			`.beep_en(beep_en)`
199			`);`
200
201			`endmodule`
202
203			`define ADDR_LED 8
204			`define ADDR_SEG 0
205			`define ADDR_SW 9
206			`define ADDR_KEY 10
207			`define ADDR_BEEP 11
208			`define ADDR_SECGEN 12
209
210			`module devices_box(`
211			`input clk,rst,wr,rd,`
212			`input [7:0]din,`
213			`input [7:0]sw ,`
214			`input [3:0] key,`
215			`input [7:0]wr_addr,`
216			`input [7:0]rd_addr,`
217			`output [7:0]dout ,`
218			`output [7:0]seg7_sel,`
219			`output [7:0]seg7_data,`
220			`output [7:0]led`
221			`);`
222
223
224			`wire [7:0]dout_key;`
225			wire sel_key_wr = wr_addr==`ADDR_KEY;
226			wire sel_key_rd = rd_addr==`ADDR_KEY;
227			`key_interface u1(`
228			`.clk(clk),`
229			`.rst(rst),`
230			`.rd(rd&sel_key_rd),`
231			`.key(key),`
232			`.dout(dout_key)`
233			`);`
234
235			`wire [7:0]dout_sw;`
236
237			wire sel_sw_wr = wr_addr==`ADDR_SW;
238			wire sel_sw_rd = rd_addr==`ADDR_SW;
239			`sw_interface u2(`
240			`.clk(clk),`
241			`.rst(rst),`
242			`.rd(rd&sel_sw_rd),`
243			`.sw(sw),`
244			`.dout(dout_sw)`
245			`);`
246
247			`wire [7:0]dout_seg7led;`
248
249			`wire sel_seg7_wr = (wr_addr&(~7))== 0;`
250			`wire sel_seg7_rd = (rd_addr&(~7))== 0;`
251
252			`ifdef HARD_CLOCK
253			`hard_clock`
254			`else
255			`ifdef SEG7_CLOCK_MODEL
256			`clock_seg7led_interface`
257			`else
258			`seg7led_interface`
259			`endif
260			`endif
261
262			`clock(`
263			`.clk(clk),`
264			`.rst(rst),`
265			`.din(din ),`
266			`.dout(dout_seg7led),`
267			`.wr(wr&sel_seg7_wr ),`
268			`.rd(rd&sel_seg7_rd ) ,`
269			`.rd_addr(rd_addr[2:0]),`
270			`.wr_addr(wr_addr[2:0]),`
271			`.seg7_sel(seg7_sel),`
272			`.seg7_data(seg7_data)`
273			`);`
274
275
276			`wire [7:0] dout_led;`
277			wire sel_led_wr = rd_addr==`ADDR_LED;
278			wire sel_led_rd = wr_addr==`ADDR_LED;
279			`led_interface u4(`
280			`.clk(clk),`
281			`.rst(rst),`
282			`.wr(wr&sel_led_wr),`
283			`.rd(rd&sel_led_rd),`
284			`.din(din),`
285			`.dout(dout_led),`
286			`.led(led)`
287			`);`
288
289			`wire [7:0]dout_beep;`
290
291			wire sel_beep_rd = rd_addr==`ADDR_BEEP;
292			wire sel_beep_wr = wr_addr==`ADDR_BEEP;
293
294			`beep_interface u5(`
295			`.clk(clk),`
296			`.rst(rst),`
297			`.rd(rd&sel_beep_rd),`
298			`.wr(wr&sel_beep_wr),`
299			`.dout(dout_beep) ,`
300			`.din(din),`
301			`.beep(beep)`
302			`);`
303
304			`wire [7:0] dout_secgen ;`
305			wire sel_secgen_rd = rd_addr==`ADDR_SECGEN;
306			wire sel_secgen_wr = wr_addr==`ADDR_SECGEN;
307
308			`second_gen secgen(`
309			`.clk(clk),`
310			`.rst(rst),`
311			`.rd(rd&sel_secgen_rd),`
312			`.din(din),`
313			`.wr(wr&sel_secgen_wr),`
314			`.dout(dout_secgen)`
315			`);`
316
317			`assign dout = dout_key \| dout_sw \|dout_seg7led \| dout_led \| dout_beep \| dout_secgen;`
318
319			`endmodule`
320
321			`define CLK_HZ 25000000
322
323			`module second_gen(`
324			`input clk,rst,`
325			`input rd,`
326			`input [7:0]din,`
327			`input wr,`
328			`output reg [7:0]dout`
329			`);`
330			`reg [31:0] cntr;`
331			wire time_out = cntr==(`CLK_HZ-1);
332
333			`wire clr = wr&(din[0]==0);`
334
335			`always @(posedge clk)`
336			`if (rst)cntr=0;`
337			`else`
338			`if (time_out)`
339			`cntr=0;`
340			`else`
341			`cntr=cntr+1;`
342
343			`reg int_req;`
344			`always @ (posedge clk)`
345			`if (clr)`
346			`int_req=0;`
347			`else`
348			`int_req = int_req\|time_out ;`
349
350			`always @ (posedge clk)`
351			`if(rd)`
352			`dout={7'b0,int_req};`
353			`else dout=0;`
354
355			`endmodule`
356
357			`module hard_clock(`
358			`input clk,`
359			`input rst,`
360			`input wr,`
361			`input rd,`
362			`input [2:0]rd_addr,`
363			`input [2:0]wr_addr,`
364			`output reg [7:0] seg7_data,`
365			`output reg [7:0] seg7_sel,`
366			`input [7:0]din,`
367			`output reg[7:0]dout`
368			`);`
369
370			`define CTL_ADDR 3
371			`define HOUR_ADDR 2
372			`define MIN_ADDR 1
373			`define SEC_ADDR 0
374
375			`reg [7:0]hour;`
376			`reg [7:0]min;`
377			`reg [7:0]sec;`
378			`reg [7:0]ctl;`
379
380			always @ (posedge clk)if (rst)hour=0; else if (wr&wr_addr==`HOUR_ADDR)hour=din;
381			always @ (posedge clk)if (rst)min=0; else if (wr&wr_addr==`MIN_ADDR)min=din;
382			always @ (posedge clk)if (rst)sec=0; else if (wr&wr_addr==`SEC_ADDR)sec=din;
383
384			`always @(posedge clk) if (rd)`
385			`case (rd_addr[2:0])`
386			`SEC_ADDR:dout = sec;
387			`MIN_ADDR :dout = min;
388			`HOUR_ADDR:dout = hour;
389			`CTL_ADDR:dout = ctl;
390			`endcase else dout=0;`
391
392			`/the main counter/`
393			`reg [31:0] seg7_cntr;`
394			`always @(posedge clk)seg7_cntr=seg7_cntr+1;`
395			`wire [2:0] sel =seg7_cntr[17:15] ;`
396			`wire flash_bit = seg7_cntr[23];`
397			`always @(posedge clk)`
398			`case (sel[2:0])`
399			`0:seg7_data=(ctl[0]&flash_bit)?'hff:seg(sec[3:0]);`
400			`1:seg7_data=(ctl[1]&flash_bit)?'hff:seg(sec[7:4]);`
401			`2:seg7_data=(ctl[2]&flash_bit)?'hff:~8'b01000000;`
402			`3:seg7_data=(ctl[3]&flash_bit)?'hff:seg(min[3:0]);`
403			`4:seg7_data=(ctl[4]&flash_bit)?'hff:seg(min[7:4]);`
404			`5:seg7_data=(ctl[5]&flash_bit)?'hff:~8'b01000000;`
405			`6:seg7_data=(ctl[6]&flash_bit)?'hff:seg(hour[3:0]);`
406			`7:seg7_data=(ctl[7]&flash_bit)?'hff:seg(hour[7:4]);`
407			`endcase`
408
409			`always @(posedge clk) seg7_sel=~(1<<sel);`
410			`function [7:0] seg;`
411			`input [3:0] data;`
412			`begin`
413			`case(data)`
414			`0: seg = ~8'b00111111;//b11111100;`
415			`1: seg = ~8'b00000110;//01100000;`
416			`2: seg = ~8'b01011011;//11011010;`
417			`3: seg = ~8'b01001111;//11010010;`
418			`4: seg = ~8'b01100110;//1100110;`
419			`5: seg = ~8'b01101101;//10110110;`
420			`6: seg = ~8'b01111101;//10111110;`
421			`7: seg = ~8'b00000111;//11100000;`
422			`8: seg = ~8'b01111111;//11111110;`
423			`9: seg = ~8'b01101111;//11110110;`
424			`10: seg = ~8'b01110111;//11101110;`
425			`11: seg = ~8'b01111100;//00111110;`
426			`12: seg = ~8'b01011000;//00011010;`
427			`13: seg = ~8'b01011110;//01111010;`
428			`14: seg = ~8'b01111001;//10011110;`
429			`15: seg = ~8'b01110001;//10001110;`
430			`endcase`
431			`end`
432			`endfunction`
433			`endmodule`
434
435
436			`define KEY_ACTIVE_LEVEL 1
437			`define TIME_OUT_VALUE 25000000/2
438
439			`module key_fsm(`
440			`input clk,rst,`
441			`input key_i,`
442			`output reg key_o,`
443			`input rd`
444			`);`
445
446			`reg [3:0]curr_state,next_state;`
447			`reg [31:0] cntr ;`
448
449			`always @ (posedge clk)`
450			`if (rst)cntr =0;`
451			`else if (curr_state==1)`
452			`cntr=cntr+1;`
453			`else cntr=0;`
454
455			`always @ (posedge clk)`
456			`if (rst)curr_state=0;`
457			`else`
458			`curr_state = next_state;`
459
460			`always @*`
461			`case (curr_state)`
462			0:if (key_i==`KEY_ACTIVE_LEVEL&rd)
463			`//read a active key value ,then we need delay for a period`
464			`next_state = 1;else next_state = 0;`
465			1:if(cntr==`TIME_OUT_VALUE)
466			`next_state = 0;else next_state = 1;`
467			`endcase`
468
469			`always @*`
470			`key_o=key_i&(~curr_state);`
471
472			`endmodule`