OpenCores
URL https://opencores.org/ocsvn/lwrisc/lwrisc/trunk

Subversion Repositories lwrisc

[/] [lwrisc/] [trunk/] [RTL/] [mem_man.v] - Blame information for rev 16

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 16 mcupro
 
2 7 mcupro
`include "clairisc_def.h"
3 16 mcupro
 
4 7 mcupro
`define ADDR_STATUS                3
5 16 mcupro
`define ADDR_DVC_DATA              0
6
`define ADDR_DVC_WR_ADDR           2
7
`define ADDR_DVC_RD_ADDR           1
8 7 mcupro
 
9 16 mcupro
/*
10
#define    PORT_DATA        *(unsigned char*)0
11
#define    IN_PORT_ADDR     *(unsigned char*)1
12
#define    OUT_PORT_ADDR    *(unsigned char*)2
13
#define    STATUS           *(unsigned char*)3
14
*/
15
 
16
module  mem_man(
17 7 mcupro
        input wr_en,
18
        input clk,
19 16 mcupro
        input rst,
20
 
21 7 mcupro
        input ci,
22
        input zi,
23
        input z_wr,
24
        input c_wr,
25 16 mcupro
 
26
                output reg [7:0] dout,
27 7 mcupro
        output co,
28
        input [7:0] din     ,
29
        output reg [7:0]status     ,
30
 
31 16 mcupro
        input  [4:0] rd_addr,
32
        input  [4:0] wr_addr ,
33
 
34
        output reg [7:0]dvc_wr_addr,
35
        output reg [7:0]dvc_rd_addr,
36
        output reg  [7:0]data_mem2dvc,
37
        input [7:0]data_dvc2mem,
38
        output reg dvc_wr       ,
39
        output /*reg */dvc_rd
40
);
41 7 mcupro
 
42 16 mcupro
 
43 7 mcupro
    reg wr_en_r;
44 16 mcupro
    reg [7:0] din_r;
45
        reg [4:0] wr_addr_r;
46
    reg [4:0] rd_addr_r;
47 7 mcupro
 
48
    always @(posedge clk)
49 16 mcupro
    begin
50 7 mcupro
        wr_addr_r<=wr_addr;
51
        rd_addr_r<=rd_addr;
52
        wr_en_r<=wr_en;
53
        din_r<=din;
54 16 mcupro
    end
55
 
56 7 mcupro
    wire [7:0] ram_q ;
57
    wire [7:0] alt_ram_q;
58
 
59 16 mcupro
 //   `ifdef SIM        
60 7 mcupro
    sim_reg_file i_reg_file(
61
                     .data(din),
62
                     .wren(wr_en),
63 16 mcupro
                     .wraddress(wr_addr[4:0]),
64
                     .rdaddress(rd_addr[4:0]),
65 7 mcupro
                     .clock(clk),
66
                     .q(alt_ram_q));
67 16 mcupro
 /*   `else
68 7 mcupro
    ram128x8 i_reg_file(
69
                 .data(din),
70
                 .wren(wr_en),
71
                 .wraddress(wr_addr),
72
                 .rdaddress(rd_addr),
73
                 .clock(clk),
74
                 .q(alt_ram_q)
75 16 mcupro
             );
76 7 mcupro
    `endif
77 16 mcupro
  */
78
    assign ram_q =/* ((wr_addr_r==rd_addr_r)&&(wr_en_r))?din_r:*/alt_ram_q;
79 7 mcupro
 
80
    /*status register*/
81
    wire write_status = wr_addr[4:0] ==`ADDR_STATUS && wr_en;
82
    always@(posedge clk)
83
    begin
84
        if (rst)status<=8'h3f;//default value
85
        else
86
            if (write_status)status<=din;
87
            else
88
            begin
89
                if (c_wr)status[0]<=ci;
90 16 mcupro
                                if (z_wr)status[2]<=zi;
91 7 mcupro
            end
92 16 mcupro
    end
93
 
94 7 mcupro
    assign co = status[0];
95
 
96 16 mcupro
    `ifdef SIM
97
    always@(*)
98 7 mcupro
    begin
99 16 mcupro
        if (wr_en)
100
            $display("hex=>%x< char=>%x<",wr_addr[4:0],din[7:0]);
101 7 mcupro
    end
102 16 mcupro
    `endif
103
 
104
    always@(*)
105
    case(rd_addr_r[4:0])
106
                `ADDR_STATUS:dout = status;
107
                `ADDR_DVC_DATA :dout  = data_dvc2mem ;
108 7 mcupro
        default dout = ram_q ;
109 16 mcupro
    endcase
110
 
111
        always @ (posedge clk) if ((wr_addr[4:0]==`ADDR_DVC_WR_ADDR)&&(1==wr_en))dvc_wr_addr <=din;
112
        always @ (posedge clk)  if ((wr_addr[4:0]==`ADDR_DVC_RD_ADDR)&&(1==wr_en))  dvc_rd_addr <=din;
113
        always @ (posedge clk) if ((wr_addr[4:0]==`ADDR_DVC_DATA )&&(1==wr_en)) data_mem2dvc <=din;
114
        always  @ (*) dvc_wr  <=wr_en_r&(wr_addr==0);
115
        assign  dvc_rd   =      1'b1  ;
116
 
117
 
118 7 mcupro
endmodule
119
 
120
 
121
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.