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[/] [lwrisc/] [trunk/] [RTL/] [mem_man.v] - Blame information for rev 7

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`include "clairisc_def.h"
 
`define ADDR_FSR                   4
`define ADDR_STATUS                3
`define ADDR_IN0               5
`define ADDR_IN1               1
`define ADDR_OUT0                6
`define ADDR_OUT1                7
 
module wb_mem_man(
        input wr_en,
        input clk,
        input rst,
        input ci,
        input zi,
        input z_wr,
        input c_wr,
        output reg [7:0] dout,
        output co,
        output [1:0] bank,
        input [7:0] din     ,
        output reg [7:0]status     ,
 
        input  [6:0] rd_addr,
        input  [6:0] wr_addr ,
 
        input  [7:0] in0,
        input  [7:0] in1,
        output reg [7:0] out0,
        output reg [7:0] out1
    );
    reg wr_en_r;
    reg [6:0] din_r, wr_addr_r;
    reg [6:0] rd_addr_r;
 
    always @(posedge clk)
    begin  //used to bypass the data
        //which wrote anf then be read in the followwing period
        wr_addr_r<=wr_addr;
        rd_addr_r<=rd_addr;
        wr_en_r<=wr_en;
        din_r<=din;
    end
 
    wire [7:0] ram_q ;
    wire [7:0] alt_ram_q;
 
    `ifdef SIM
 
    sim_reg_file i_reg_file(
                     .data(din),
                     .wren(wr_en),
                     .wraddress(wr_addr),
                     .rdaddress(rd_addr),
                     .clock(clk),
                     .q(alt_ram_q));
    `else
    ram128x8 i_reg_file(
                 .data(din),
                 .wren(wr_en),
                 .wraddress(wr_addr),
                 .rdaddress(rd_addr),
                 .clock(clk),
                 .q(alt_ram_q)
             );
    `endif
 
    assign ram_q = ((wr_addr_r==rd_addr_r)&&(wr_en_r))?din_r:alt_ram_q;
 
    /*status register*/
    wire write_status = wr_addr[4:0] ==`ADDR_STATUS && wr_en;
    always@(posedge clk)
    begin
        if (rst)status<=8'h3f;//default value
        else
            if (write_status)status<=din;
            else
            begin
                if (c_wr)status[0]<=ci;
                if (z_wr)status[2]<=zi;
            end
    end
 
    assign co = status[0];
 
    `ifdef SIM
 
    wire write_disp = wr_addr == 'h1f && wr_en;
    always@(posedge clk)
    begin
        if (write_disp)
            $display("hex=>%x< char=>%c<",din,din);
    end
    `endif
 
    /*fsr register*/
    reg [7:0] fsr;
    assign bank = fsr[6:5];
    wire write_fsr = wr_addr[4:0] == `ADDR_FSR &&wr_en ;
    always@(posedge clk)
    begin
        if (rst)fsr<=0;
        else  if(write_fsr) fsr<=din[7:0];
    end
 
    /*latch the input data*/
    reg [7:0]     reg_in1,reg_in0;
    always@(posedge clk) reg_in0<=in0;
    always@(posedge clk) reg_in1<=in1;
 
    /*data output latch */
    wire write_out0 = wr_addr[4:0] == `ADDR_OUT0 &&wr_en ;
    always@(posedge clk)
    begin
        if (rst)out0<=0;
        else  if(write_out0)out0<=din[7:0];
    end
 
    /*data output latch */
    wire write_out1 = wr_addr[4:0] == `ADDR_OUT1 &&wr_en ;
    always@(posedge clk)
    begin
        if (rst)out1<=0;
        else  if(write_out1)out1<=din[7:0];
    end
 
    /*data bus output select logic*/
    always@(*)//select status,fsr,wb_data,ram,wb_din
    case(rd_addr_r[4:0])
        `ADDR_FSR:dout    = fsr;
        `ADDR_STATUS:dout = status;
        `ADDR_IN0:dout    = reg_in0;
        `ADDR_IN1:dout    = reg_in1;
        default dout = ram_q ;
    endcase
endmodule
 
 
 

Line No.	Rev	Author	Line
1	7	mcupro	`include "clairisc_def.h"
2
3			`define ADDR_FSR 4
4			`define ADDR_STATUS 3
5			`define ADDR_IN0 5
6			`define ADDR_IN1 1
7			`define ADDR_OUT0 6
8			`define ADDR_OUT1 7
9
10			`module wb_mem_man(`
11			`input wr_en,`
12			`input clk,`
13			`input rst,`
14			`input ci,`
15			`input zi,`
16			`input z_wr,`
17			`input c_wr,`
18			`output reg [7:0] dout,`
19			`output co,`
20			`output [1:0] bank,`
21			`input [7:0] din ,`
22			`output reg [7:0]status ,`
23
24			`input [6:0] rd_addr,`
25			`input [6:0] wr_addr ,`
26
27			`input [7:0] in0,`
28			`input [7:0] in1,`
29			`output reg [7:0] out0,`
30			`output reg [7:0] out1`
31			`);`
32			`reg wr_en_r;`
33			`reg [6:0] din_r, wr_addr_r;`
34			`reg [6:0] rd_addr_r;`
35
36			`always @(posedge clk)`
37			`begin //used to bypass the data`
38			`//which wrote anf then be read in the followwing period`
39			`wr_addr_r<=wr_addr;`
40			`rd_addr_r<=rd_addr;`
41			`wr_en_r<=wr_en;`
42			`din_r<=din;`
43			`end`
44
45			`wire [7:0] ram_q ;`
46			`wire [7:0] alt_ram_q;`
47
48			`ifdef SIM
49
50			`sim_reg_file i_reg_file(`
51			`.data(din),`
52			`.wren(wr_en),`
53			`.wraddress(wr_addr),`
54			`.rdaddress(rd_addr),`
55			`.clock(clk),`
56			`.q(alt_ram_q));`
57			`else
58			`ram128x8 i_reg_file(`
59			`.data(din),`
60			`.wren(wr_en),`
61			`.wraddress(wr_addr),`
62			`.rdaddress(rd_addr),`
63			`.clock(clk),`
64			`.q(alt_ram_q)`
65			`);`
66			`endif
67
68			`assign ram_q = ((wr_addr_r==rd_addr_r)&&(wr_en_r))?din_r:alt_ram_q;`
69
70			`/status register/`
71			wire write_status = wr_addr[4:0] ==`ADDR_STATUS && wr_en;
72			`always@(posedge clk)`
73			`begin`
74			`if (rst)status<=8'h3f;//default value`
75			`else`
76			`if (write_status)status<=din;`
77			`else`
78			`begin`
79			`if (c_wr)status[0]<=ci;`
80			`if (z_wr)status[2]<=zi;`
81			`end`
82			`end`
83
84			`assign co = status[0];`
85
86			`ifdef SIM
87
88			`wire write_disp = wr_addr == 'h1f && wr_en;`
89			`always@(posedge clk)`
90			`begin`
91			`if (write_disp)`
92			`$display("hex=>%x< char=>%c<",din,din);`
93			`end`
94			`endif
95
96			`/fsr register/`
97			`reg [7:0] fsr;`
98			`assign bank = fsr[6:5];`
99			wire write_fsr = wr_addr[4:0] == `ADDR_FSR &&wr_en ;
100			`always@(posedge clk)`
101			`begin`
102			`if (rst)fsr<=0;`
103			`else if(write_fsr) fsr<=din[7:0];`
104			`end`
105
106			`/latch the input data/`
107			`reg [7:0] reg_in1,reg_in0;`
108			`always@(posedge clk) reg_in0<=in0;`
109			`always@(posedge clk) reg_in1<=in1;`
110
111			`/data output latch /`
112			wire write_out0 = wr_addr[4:0] == `ADDR_OUT0 &&wr_en ;
113			`always@(posedge clk)`
114			`begin`
115			`if (rst)out0<=0;`
116			`else if(write_out0)out0<=din[7:0];`
117			`end`
118
119			`/data output latch /`
120			wire write_out1 = wr_addr[4:0] == `ADDR_OUT1 &&wr_en ;
121			`always@(posedge clk)`
122			`begin`
123			`if (rst)out1<=0;`
124			`else if(write_out1)out1<=din[7:0];`
125			`end`
126
127			`/data bus output select logic/`
128			`always@(*)//select status,fsr,wb_data,ram,wb_din`
129			`case(rd_addr_r[4:0])`
130			`ADDR_FSR:dout = fsr;
131			`ADDR_STATUS:dout = status;
132			`ADDR_IN0:dout = reg_in0;
133			`ADDR_IN1:dout = reg_in1;
134			`default dout = ram_q ;`
135			`endcase`
136			`endmodule`
137
138
139

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[/] [lwrisc/] [trunk/] [RTL/] [mem_man.v] - Blame information for rev 7