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[/] [lwrisc/] [trunk/] [RTL/] [risc_core.v] - Blame information for rev 19

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`include "clairisc_def.h"
module ClaiRISC_core (
        input clk,
        input rst,
        output [7:0]dvc_wr_addr,
        output [7:0]dvc_rd_addr,
        output  [7:0]data_mem2dvc,
        input [7:0]data_dvc2mem,
        output dvc_wr  ,
        output dvc_rd
    );
 
    supply0 GND;
    wire w_c_2alu;
    wire w_c_2mem;
    reg w_c_wr;
    reg w_c_wr_r;
    reg w_mem_wr;
    reg w_mem_wr_r;
    reg w_muxa_ctl;
    reg w_muxa_ctl_r;
    reg w_muxb_ctl;
    reg w_reg_muxb_r;
    reg w_skip;
    reg w_w_wr;
    reg w_w_wr_r;
        wire w_z;
    reg w_z_wr;
    reg w_z_wr_r;
    reg [7:0] w_alu_in_a;
    reg [7:0] w_alu_in_b;
    reg [4:0] w_alu_op;
    reg [4:0] w_alu_op_r;
    reg [7:0] w_alu_res;
    wire [1:0] w_bank;
    reg [7:0] w_bd_r;
    reg [1:0] w_brc_ctl;
    reg [1:0] w_br_ctl_r;
    reg [8:0] w_ek_r;
    wire [7:0] w_file_o;
    wire [11:0] w_ins;
    reg [10:0] w_pc;
    reg [2:0] w_pc_gen_ctl;
    reg [10:0] w_pc_nxt;
    wire [4:0] w_rd_addr;
    wire [7:0] w_status;
    reg [1:0] w_stk_op;
    wire [10:0] w_stk_pc;
    reg[4:0] w_wbadd_r;
    wire [4:0] w_wd_addr;
    reg [7:0] w_wreg;
    wire [4:0] w_wr_addr;
 
    always @(posedge clk)
        w_pc<=w_pc_nxt;
 
    reg [10:0]   stack1, stack2,stack3, stack4;
 
        initial begin
        stack1=0;
        stack2=0;
        stack3=0;
        stack4=0;
        end
 
    assign w_stk_pc = stack1;
 
    always @(posedge clk)
    begin
        case (w_stk_op)
            `STK_PSH    :// PUSH stack
            begin
                stack4 <= stack3;
                stack3 <= stack2;
                stack2 <= stack1;
                stack1 <= w_pc+1;
            end
            `STK_POP    :// POP stack
            begin
                stack1 <= stack2;
                                stack2 <= stack3;
                stack3 <= stack4;
                        end
            //  default ://do nothing
        endcase
    end
 
    assign         w_rd_addr =w_wd_addr[4:0];
 
    mem_man   mem_man
                 (
                     .c_wr(w_c_wr_r),
                     .ci(w_c_2mem),
                     .clk(clk),
                     .co(w_c_2alu),
                     .din(w_alu_res),
                     .dout(w_file_o),
                     .rd_addr(w_rd_addr[4:0]),
                     .rst(rst),
                     .status(w_status),
                     .wr_addr(w_wr_addr[4:0]),
                     .wr_en(w_mem_wr_r),
                     .z_wr(w_z_wr_r),
                     .zi(w_z),
                                         .dvc_wr_addr(dvc_wr_addr),
                         .dvc_rd_addr(dvc_rd_addr),
                         .data_mem2dvc(data_mem2dvc),
                         .data_dvc2mem(data_dvc2mem),
                         .dvc_wr(dvc_wr),
                                         .dvc_rd(dvc_rd)
                 );
 
    always @(posedge clk)
        if (w_skip)
            w_alu_op_r<=0;
        else
            w_alu_op_r<=w_alu_op;
 
    always@(posedge clk)
        if (w_skip)       w_br_ctl_r<=0;
        else w_br_ctl_r<=w_brc_ctl;
 
    always@(posedge clk)
        if (w_skip)       w_z_wr_r<=0;
        else  w_z_wr_r<=w_z_wr;
 
    always @ (posedge clk)
        if (w_skip)
            w_c_wr_r<=0;
        else
            w_c_wr_r<=w_c_wr;
 
    always @(posedge clk)
        if(w_skip)
            w_mem_wr_r<=0;
        else
            w_mem_wr_r<=w_mem_wr;
 
    always @(posedge clk)
        if (w_w_wr_r)
            w_wreg<=w_alu_res;
 
        always @ (posedge clk)
                w_bd_r<=1<<w_ins[7:5];
 
    always @(posedge clk)
                w_w_wr_r <=w_w_wr ;
 
    always @(posedge clk)
        w_ek_r<=w_ins[8:0];
 
    assign w_wd_addr = w_ins[4:0];
 
    always@(posedge clk)
        w_wbadd_r<=w_wd_addr;
 
 
           assign w_wr_addr =  w_wbadd_r[4:0];
    reg         addercout;
    always @(*) begin
        case (w_alu_op_r) // synsys parallel_case
            `ALU_ADD:   {addercout,  w_alu_res}  = w_alu_in_a + w_alu_in_b;
            `ALU_SUB:  {addercout,  w_alu_res}  = w_alu_in_b - w_alu_in_a;
            `ALU_ROR:  {addercout,  w_alu_res}  = {w_alu_in_b[0], w_c_2alu, w_alu_in_b[7:1]};
            `ALU_ROL:  {addercout,  w_alu_res}  = {w_alu_in_b[7],w_alu_in_b[6:0], w_c_2alu};
            `ALU_OR:   {addercout,  w_alu_res}  = {1'bx, w_alu_in_a | w_alu_in_b};
            `ALU_XOR:  {addercout,  w_alu_res}  = {1'bx, w_alu_in_a ^ w_alu_in_b};
            `ALU_COM:  {addercout,  w_alu_res}  = {1'bx, ~w_alu_in_b};
            `ALU_SWAP: {addercout,  w_alu_res}  = {1'bx, w_alu_in_b[3:0], w_alu_in_b[7:4]};
            `ALU_AND,//:  {addercout,  y}  = {1'bx, a & b};
            `ALU_BTFSC,//:  {addercout,  y}  = {1'bx, a & b };
            `ALU_BTFSS: {addercout,  w_alu_res}  = {1'bx, w_alu_in_a & w_alu_in_b };
            `ALU_DEC:   {addercout,  w_alu_res}  = {1'bx, w_alu_in_b - 1};
            `ALU_INC:   {addercout,  w_alu_res}  = {1'bx, 1 + w_alu_in_b};
            `ALU_PA :   {addercout,  w_alu_res}  = {1'bx, w_alu_in_a};
            `ALU_PB :   {addercout,  w_alu_res}  = {1'bx, w_alu_in_b};
            `ALU_BSF :  {addercout,  w_alu_res}  = {1'Bx,w_alu_in_a | w_alu_in_b};
            `ALU_BCF :  {addercout,  w_alu_res}  = {1'bx,~w_alu_in_a & w_alu_in_b};
            default:     {addercout, w_alu_res}  = {1'bx, 8'h00};
        endcase
    end
    assign  w_z = (w_alu_res== 8'h00);
    assign  w_c_2mem =  (w_alu_op_r == `ALU_SUB) ?  ~addercout : addercout;
 
    always @(posedge clk)
        if( w_skip)      w_muxa_ctl_r<=0;
        else
            w_muxa_ctl_r<=       w_muxa_ctl;
 
    always @ (posedge clk)
        if (w_skip)              w_reg_muxb_r<=0;
        else
            w_reg_muxb_r<=      w_muxb_ctl;
 
 
    always@(*)
        if (w_muxa_ctl_r==`MUXA_W)
            w_alu_in_a=w_wreg;
        else
            w_alu_in_a=w_bd_r;
 
 
    always @(*)
        if (w_reg_muxb_r==`MUXB_EK)
            w_alu_in_b=w_ek_r[7:0];
        else w_alu_in_b=w_file_o;
 
    always @(*)
    case (w_br_ctl_r)
        //Z==1 means the ALU result is 0
        //Z==0 means the ALU result is not 0
        `BG_ZERO :w_skip =  (w_z==1);   //if the ALU result is 0 then the next instrction will be discarded
        `BG_NZERO :w_skip = (w_z==0);     //if the ALU result is not zero
        //then skip the next instruction
        default w_skip = 0;
    endcase
 
com_prom program_rom
         (
             .clk(clk),
             .dout(w_ins),
             .rd_addr(w_pc_nxt)
         );
 
    always @ (*)
        if (rst)
            w_pc_nxt=0;//'h1ff;            //THE RST ENTRY
        else
            if(w_skip)
            begin
                w_pc_nxt = w_pc+1;
            end
            else
            begin
                case(w_pc_gen_ctl)
                    `PC_GOTO,
                    `PC_CALL:   w_pc_nxt= w_ins[7:0];//{w_status[7:6],1'b0,w_ins[7:0]};
                    `PC_RET :   w_pc_nxt= w_stk_pc;
                    default
                    w_pc_nxt= w_pc+1;
                endcase
            end
 
 
        always @(*) begin
        casex (w_ins)
 
            12'b0000_001X_XXXX:            //Checked 2008_11_22
                //REPLACE ID = MOVWF
                //REPLACE ID = MOVWF
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_IGN;           //check 2008_11_22
                w_alu_op = `ALU_PA;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of MOVWF ;
 
            12'b0000_0100_0000:
                //REPLACE ID = CLRW
                //REPLACE ID = CLRW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_IGN;          //check 2008_11_22
                w_alu_op = `ALU_ZERO;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of CLRW ;
 
            12'b0000_011X_XXXX:
                //REPLACE ID = CLRF
                //REPLACE ID = CLRF
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_IGN;     //check 2008_11_22
                w_alu_op = `ALU_ZERO;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of CLRF ;
 
            12'b0000_100X_XXXX:
                //REPLACE ID = SUBWF_W
                //REPLACE ID = SUBWF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;     //check 2008_11_22
                w_alu_op = `ALU_SUB;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of SUBWF_W ;
 
            12'b0000_101X_XXXX:
                //REPLACE ID = SUBWF_F
                //REPLACE ID = SUBWF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;           //check 2008_11_22
                w_alu_op = `ALU_SUB;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of SUBWF_F ;
 
            12'b0000_110X_XXXX:
                //REPLACE ID = DECF_W
                //REPLACE ID = DECF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;           //check 2008_11_22
                w_alu_op = `ALU_DEC;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of DECF_W ;
 
 
            12'b0000_111X_XXXX:
                //REPLACE ID = DECF_F
                //REPLACE ID = DECF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;           //check 2008_11_22
                w_alu_op = `ALU_DEC;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of DECF_F ;
 
            12'b0001_000X_XXXX:
                //REPLACE ID = IORWF_W
                //REPLACE ID = IORWF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG; // `MUXB_EK;                     //fixed 2008_11_22
                w_alu_op = `ALU_OR;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of IORWF_W ;
 
 
 
            12'b0001_001X_XXXX:
                //REPLACE ID = IORWF_F
                //REPLACE ID = IORWF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG; // `MUXB_EK;                     //fixed 2008_11_22
                w_alu_op = `ALU_OR;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of IORWF_F ;
 
            12'b0001_010X_XXXX:
                //REPLACE ID = ANDWF_W
                //REPLACE ID = ANDWF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl =`MUXB_REG;// `MUXB_EK;                       //fixed 2008_11_22
                w_alu_op = `ALU_AND;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of ANDWF_W ;
 
            12'b0001_011X_XXXX:
                //REPLACE ID = ANDWF_F
                //REPLACE ID = ANDWF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl =`MUXB_REG;// `MUXB_EK;                       //fixed 2008_11_22
                w_alu_op = `ALU_AND;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of ANDWF_F ;
 
            12'b0001_100X_XXXX:
                //REPLACE ID = XORWF_W
                //REPLACE ID = XORWF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;     //check 2008_11_22
                w_alu_op = `ALU_XOR;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of XORWF_W ;
 
            12'b0001_101X_XXXX:
                //REPLACE ID = XORWF_F
                //REPLACE ID = XORWF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;    //check 2008_11_22
                w_alu_op = `ALU_XOR;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of XORWF_F ;
 
            12'b0001_110X_XXXX:
                //REPLACE ID = ADDWF_W
                //REPLACE ID = ADDWF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;          //check 2008_11_22
                w_alu_op = `ALU_ADD;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of ADDWF_W ;
 
            12'b0001_111X_XXXX:
                //REPLACE ID = ADDWF_F
                //REPLACE ID = ADDWF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_ADD;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of ADDWF_F ;
 
            12'b0010_000X_XXXX:
                //REPLACE ID = MOVF_W
                //REPLACE ID = MOVF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;    //check 2008_11_22
                w_alu_op = `ALU_PB;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of MOVF_W ;
 
 
            12'b0010_001X_XXXX:
                //REPLACE ID = MOVF_F
                //REPLACE ID = MOVF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;           //check 2008_11_22
                w_alu_op = `ALU_PB;
                w_mem_wr = `DIS;//Also can be set as EN
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of MOVF_F ;
 
            12'b0010_010X_XXXX:
                //REPLACE ID = COMF_W
                //REPLACE ID = COMF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;         //check 2008_11_22
                w_alu_op = `ALU_COM;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of COMF_W ;
 
            12'b0010_011X_XXXX:
                //REPLACE ID = COMF_F
                //REPLACE ID = COMF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;            //check 2008_11_22
                w_alu_op = `ALU_COM;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of COMF_F ;
 
            12'b0010_100X_XXXX:
                //REPLACE ID = INCF_W
                //REPLACE ID = INCF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;         //check 2008_11_22
                w_alu_op = `ALU_INC;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of INCF_W ;
 
            12'b0010_101X_XXXX:
                //REPLACE ID = INCF_F
                //REPLACE ID = INCF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;          //check 2008_11_22
                w_alu_op = `ALU_INC;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of INCF_F ;
 
            12'b0010_110X_XXXX:
                //REPLACE ID = DECFSZ_W
                //REPLACE ID = DECFSZ_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;                   //check 2008_11_22
                w_alu_op = `ALU_DEC;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_ZERO;            //if the result is 0 then the next w_insrction will be discarded
            end //end of DECFSZ_W ;
 
            12'b0010_111X_XXXX:
                //REPLACE ID = DECFSZ_F
                //REPLACE ID = DECFSZ_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;            //check 2008_11_22
                w_alu_op = `ALU_DEC;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_ZERO;             //if the result is 0 then the next w_insrction will be discarded
            end //end of DECFSZ_F ;
            //checked
 
            12'b0011_000X_XXXX:
                //REPLACE ID = RRF_W
                //REPLACE ID = RRF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;                 //check 2008_11_22
                w_alu_op = `ALU_ROR;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of RRF_W ;
            //checked
 
            12'b0011_001X_XXXX:
                //REPLACE ID = RRF_F
                //REPLACE ID = RRF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;   //check 2008_11_22
                w_alu_op = `ALU_ROR;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of RRF_F ;
 
            //
            12'b0011_010X_XXXX:
                //REPLACE ID = RLF_W
                //REPLACE ID = RLF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;  //check 2008_11_22
                w_alu_op = `ALU_ROL;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of RLF_W ;
 
            12'b0011_011X_XXXX:
                //REPLACE ID = RLF_F
                //REPLACE ID = RLF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;    //check 2008_11_22
                w_alu_op = `ALU_ROL;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of RLF_F ;
 
            12'b0011_100X_XXXX:
                //REPLACE ID = SWAPF_W
                //REPLACE ID = SWAPF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;         //check 2008_11_22
                w_alu_op = `ALU_SWAP;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of SWAPF_F ;
 
            12'b0011_101X_XXXX:
                //REPLACE ID = SWAPF_F
                //REPLACE ID = SWAPF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;         //check 2008_11_22
                w_alu_op = `ALU_SWAP;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of SWAPF_F ;
 
            12'b0011_110X_XXXX:
                //REPLACE ID = INCFSZ_W
                //REPLACE ID = INCFSZ_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;    //check 2008_11_22
                w_alu_op = `ALU_INC;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_ZERO;
            end //end of INCFSZ_W ;
 
            12'b0011_111X_XXXX:
                //REPLACE ID = INCFSZ_F
                //REPLACE ID = INCFSZ_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;   //check 2008_11_22
                w_alu_op = `ALU_INC;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_ZERO;
            end //end of INCFSZ_F ;
 
            12'b0100_XXXX_XXXX:
                //REPLACE ID = BCF
                //REPLACE ID = BCF
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_BD;
                w_muxb_ctl = `MUXB_REG;          //check 2008_11_22
                w_alu_op = `ALU_BCF;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of BCF ;
 
            12'b0101_XXXX_XXXX:
                //REPLACE ID = BSF
                //REPLACE ID = BSF
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_BD;
                w_muxb_ctl = `MUXB_REG;         //check 2008_11_22
                w_alu_op = `ALU_BSF;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of BSF ;
            /**/
 
            12'b0110_XXXX_XXXX:
                //REPLACE ID = BTFSC
                //REPLACE ID = BTFSC
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_BD;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_BTFSC;      //check 2008_11_22
                w_mem_wr = `DIS;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_ZERO;
            end //end of BTFSC ;
 
            12'b0111_XXXX_XXXX:
                //REPLACE ID = BTFSS
                //REPLACE ID = BTFSS
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_BD;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_BTFSS;
                w_mem_wr = `DIS;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NZERO;
            end //end of BTFSS ;
 
            12'b1000_XXXX_XXXX:
                //REPLACE ID = RETLW
                //REPLACE ID = RETLW
            begin
                w_pc_gen_ctl = `PC_RET ;
                w_stk_op = `STK_POP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_EK;                     //check 2008_11_22
                w_alu_op = `ALU_PB;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of RETLW ;
 
            12'b1001_XXXX_XXXX:
                //REPLACE ID = CALL
                //REPLACE ID = CALL
            begin
                w_pc_gen_ctl = `PC_GOTO;
                w_stk_op = `STK_PSH;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_IGN;          //check 2008_11_22
                w_alu_op = `ALU_NOP;
                w_mem_wr = `DIS;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of CALL ;
 
            12'b101X_XXXX_XXXX:
                //REPLACE ID = GOTO
                //REPLACE ID = GOTO
            begin
                w_pc_gen_ctl = `PC_GOTO;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_IGN;    //check 2008_11_22
                w_alu_op = `ALU_NOP;
                w_mem_wr = `DIS;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of GOTO ;
 
            12'b1100_XXXX_XXXX:
                //REPLACE ID = MOVLW
                //REPLACE ID = MOVLW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_EK;    //check 2008_11_22
                w_alu_op = `ALU_PB;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of MOVLW ;
 
            12'b1101_XXXX_XXXX:
                //REPLACE ID = IORLW
                //REPLACE ID = IORLW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_EK;  //check 2008_11_22
                w_alu_op = `ALU_OR;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of IORLW ;
 
            12'b1110_XXXX_XXXX:
                //REPLACE ID = ANDLW
                //REPLACE ID = ANDLW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_EK;  //check 2008_11_22
                w_alu_op = `ALU_AND;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of ANDLW ;
 
            12'b1111_XXXX_XXXX:
                //REPLACE ID = XORLW
                //REPLACE ID = XORLW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_EK;    //check 2008_11_22
                w_alu_op = `ALU_XOR;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of XORLW ;
 
 
            default:
                //REPLACE ID = NOP
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_IGN;   //check 2008_11_22
                w_alu_op = `ALU_NOP;
                w_mem_wr = `DIS;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of NOP ;
        endcase
    end
endmodule

Line No.	Rev	Author	Line
1	11	mcupro
2	7	mcupro	`include "clairisc_def.h"
3			`module ClaiRISC_core (`
4			`input clk,`
5	16	mcupro	`input rst,`
6			`output [7:0]dvc_wr_addr,`
7			`output [7:0]dvc_rd_addr,`
8			`output [7:0]data_mem2dvc,`
9			`input [7:0]data_dvc2mem,`
10			`output dvc_wr ,`
11			`output dvc_rd`
12	7	mcupro	`);`
13
14			`supply0 GND;`
15			`wire w_c_2alu;`
16			`wire w_c_2mem;`
17			`reg w_c_wr;`
18			`reg w_c_wr_r;`
19			`reg w_mem_wr;`
20			`reg w_mem_wr_r;`
21			`reg w_muxa_ctl;`
22			`reg w_muxa_ctl_r;`
23			`reg w_muxb_ctl;`
24			`reg w_reg_muxb_r;`
25			`reg w_skip;`
26			`reg w_w_wr;`
27	16	mcupro	`reg w_w_wr_r;`
28			`wire w_z;`
29	7	mcupro	`reg w_z_wr;`
30			`reg w_z_wr_r;`
31			`reg [7:0] w_alu_in_a;`
32			`reg [7:0] w_alu_in_b;`
33			`reg [4:0] w_alu_op;`
34			`reg [4:0] w_alu_op_r;`
35	16	mcupro	`reg [7:0] w_alu_res;`
36	7	mcupro	`wire [1:0] w_bank;`
37			`reg [7:0] w_bd_r;`
38			`reg [1:0] w_brc_ctl;`
39			`reg [1:0] w_br_ctl_r;`
40			`reg [8:0] w_ek_r;`
41			`wire [7:0] w_file_o;`
42			`wire [11:0] w_ins;`
43			`reg [10:0] w_pc;`
44			`reg [2:0] w_pc_gen_ctl;`
45			`reg [10:0] w_pc_nxt;`
46	16	mcupro	`wire [4:0] w_rd_addr;`
47	7	mcupro	`wire [7:0] w_status;`
48			`reg [1:0] w_stk_op;`
49			`wire [10:0] w_stk_pc;`
50			`reg[4:0] w_wbadd_r;`
51			`wire [4:0] w_wd_addr;`
52			`reg [7:0] w_wreg;`
53	16	mcupro	`wire [4:0] w_wr_addr;`
54	7	mcupro
55			`always @(posedge clk)`
56			`w_pc<=w_pc_nxt;`
57
58	16	mcupro	`reg [10:0] stack1, stack2,stack3, stack4;`
59
60			`initial begin`
61			`stack1=0;`
62			`stack2=0;`
63			`stack3=0;`
64			`stack4=0;`
65			`end`
66
67	7	mcupro	`assign w_stk_pc = stack1;`
68
69			`always @(posedge clk)`
70			`begin`
71			`case (w_stk_op)`
72			`STK_PSH :// PUSH stack
73	16	mcupro	`begin`
74	7	mcupro	`stack4 <= stack3;`
75	16	mcupro	`stack3 <= stack2;`
76	7	mcupro	`stack2 <= stack1;`
77	16	mcupro	`stack1 <= w_pc+1;`
78	7	mcupro	`end`
79			`STK_POP :// POP stack
80			`begin`
81	16	mcupro	`stack1 <= stack2;`
82			`stack2 <= stack3;`
83			`stack3 <= stack4;`
84			`end`
85	7	mcupro	`// default ://do nothing`
86			`endcase`
87			`end`
88
89	16	mcupro	`assign w_rd_addr =w_wd_addr[4:0];`
90	7	mcupro
91	16	mcupro	`mem_man mem_man`
92			`(`
93	7	mcupro	`.c_wr(w_c_wr_r),`
94			`.ci(w_c_2mem),`
95			`.clk(clk),`
96			`.co(w_c_2alu),`
97			`.din(w_alu_res),`
98			`.dout(w_file_o),`
99	16	mcupro	`.rd_addr(w_rd_addr[4:0]),`
100	7	mcupro	`.rst(rst),`
101			`.status(w_status),`
102	16	mcupro	`.wr_addr(w_wr_addr[4:0]),`
103	7	mcupro	`.wr_en(w_mem_wr_r),`
104			`.z_wr(w_z_wr_r),`
105	16	mcupro	`.zi(w_z),`
106			`.dvc_wr_addr(dvc_wr_addr),`
107			`.dvc_rd_addr(dvc_rd_addr),`
108			`.data_mem2dvc(data_mem2dvc),`
109			`.data_dvc2mem(data_dvc2mem),`
110			`.dvc_wr(dvc_wr),`
111			`.dvc_rd(dvc_rd)`
112	7	mcupro	`);`
113
114	16	mcupro	`always @(posedge clk)`
115			`if (w_skip)`
116	7	mcupro	`w_alu_op_r<=0;`
117			`else`
118			`w_alu_op_r<=w_alu_op;`
119
120			`always@(posedge clk)`
121	16	mcupro	`if (w_skip) w_br_ctl_r<=0;`
122	7	mcupro	`else w_br_ctl_r<=w_brc_ctl;`
123
124			`always@(posedge clk)`
125	16	mcupro	`if (w_skip) w_z_wr_r<=0;`
126	7	mcupro	`else w_z_wr_r<=w_z_wr;`
127
128			`always @ (posedge clk)`
129	16	mcupro	`if (w_skip)`
130	7	mcupro	`w_c_wr_r<=0;`
131			`else`
132			`w_c_wr_r<=w_c_wr;`
133
134			`always @(posedge clk)`
135	16	mcupro	`if(w_skip)`
136	7	mcupro	`w_mem_wr_r<=0;`
137	16	mcupro	`else`
138	7	mcupro	`w_mem_wr_r<=w_mem_wr;`
139
140			`always @(posedge clk)`
141	16	mcupro	`if (w_w_wr_r)`
142	7	mcupro	`w_wreg<=w_alu_res;`
143
144			`always @ (posedge clk)`
145			`w_bd_r<=1<<w_ins[7:5];`
146
147	16	mcupro	`always @(posedge clk)`
148			`w_w_wr_r <=w_w_wr ;`
149	7	mcupro
150			`always @(posedge clk)`
151			`w_ek_r<=w_ins[8:0];`
152
153			`assign w_wd_addr = w_ins[4:0];`
154
155			`always@(posedge clk)`
156			`w_wbadd_r<=w_wd_addr;`
157	16	mcupro
158	7	mcupro
159	16	mcupro	`assign w_wr_addr = w_wbadd_r[4:0];`
160	7	mcupro	`reg addercout;`
161			`always @(*) begin`
162			`case (w_alu_op_r) // synsys parallel_case`
163			`ALU_ADD: {addercout, w_alu_res} = w_alu_in_a + w_alu_in_b;
164			`ALU_SUB: {addercout, w_alu_res} = w_alu_in_b - w_alu_in_a;
165			`ALU_ROR: {addercout, w_alu_res} = {w_alu_in_b[0], w_c_2alu, w_alu_in_b[7:1]};
166			`ALU_ROL: {addercout, w_alu_res} = {w_alu_in_b[7],w_alu_in_b[6:0], w_c_2alu};
167			`ALU_OR: {addercout, w_alu_res} = {1'bx, w_alu_in_a \| w_alu_in_b};
168			`ALU_XOR: {addercout, w_alu_res} = {1'bx, w_alu_in_a ^ w_alu_in_b};
169			`ALU_COM: {addercout, w_alu_res} = {1'bx, ~w_alu_in_b};
170			`ALU_SWAP: {addercout, w_alu_res} = {1'bx, w_alu_in_b[3:0], w_alu_in_b[7:4]};
171			`ALU_AND,//: {addercout, y} = {1'bx, a & b};
172			`ALU_BTFSC,//: {addercout, y} = {1'bx, a & b };
173			`ALU_BTFSS: {addercout, w_alu_res} = {1'bx, w_alu_in_a & w_alu_in_b };
174			`ALU_DEC: {addercout, w_alu_res} = {1'bx, w_alu_in_b - 1};
175			`ALU_INC: {addercout, w_alu_res} = {1'bx, 1 + w_alu_in_b};
176			`ALU_PA : {addercout, w_alu_res} = {1'bx, w_alu_in_a};
177			`ALU_PB : {addercout, w_alu_res} = {1'bx, w_alu_in_b};
178			`ALU_BSF : {addercout, w_alu_res} = {1'Bx,w_alu_in_a \| w_alu_in_b};
179			`ALU_BCF : {addercout, w_alu_res} = {1'bx,~w_alu_in_a & w_alu_in_b};
180			`default: {addercout, w_alu_res} = {1'bx, 8'h00};`
181			`endcase`
182			`end`
183			`assign w_z = (w_alu_res== 8'h00);`
184			assign w_c_2mem = (w_alu_op_r == `ALU_SUB) ? ~addercout : addercout;
185
186			`always @(posedge clk)`
187			`if( w_skip) w_muxa_ctl_r<=0;`
188			`else`
189			`w_muxa_ctl_r<= w_muxa_ctl;`
190
191			`always @ (posedge clk)`
192			`if (w_skip) w_reg_muxb_r<=0;`
193			`else`
194			`w_reg_muxb_r<= w_muxb_ctl;`
195
196
197			`always@(*)`
198			if (w_muxa_ctl_r==`MUXA_W)
199			`w_alu_in_a=w_wreg;`
200			`else`
201			`w_alu_in_a=w_bd_r;`
202
203
204			`always @(*)`
205			if (w_reg_muxb_r==`MUXB_EK)
206			`w_alu_in_b=w_ek_r[7:0];`
207			`else w_alu_in_b=w_file_o;`
208
209			`always @(*)`
210			`case (w_br_ctl_r)`
211			`//Z==1 means the ALU result is 0`
212			`//Z==0 means the ALU result is not 0`
213			`BG_ZERO :w_skip = (w_z==1); //if the ALU result is 0 then the next instrction will be discarded
214			`BG_NZERO :w_skip = (w_z==0); //if the ALU result is not zero
215			`//then skip the next instruction`
216			`default w_skip = 0;`
217			`endcase`
218	16	mcupro
219			`com_prom program_rom`
220	7	mcupro	`(`
221			`.clk(clk),`
222			`.dout(w_ins),`
223			`.rd_addr(w_pc_nxt)`
224	16	mcupro	`);`
225	7	mcupro
226			`always @ (*)`
227			`if (rst)`
228			`w_pc_nxt=0;//'h1ff; //THE RST ENTRY`
229			`else`
230			`if(w_skip)`
231			`begin`
232			`w_pc_nxt = w_pc+1;`
233			`end`
234			`else`
235			`begin`
236			`case(w_pc_gen_ctl)`
237			`PC_GOTO,
238	16	mcupro	`PC_CALL: w_pc_nxt= w_ins[7:0];//{w_status[7:6],1'b0,w_ins[7:0]};
239			`PC_RET : w_pc_nxt= w_stk_pc;
240	7	mcupro	`default`
241			`w_pc_nxt= w_pc+1;`
242			`endcase`
243			`end`
244
245	14	mcupro
246	16	mcupro	`always @(*) begin`
247	7	mcupro	`casex (w_ins)`
248
249	14	mcupro	`12'b0000_001X_XXXX: //Checked 2008_11_22`
250	7	mcupro	`//REPLACE ID = MOVWF`
251			`//REPLACE ID = MOVWF`
252			`begin`
253			w_pc_gen_ctl = `PC_NEXT;
254			w_stk_op = `STK_NOP;
255			w_muxa_ctl = `MUXA_W;
256	14	mcupro	w_muxb_ctl = `MUXB_IGN; //check 2008_11_22
257	7	mcupro	w_alu_op = `ALU_PA;
258			w_mem_wr = `EN;
259			w_w_wr = `DIS;
260			w_z_wr = `DIS;
261			w_c_wr = `DIS;
262			w_brc_ctl = `BG_NOP;
263			`end //end of MOVWF ;`
264
265			`12'b0000_0100_0000:`
266			`//REPLACE ID = CLRW`
267			`//REPLACE ID = CLRW`
268			`begin`
269			w_pc_gen_ctl = `PC_NEXT;
270			w_stk_op = `STK_NOP;
271			w_muxa_ctl = `MUXA_IGN;
272	14	mcupro	w_muxb_ctl = `MUXB_IGN; //check 2008_11_22
273	7	mcupro	w_alu_op = `ALU_ZERO;
274			w_mem_wr = `DIS;
275			w_w_wr = `EN;
276			w_z_wr = `EN;
277			w_c_wr = `DIS;
278			w_brc_ctl = `BG_NOP;
279			`end //end of CLRW ;`
280
281			`12'b0000_011X_XXXX:`
282			`//REPLACE ID = CLRF`
283			`//REPLACE ID = CLRF`
284			`begin`
285			w_pc_gen_ctl = `PC_NEXT;
286			w_stk_op = `STK_NOP;
287			w_muxa_ctl = `MUXA_IGN;
288	14	mcupro	w_muxb_ctl = `MUXB_IGN; //check 2008_11_22
289	7	mcupro	w_alu_op = `ALU_ZERO;
290			w_mem_wr = `EN;
291			w_w_wr = `DIS;
292			w_z_wr = `EN;
293			w_c_wr = `DIS;
294			w_brc_ctl = `BG_NOP;
295			`end //end of CLRF ;`
296
297			`12'b0000_100X_XXXX:`
298			`//REPLACE ID = SUBWF_W`
299			`//REPLACE ID = SUBWF_W`
300			`begin`
301			w_pc_gen_ctl = `PC_NEXT;
302			w_stk_op = `STK_NOP;
303			w_muxa_ctl = `MUXA_W;
304	14	mcupro	w_muxb_ctl = `MUXB_REG; //check 2008_11_22
305	7	mcupro	w_alu_op = `ALU_SUB;
306			w_mem_wr = `DIS;
307			w_w_wr = `EN;
308			w_z_wr = `EN;
309			w_c_wr = `EN;
310			w_brc_ctl = `BG_NOP;
311			`end //end of SUBWF_W ;`
312
313			`12'b0000_101X_XXXX:`
314			`//REPLACE ID = SUBWF_F`
315			`//REPLACE ID = SUBWF_F`
316			`begin`
317			w_pc_gen_ctl = `PC_NEXT;
318			w_stk_op = `STK_NOP;
319			w_muxa_ctl = `MUXA_W;
320	14	mcupro	w_muxb_ctl = `MUXB_REG; //check 2008_11_22
321	7	mcupro	w_alu_op = `ALU_SUB;
322			w_mem_wr = `EN;
323			w_w_wr = `DIS;
324			w_z_wr = `EN;
325			w_c_wr = `EN;
326			w_brc_ctl = `BG_NOP;
327			`end //end of SUBWF_F ;`
328
329			`12'b0000_110X_XXXX:`
330			`//REPLACE ID = DECF_W`
331			`//REPLACE ID = DECF_W`
332			`begin`
333			w_pc_gen_ctl = `PC_NEXT;
334			w_stk_op = `STK_NOP;
335			w_muxa_ctl = `MUXA_IGN;
336	14	mcupro	w_muxb_ctl = `MUXB_REG; //check 2008_11_22
337	7	mcupro	w_alu_op = `ALU_DEC;
338			w_mem_wr = `DIS;
339			w_w_wr = `EN;
340			w_z_wr = `EN;
341			w_c_wr = `DIS;
342			w_brc_ctl = `BG_NOP;
343			`end //end of DECF_W ;`
344
345
346			`12'b0000_111X_XXXX:`
347			`//REPLACE ID = DECF_F`
348			`//REPLACE ID = DECF_F`
349			`begin`
350			w_pc_gen_ctl = `PC_NEXT;
351			w_stk_op = `STK_NOP;
352			w_muxa_ctl = `MUXA_IGN;
353	14	mcupro	w_muxb_ctl = `MUXB_REG; //check 2008_11_22
354	7	mcupro	w_alu_op = `ALU_DEC;
355			w_mem_wr = `EN;
356			w_w_wr = `DIS;
357			w_z_wr = `EN;
358			w_c_wr = `DIS;
359			w_brc_ctl = `BG_NOP;
360			`end //end of DECF_F ;`
361
362			`12'b0001_000X_XXXX:`
363			`//REPLACE ID = IORWF_W`
364			`//REPLACE ID = IORWF_W`
365			`begin`
366			w_pc_gen_ctl = `PC_NEXT;
367			w_stk_op = `STK_NOP;
368			w_muxa_ctl = `MUXA_W;
369	14	mcupro	w_muxb_ctl = `MUXB_REG; // `MUXB_EK; //fixed 2008_11_22
370	7	mcupro	w_alu_op = `ALU_OR;
371			w_mem_wr = `DIS;
372			w_w_wr = `EN;
373			w_z_wr = `EN;
374			w_c_wr = `DIS;
375			w_brc_ctl = `BG_NOP;
376			`end //end of IORWF_W ;`
377
378
379
380			`12'b0001_001X_XXXX:`
381			`//REPLACE ID = IORWF_F`
382			`//REPLACE ID = IORWF_F`
383			`begin`
384			w_pc_gen_ctl = `PC_NEXT;
385			w_stk_op = `STK_NOP;
386			w_muxa_ctl = `MUXA_W;
387	14	mcupro	w_muxb_ctl = `MUXB_REG; // `MUXB_EK; //fixed 2008_11_22
388	7	mcupro	w_alu_op = `ALU_OR;
389			w_mem_wr = `EN;
390			w_w_wr = `DIS;
391			w_z_wr = `EN;
392			w_c_wr = `DIS;
393			w_brc_ctl = `BG_NOP;
394			`end //end of IORWF_F ;`
395
396			`12'b0001_010X_XXXX:`
397			`//REPLACE ID = ANDWF_W`
398			`//REPLACE ID = ANDWF_W`
399			`begin`
400			w_pc_gen_ctl = `PC_NEXT;
401			w_stk_op = `STK_NOP;
402			w_muxa_ctl = `MUXA_W;
403	14	mcupro	w_muxb_ctl =`MUXB_REG;// `MUXB_EK; //fixed 2008_11_22
404	7	mcupro	w_alu_op = `ALU_AND;
405			w_mem_wr = `DIS;
406			w_w_wr = `EN;
407			w_z_wr = `EN;
408			w_c_wr = `DIS;
409			w_brc_ctl = `BG_NOP;
410			`end //end of ANDWF_W ;`
411
412			`12'b0001_011X_XXXX:`
413			`//REPLACE ID = ANDWF_F`
414			`//REPLACE ID = ANDWF_F`
415			`begin`
416			w_pc_gen_ctl = `PC_NEXT;
417			w_stk_op = `STK_NOP;
418			w_muxa_ctl = `MUXA_W;
419	14	mcupro	w_muxb_ctl =`MUXB_REG;// `MUXB_EK; //fixed 2008_11_22
420	7	mcupro	w_alu_op = `ALU_AND;
421			w_mem_wr = `EN;
422			w_w_wr = `DIS;
423			w_z_wr = `EN;
424			w_c_wr = `DIS;
425			w_brc_ctl = `BG_NOP;
426			`end //end of ANDWF_F ;`
427
428			`12'b0001_100X_XXXX:`
429			`//REPLACE ID = XORWF_W`
430			`//REPLACE ID = XORWF_W`
431			`begin`
432			w_pc_gen_ctl = `PC_NEXT;
433			w_stk_op = `STK_NOP;
434			w_muxa_ctl = `MUXA_W;
435	14	mcupro	w_muxb_ctl = `MUXB_REG; //check 2008_11_22
436	7	mcupro	w_alu_op = `ALU_XOR;
437			w_mem_wr = `DIS;
438			w_w_wr = `EN;
439			w_z_wr = `EN;
440			w_c_wr = `DIS;
441			w_brc_ctl = `BG_NOP;
442			`end //end of XORWF_W ;`
443
444			`12'b0001_101X_XXXX:`
445			`//REPLACE ID = XORWF_F`
446			`//REPLACE ID = XORWF_F`
447			`begin`
448			w_pc_gen_ctl = `PC_NEXT;
449			w_stk_op = `STK_NOP;
450			w_muxa_ctl = `MUXA_W;
451	14	mcupro	w_muxb_ctl = `MUXB_REG; //check 2008_11_22
452	7	mcupro	w_alu_op = `ALU_XOR;
453			w_mem_wr = `EN;
454			w_w_wr = `DIS;
455			w_z_wr = `EN;
456			w_c_wr = `DIS;
457			w_brc_ctl = `BG_NOP;
458			`end //end of XORWF_F ;`
459
460			`12'b0001_110X_XXXX:`
461			`//REPLACE ID = ADDWF_W`
462			`//REPLACE ID = ADDWF_W`
463			`begin`
464			w_pc_gen_ctl = `PC_NEXT;
465			w_stk_op = `STK_NOP;
466			w_muxa_ctl = `MUXA_W;
467	14	mcupro	w_muxb_ctl = `MUXB_REG; //check 2008_11_22
468	7	mcupro	w_alu_op = `ALU_ADD;
469			w_mem_wr = `DIS;
470			w_w_wr = `EN;
471			w_z_wr = `EN;
472			w_c_wr = `EN;
473			w_brc_ctl = `BG_NOP;
474			`end //end of ADDWF_W ;`
475
476			`12'b0001_111X_XXXX:`
477			`//REPLACE ID = ADDWF_F`
478			`//REPLACE ID = ADDWF_F`
479			`begin`
480			w_pc_gen_ctl = `PC_NEXT;
481			w_stk_op = `STK_NOP;
482			w_muxa_ctl = `MUXA_W;
483			w_muxb_ctl = `MUXB_REG;
484			w_alu_op = `ALU_ADD;
485			w_mem_wr = `EN;
486			w_w_wr = `DIS;
487			w_z_wr = `EN;
488			w_c_wr = `EN;
489			w_brc_ctl = `BG_NOP;
490			`end //end of ADDWF_F ;`
491
492			`12'b0010_000X_XXXX:`
493			`//REPLACE ID = MOVF_W`
494			`//REPLACE ID = MOVF_W`
495			`begin`
496			w_pc_gen_ctl = `PC_NEXT;
497			w_stk_op = `STK_NOP;
498			w_muxa_ctl = `MUXA_IGN;
499	14	mcupro	w_muxb_ctl = `MUXB_REG; //check 2008_11_22
500	7	mcupro	w_alu_op = `ALU_PB;

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