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1 11 mcupro 
/******************************************************************
2 
 *                                                                *
3 
 *    Author: Liwei                                               *
4 
 *                                                                *
5 
 *    This file is part of the "ClaiRISC" project,                *
6 
 *    The folder in CVS is named as "lwrisc"                      *
7 
 *    Downloaded from:                                            *
8 
 *    http://www.opencores.org/pdownloads.cgi/list/lwrisc         *
9 
 *                                                                *
10 
 *    If you encountered any problem, please contact me via       *
11 
 *    Email:mcupro@opencores.org  or mcupro@163.com               *
12 
 *                                                                *
13 
 ******************************************************************/
14 
 
15 7 mcupro 
`include "clairisc_def.h"
16 
module ClaiRISC_core (
17 
        input clk,
18 
        input rst               ,
19 
        input [7:0] in0,
20 
        input [7:0] in1,
21 
        output [7:0] out0,
22 
        output [7:0] out1
23 
    );
24 
 
25 
    supply0 GND;
26 
    wire w_c_2alu;
27 
    wire w_c_2mem;
28 
    reg w_c_wr;
29 
    reg w_c_wr_r;
30 
    reg w_mem_wr;
31 
    reg w_mem_wr_r;
32 
    reg w_muxa_ctl;
33 
    reg w_muxa_ctl_r;
34 
    reg w_muxb_ctl;
35 
    reg w_reg_muxb_r;
36 
    reg w_skip;
37 
    reg w_w_wr;
38 
    reg w_w_wr_r;
39 
    wire w_z;
40 
    reg w_z_wr;
41 
    reg w_z_wr_r;
42 
    reg [7:0] w_alu_in_a;
43 
    reg [7:0] w_alu_in_b;
44 
    reg [4:0] w_alu_op;
45 
    reg [4:0] w_alu_op_r;
46 
    reg [7:0] w_alu_res;
47 
    wire [1:0] w_bank;
48 
    reg [7:0] w_bd_r;
49 
    reg [1:0] w_brc_ctl;
50 
    reg [1:0] w_br_ctl_r;
51 
    reg [8:0] w_ek_r;
52 
    wire [7:0] w_file_o;
53 
    wire [11:0] w_ins;
54 
    reg [10:0] w_pc;
55 
    reg [2:0] w_pc_gen_ctl;
56 
    reg [10:0] w_pc_nxt;
57 
    wire [6:0] w_rd_addr;
58 
    wire [7:0] w_status;
59 
    reg [1:0] w_stk_op;
60 
    wire [10:0] w_stk_pc;
61 
    reg[4:0] w_wbadd_r;
62 
    wire [4:0] w_wd_addr;
63 
    reg [7:0] w_wreg;
64 
    wire [6:0] w_wr_addr;
65 
 
66 
    always @(posedge clk)
67 
        w_pc<=w_pc_nxt;
68 
 
69 
    reg [10:0]   stack1, stack2, stack3, stack4;
70 
    assign w_stk_pc = stack1;
71 
 
72 
    always @(posedge clk)
73 
    begin
74 
        case (w_stk_op)
75 
            `STK_PSH    :// PUSH stack
76 
            begin
77 
                stack4 <= stack3;
78 
                stack3 <= stack2;
79 
                stack2 <= stack1;
80 
                stack1 <= w_pc;
81 
            end
82 
            `STK_POP    :// POP stack
83 
            begin
84 
                stack1 <= stack2;
85 
                stack2 <= stack3;
86 
                stack3 <= stack4;
87 
            end
88 
            //  default ://do nothing
89 
        endcase
90 
    end
91 
 
92 
    assign         w_rd_addr ={ w_bank[1:0],w_wd_addr[4:0]};
93 
 
94 
    wb_mem_man   mem_man
95 
                 (
96 
                     .bank(w_bank),
97 
                     .c_wr(w_c_wr_r),
98 
                     .ci(w_c_2mem),
99 
                     .clk(clk),
100 
                     .co(w_c_2alu),
101 
                     .din(w_alu_res),
102 
                     .dout(w_file_o),
103 
                     .rd_addr(w_rd_addr),
104 
                     .rst(rst),
105 
                     .status(w_status),
106 
                     .wr_addr(w_wr_addr),
107 
                     .wr_en(w_mem_wr_r),
108 
                     .z_wr(w_z_wr_r),
109 
                     .zi(w_z),
110 
                     .in0(in0),
111 
                     .in1(in1),
112 
                     .out0(out0),
113 
                     .out1(out1)
114 
                 );
115 
 
116 
    always @(posedge clk)
117 
        if (w_skip==1)
118 
            w_alu_op_r<=0;
119 
        else
120 
            w_alu_op_r<=w_alu_op;
121 
 
122 
    always@(posedge clk)
123 
        if (w_skip==1)    w_br_ctl_r<=0;
124 
        else w_br_ctl_r<=w_brc_ctl;
125 
 
126 
    always@(posedge clk)
127 
        if (w_skip==1)    w_z_wr_r<=0;
128 
        else  w_z_wr_r<=w_z_wr;
129 
 
130 
    always @ (posedge clk)
131 
        if (w_skip==1)
132 
            w_c_wr_r<=0;
133 
        else
134 
            w_c_wr_r<=w_c_wr;
135 
 
136 
    always @(posedge clk)
137 
        if(w_skip==1)
138 
            w_mem_wr_r<=0;
139 
        else
140 
            w_mem_wr_r<=w_mem_wr;
141 
 
142 
    always @(posedge clk)
143 
        if (w_w_wr_r==1)
144 
            w_wreg<=w_alu_res;
145 
 
146 
        always @ (posedge clk)
147 
                w_bd_r<=1<<w_ins[7:5];
148 
 
149 
    always @(posedge clk)
150 
        w_w_wr_r <=w_w_wr ;
151 
 
152 
    always @(posedge clk)
153 
        w_ek_r<=w_ins[8:0];
154 
 
155 
    assign w_wd_addr = w_ins[4:0];
156 
 
157 
    always@(posedge clk)
158 
        w_wbadd_r<=w_wd_addr;
159 
 
160 
    assign w_wr_addr = {w_bank[1:0],w_wbadd_r[4:0]};
161 
 
162 
 
163 
    reg         addercout;
164 
    always @(*) begin
165 
        case (w_alu_op_r) // synsys parallel_case
166 
            `ALU_ADD:   {addercout,  w_alu_res}  = w_alu_in_a + w_alu_in_b;
167 
            `ALU_SUB:  {addercout,  w_alu_res}  = w_alu_in_b - w_alu_in_a;
168 
            `ALU_ROR:  {addercout,  w_alu_res}  = {w_alu_in_b[0], w_c_2alu, w_alu_in_b[7:1]};
169 
            `ALU_ROL:  {addercout,  w_alu_res}  = {w_alu_in_b[7],w_alu_in_b[6:0], w_c_2alu};
170 
            `ALU_OR:   {addercout,  w_alu_res}  = {1'bx, w_alu_in_a | w_alu_in_b};
171 
            `ALU_XOR:  {addercout,  w_alu_res}  = {1'bx, w_alu_in_a ^ w_alu_in_b};
172 
            `ALU_COM:  {addercout,  w_alu_res}  = {1'bx, ~w_alu_in_b};
173 
            `ALU_SWAP: {addercout,  w_alu_res}  = {1'bx, w_alu_in_b[3:0], w_alu_in_b[7:4]};
174 
            `ALU_AND,//:  {addercout,  y}  = {1'bx, a & b};
175 
            `ALU_BTFSC,//:  {addercout,  y}  = {1'bx, a & b };
176 
            `ALU_BTFSS: {addercout,  w_alu_res}  = {1'bx, w_alu_in_a & w_alu_in_b };
177 
            `ALU_DEC:   {addercout,  w_alu_res}  = {1'bx, w_alu_in_b - 1};
178 
            `ALU_INC:   {addercout,  w_alu_res}  = {1'bx, 1 + w_alu_in_b};
179 
            `ALU_PA :   {addercout,  w_alu_res}  = {1'bx, w_alu_in_a};
180 
            `ALU_PB :   {addercout,  w_alu_res}  = {1'bx, w_alu_in_b};
181 
            `ALU_BSF :  {addercout,  w_alu_res}  = {1'Bx,w_alu_in_a | w_alu_in_b};
182 
            `ALU_BCF :  {addercout,  w_alu_res}  = {1'bx,~w_alu_in_a & w_alu_in_b};
183 
            default:     {addercout, w_alu_res}  = {1'bx, 8'h00};
184 
        endcase
185 
    end
186 
    assign  w_z = (w_alu_res== 8'h00);
187 
    assign  w_c_2mem =  (w_alu_op_r == `ALU_SUB) ?  ~addercout : addercout;
188 
 
189 
    always @(posedge clk)
190 
        if( w_skip)      w_muxa_ctl_r<=0;
191 
        else
192 
            w_muxa_ctl_r<=       w_muxa_ctl;
193 
 
194 
    always @ (posedge clk)
195 
        if (w_skip)              w_reg_muxb_r<=0;
196 
        else
197 
            w_reg_muxb_r<=      w_muxb_ctl;
198 
 
199 
 
200 
    always@(*)
201 
        if (w_muxa_ctl_r==`MUXA_W)
202 
            w_alu_in_a=w_wreg;
203 
        else
204 
            w_alu_in_a=w_bd_r;
205 
 
206 
 
207 
    always @(*)
208 
        if (w_reg_muxb_r==`MUXB_EK)
209 
            w_alu_in_b=w_ek_r[7:0];
210 
        else w_alu_in_b=w_file_o;
211 
 
212 
    always @(*)
213 
    case (w_br_ctl_r)
214 
        //Z==1 means the ALU result is 0
215 
        //Z==0 means the ALU result is not 0
216 
        `BG_ZERO :w_skip =  (w_z==1);   //if the ALU result is 0 then the next instrction will be discarded
217 
        `BG_NZERO :w_skip = (w_z==0);     //if the ALU result is not zero
218 
        //then skip the next instruction
219 
        default w_skip = 0;
220 
    endcase
221 
 
222 
 
223 
    pram program_rom
224 
         (
225 
             .clk(clk),
226 
             .dout(w_ins),
227 
             .rd_addr(w_pc_nxt)
228 
         );
229 
 
230 
    always @ (*)
231 
        if (rst)
232 
            w_pc_nxt=0;//'h1ff;            //THE RST ENTRY
233 
        else
234 
            if(w_skip)
235 
            begin
236 
                w_pc_nxt = w_pc+1;
237 
            end
238 
            else
239 
            begin
240 
                case(w_pc_gen_ctl)
241 
                    `PC_GOTO,
242 
                    `PC_CALL:    w_pc_nxt= {w_status[7:6],w_ins[8:0]};
243 
                    `PC_RET:    w_pc_nxt= w_stk_pc;
244 
                    default
245 
                    w_pc_nxt= w_pc+1;
246 
                endcase
247 
            end
248 
 
249 
    always @(*) begin
250 
        casex (w_ins)
251 
 
252 
            12'b0000_001X_XXXX:
253 
                //REPLACE ID = MOVWF
254 
                //REPLACE ID = MOVWF
255 
            begin
256 
                w_pc_gen_ctl = `PC_NEXT;
257 
                w_stk_op = `STK_NOP;
258 
                w_muxa_ctl = `MUXA_W;
259 
                w_muxb_ctl = `MUXB_IGN;
260 
                w_alu_op = `ALU_PA;
261 
                w_mem_wr = `EN;
262 
                w_w_wr = `DIS;
263 
                w_z_wr = `DIS;
264 
                w_c_wr = `DIS;
265 
                w_brc_ctl = `BG_NOP;
266 
            end //end of MOVWF ;
267 
 
268 
            12'b0000_0100_0000:
269 
                //REPLACE ID = CLRW
270 
                //REPLACE ID = CLRW
271 
            begin
272 
                w_pc_gen_ctl = `PC_NEXT;
273 
                w_stk_op = `STK_NOP;
274 
                w_muxa_ctl = `MUXA_IGN;
275 
                w_muxb_ctl = `MUXB_IGN;
276 
                w_alu_op = `ALU_ZERO;
277 
                w_mem_wr = `DIS;
278 
                w_w_wr = `EN;
279 
                w_z_wr = `EN;
280 
                w_c_wr = `DIS;
281 
                w_brc_ctl = `BG_NOP;
282 
            end //end of CLRW ;
283 
 
284 
            12'b0000_011X_XXXX:
285 
                //REPLACE ID = CLRF
286 
                //REPLACE ID = CLRF
287 
            begin
288 
                w_pc_gen_ctl = `PC_NEXT;
289 
                w_stk_op = `STK_NOP;
290 
                w_muxa_ctl = `MUXA_IGN;
291 
                w_muxb_ctl = `MUXB_IGN;
292 
                w_alu_op = `ALU_ZERO;
293 
                w_mem_wr = `EN;
294 
                w_w_wr = `DIS;
295 
                w_z_wr = `EN;
296 
                w_c_wr = `DIS;
297 
                w_brc_ctl = `BG_NOP;
298 
            end //end of CLRF ;
299 
 
300 
            12'b0000_100X_XXXX:
301 
                //REPLACE ID = SUBWF_W
302 
                //REPLACE ID = SUBWF_W
303 
            begin
304 
                w_pc_gen_ctl = `PC_NEXT;
305 
                w_stk_op = `STK_NOP;
306 
                w_muxa_ctl = `MUXA_W;
307 
                w_muxb_ctl = `MUXB_REG;
308 
                w_alu_op = `ALU_SUB;
309 
                w_mem_wr = `DIS;
310 
                w_w_wr = `EN;
311 
                w_z_wr = `EN;
312 
                w_c_wr = `EN;
313 
                w_brc_ctl = `BG_NOP;
314 
            end //end of SUBWF_W ;
315 
 
316 
            12'b0000_101X_XXXX:
317 
                //REPLACE ID = SUBWF_F
318 
                //REPLACE ID = SUBWF_F
319 
            begin
320 
                w_pc_gen_ctl = `PC_NEXT;
321 
                w_stk_op = `STK_NOP;
322 
                w_muxa_ctl = `MUXA_W;
323 
                w_muxb_ctl = `MUXB_REG;
324 
                w_alu_op = `ALU_SUB;
325 
                w_mem_wr = `EN;
326 
                w_w_wr = `DIS;
327 
                w_z_wr = `EN;
328 
                w_c_wr = `EN;
329 
                w_brc_ctl = `BG_NOP;
330 
            end //end of SUBWF_F ;
331 
 
332 
            12'b0000_110X_XXXX:
333 
                //REPLACE ID = DECF_W
334 
                //REPLACE ID = DECF_W
335 
            begin
336 
                w_pc_gen_ctl = `PC_NEXT;
337 
                w_stk_op = `STK_NOP;
338 
                w_muxa_ctl = `MUXA_IGN;
339 
                w_muxb_ctl = `MUXB_REG;
340 
                w_alu_op = `ALU_DEC;
341 
                w_mem_wr = `DIS;
342 
                w_w_wr = `EN;
343 
                w_z_wr = `EN;
344 
                w_c_wr = `DIS;
345 
                w_brc_ctl = `BG_NOP;
346 
            end //end of DECF_W ;
347 
 
348 
 
349 
            12'b0000_111X_XXXX:
350 
                //REPLACE ID = DECF_F
351 
                //REPLACE ID = DECF_F
352 
            begin
353 
                w_pc_gen_ctl = `PC_NEXT;
354 
                w_stk_op = `STK_NOP;
355 
                w_muxa_ctl = `MUXA_IGN;
356 
                w_muxb_ctl = `MUXB_REG;
357 
                w_alu_op = `ALU_DEC;
358 
                w_mem_wr = `EN;
359 
                w_w_wr = `DIS;
360 
                w_z_wr = `EN;
361 
                w_c_wr = `DIS;
362 
                w_brc_ctl = `BG_NOP;
363 
            end //end of DECF_F ;
364 
 
365 
            12'b0001_000X_XXXX:
366 
                //REPLACE ID = IORWF_W
367 
                //REPLACE ID = IORWF_W
368 
            begin
369 
                w_pc_gen_ctl = `PC_NEXT;
370 
                w_stk_op = `STK_NOP;
371 
                w_muxa_ctl = `MUXA_W;
372 
                w_muxb_ctl = `MUXB_EK;
373 
                w_alu_op = `ALU_OR;
374 
                w_mem_wr = `DIS;
375 
                w_w_wr = `EN;
376 
                w_z_wr = `EN;
377 
                w_c_wr = `DIS;
378 
                w_brc_ctl = `BG_NOP;
379 
            end //end of IORWF_W ;
380 
 
381 
 
382 
 
383 
            12'b0001_001X_XXXX:
384 
                //REPLACE ID = IORWF_F
385 
                //REPLACE ID = IORWF_F
386 
            begin
387 
                w_pc_gen_ctl = `PC_NEXT;
388 
                w_stk_op = `STK_NOP;
389 
                w_muxa_ctl = `MUXA_W;
390 
                w_muxb_ctl = `MUXB_EK;
391 
                w_alu_op = `ALU_OR;
392 
                w_mem_wr = `EN;
393 
                w_w_wr = `DIS;
394 
                w_z_wr = `EN;
395 
                w_c_wr = `DIS;
396 
                w_brc_ctl = `BG_NOP;
397 
            end //end of IORWF_F ;
398 
 
399 
            12'b0001_010X_XXXX:
400 
                //REPLACE ID = ANDWF_W
401 
                //REPLACE ID = ANDWF_W
402 
            begin
403 
                w_pc_gen_ctl = `PC_NEXT;
404 
                w_stk_op = `STK_NOP;
405 
                w_muxa_ctl = `MUXA_W;
406 
                w_muxb_ctl = `MUXB_EK;
407 
                w_alu_op = `ALU_AND;
408 
                w_mem_wr = `DIS;
409 
                w_w_wr = `EN;
410 
                w_z_wr = `EN;
411 
                w_c_wr = `DIS;
412 
                w_brc_ctl = `BG_NOP;
413 
            end //end of ANDWF_W ;
414 
 
415 
            12'b0001_011X_XXXX:
416 
                //REPLACE ID = ANDWF_F
417 
                //REPLACE ID = ANDWF_F
418 
            begin
419 
                w_pc_gen_ctl = `PC_NEXT;
420 
                w_stk_op = `STK_NOP;
421 
                w_muxa_ctl = `MUXA_W;
422 
                w_muxb_ctl = `MUXB_EK;
423 
                w_alu_op = `ALU_AND;
424 
                w_mem_wr = `EN;
425 
                w_w_wr = `DIS;
426 
                w_z_wr = `EN;
427 
                w_c_wr = `DIS;
428 
                w_brc_ctl = `BG_NOP;
429 
            end //end of ANDWF_F ;
430 
 
431 
            12'b0001_100X_XXXX:
432 
                //REPLACE ID = XORWF_W
433 
                //REPLACE ID = XORWF_W
434 
            begin
435 
                w_pc_gen_ctl = `PC_NEXT;
436 
                w_stk_op = `STK_NOP;
437 
                w_muxa_ctl = `MUXA_W;
438 
                w_muxb_ctl = `MUXB_REG;
439 
                w_alu_op = `ALU_XOR;
440 
                w_mem_wr = `DIS;
441 
                w_w_wr = `EN;
442 
                w_z_wr = `EN;
443 
                w_c_wr = `DIS;
444 
                w_brc_ctl = `BG_NOP;
445 
            end //end of XORWF_W ;
446 
 
447 
            12'b0001_101X_XXXX:
448 
                //REPLACE ID = XORWF_F
449 
                //REPLACE ID = XORWF_F
450 
            begin
451 
                w_pc_gen_ctl = `PC_NEXT;
452 
                w_stk_op = `STK_NOP;
453 
                w_muxa_ctl = `MUXA_W;
454 
                w_muxb_ctl = `MUXB_REG;
455 
                w_alu_op = `ALU_XOR;
456 
                w_mem_wr = `EN;
457 
                w_w_wr = `DIS;
458 
                w_z_wr = `EN;
459 
                w_c_wr = `DIS;
460 
                w_brc_ctl = `BG_NOP;
461 
            end //end of XORWF_F ;
462 
 
463 
            12'b0001_110X_XXXX:
464 
                //REPLACE ID = ADDWF_W
465 
                //REPLACE ID = ADDWF_W
466 
            begin
467 
                w_pc_gen_ctl = `PC_NEXT;
468 
                w_stk_op = `STK_NOP;
469 
                w_muxa_ctl = `MUXA_W;
470 
                w_muxb_ctl = `MUXB_REG;
471 
                w_alu_op = `ALU_ADD;
472 
                w_mem_wr = `DIS;
473 
                w_w_wr = `EN;
474 
                w_z_wr = `EN;
475 
                w_c_wr = `EN;
476 
                w_brc_ctl = `BG_NOP;
477 
            end //end of ADDWF_W ;
478 
 
479 
            12'b0001_111X_XXXX:
480 
                //REPLACE ID = ADDWF_F
481 
                //REPLACE ID = ADDWF_F
482 
            begin
483 
                w_pc_gen_ctl = `PC_NEXT;
484 
                w_stk_op = `STK_NOP;
485 
                w_muxa_ctl = `MUXA_W;
486 
                w_muxb_ctl = `MUXB_REG;
487 
                w_alu_op = `ALU_ADD;
488 
                w_mem_wr = `EN;
489 
                w_w_wr = `DIS;
490 
                w_z_wr = `EN;
491 
                w_c_wr = `EN;
492 
                w_brc_ctl = `BG_NOP;
493 
            end //end of ADDWF_F ;
494 
 
495 
            12'b0010_000X_XXXX:
496 
                //REPLACE ID = MOVF_W
497 
                //REPLACE ID = MOVF_W
498 
            begin
499 
                w_pc_gen_ctl = `PC_NEXT;
500 
                w_stk_op = `STK_NOP;
501 
                w_muxa_ctl = `MUXA_IGN;
502 
                w_muxb_ctl = `MUXB_REG;
503 
                w_alu_op = `ALU_PB;
504 
                w_mem_wr = `DIS;
505 
                w_w_wr = `EN;
506 
                w_z_wr = `EN;
507 
                w_c_wr = `DIS;
508 
                w_brc_ctl = `BG_NOP;
509 
            end //end of MOVF_W ;
510 
 
511 
 
512 
            12'b0010_001X_XXXX:
513 
                //REPLACE ID = MOVF_F
514 
                //REPLACE ID = MOVF_F
515 
            begin
516 
                w_pc_gen_ctl = `PC_NEXT;
517 
                w_stk_op = `STK_NOP;
518 
                w_muxa_ctl = `MUXA_W;
519 
                w_muxb_ctl = `MUXB_REG;
520 
                w_alu_op = `ALU_PB;
521 
                w_mem_wr = `DIS;//Also can be set as EN
522 
                w_w_wr = `DIS;
523 
                w_z_wr = `EN;
524 
                w_c_wr = `DIS;
525 
                w_brc_ctl = `BG_NOP;
526 
            end //end of MOVF_F ;
527 
 
528 
            12'b0010_010X_XXXX:
529 
                //REPLACE ID = COMF_W
530 
                //REPLACE ID = COMF_W
531 
            begin
532 
                w_pc_gen_ctl = `PC_NEXT;
533 
                w_stk_op = `STK_NOP;
534 
                w_muxa_ctl = `MUXA_W;
535 
                w_muxb_ctl = `MUXB_REG;
536 
                w_alu_op = `ALU_COM;
537 
                w_mem_wr = `DIS;
538 
                w_w_wr = `EN;
539 
                w_z_wr = `EN;
540 
                w_c_wr = `DIS;
541 
                w_brc_ctl = `BG_NOP;
542 
            end //end of COMF_W ;
543 
 
544 
            12'b0010_011X_XXXX:
545 
                //REPLACE ID = COMF_F
546 
                //REPLACE ID = COMF_F
547 
            begin
548 
                w_pc_gen_ctl = `PC_NEXT;
549 
                w_stk_op = `STK_NOP;
550 
                w_muxa_ctl = `MUXA_IGN;
551 
                w_muxb_ctl = `MUXB_REG;
552 
                w_alu_op = `ALU_COM;
553 
                w_mem_wr = `EN;
554 
                w_w_wr = `DIS;
555 
                w_z_wr = `EN;
556 
                w_c_wr = `DIS;
557 
                w_brc_ctl = `BG_NOP;
558 
            end //end of COMF_F ;
559 
 
560 
            12'b0010_100X_XXXX:
561 
                //REPLACE ID = INCF_W
562 
                //REPLACE ID = INCF_W
563 
            begin
564 
                w_pc_gen_ctl = `PC_NEXT;
565 
                w_stk_op = `STK_NOP;
566 
                w_muxa_ctl = `MUXA_IGN;
567 
                w_muxb_ctl = `MUXB_REG;
568 
                w_alu_op = `ALU_INC;
569 
                w_mem_wr = `DIS;
570 
                w_w_wr = `EN;
571 
                w_z_wr = `EN;
572 
                w_c_wr = `DIS;
573 
                w_brc_ctl = `BG_NOP;
574 
            end //end of INCF_W ;
575 
 
576 
            12'b0010_101X_XXXX:
577 
                //REPLACE ID = INCF_F
578 
                //REPLACE ID = INCF_F
579 
            begin
580 
                w_pc_gen_ctl = `PC_NEXT;
581 
                w_stk_op = `STK_NOP;
582 
                w_muxa_ctl = `MUXA_IGN;
583 
                w_muxb_ctl = `MUXB_REG;
584 
                w_alu_op = `ALU_INC;
585 
                w_mem_wr = `EN;
586 
                w_w_wr = `DIS;
587 
                w_z_wr = `EN;
588 
                w_c_wr = `DIS;
589 
                w_brc_ctl = `BG_NOP;
590 
            end //end of INCF_F ;
591 
 
592 
            12'b0010_110X_XXXX:
593 
                //REPLACE ID = DECFSZ_W
594 
                //REPLACE ID = DECFSZ_W
595 
            begin
596 
                w_pc_gen_ctl = `PC_NEXT;
597 
                w_stk_op = `STK_NOP;
598 
                w_muxa_ctl = `MUXA_IGN;
599 
                w_muxb_ctl = `MUXB_REG;
600 
                w_alu_op = `ALU_DEC;
601 
                w_mem_wr = `DIS;
602 
                w_w_wr = `EN;
603 
                w_z_wr = `DIS;
604 
                w_c_wr = `DIS;
605 
                w_brc_ctl = `BG_ZERO;            //if the result is 0 then the next w_insrction will be discarded
606 
            end //end of DECFSZ_W ;
607 
 
608 
            12'b0010_111X_XXXX:
609 
                //REPLACE ID = DECFSZ_F
610 
                //REPLACE ID = DECFSZ_F
611 
            begin
612 
                w_pc_gen_ctl = `PC_NEXT;
613 
                w_stk_op = `STK_NOP;
614 
                w_muxa_ctl = `MUXA_IGN;
615 
                w_muxb_ctl = `MUXB_REG;
616 
                w_alu_op = `ALU_DEC;
617 
                w_mem_wr = `EN;
618 
                w_w_wr = `DIS;
619 
                w_z_wr = `DIS;
620 
                w_c_wr = `DIS;
621 
                w_brc_ctl = `BG_ZERO;             //if the result is 0 then the next w_insrction will be discarded
622 
            end //end of DECFSZ_F ;
623 
            //checked
624 
 
625 
            12'b0011_000X_XXXX:
626 
                //REPLACE ID = RRF_W
627 
                //REPLACE ID = RRF_W
628 
            begin
629 
                w_pc_gen_ctl = `PC_NEXT;
630 
                w_stk_op = `STK_NOP;
631 
                w_muxa_ctl = `MUXA_IGN;
632 
                w_muxb_ctl = `MUXB_REG;
633 
                w_alu_op = `ALU_ROR;
634 
                w_mem_wr = `DIS;
635 
                w_w_wr = `EN;
636 
                w_z_wr = `DIS;
637 
                w_c_wr = `EN;
638 
                w_brc_ctl = `BG_NOP;
639 
            end //end of RRF_W ;
640 
            //checked
641 
 
642 
            12'b0011_001X_XXXX:
643 
                //REPLACE ID = RRF_F
644 
                //REPLACE ID = RRF_F
645 
            begin
646 
                w_pc_gen_ctl = `PC_NEXT;
647 
                w_stk_op = `STK_NOP;
648 
                w_muxa_ctl = `MUXA_IGN;
649 
                w_muxb_ctl = `MUXB_REG;
650 
                w_alu_op = `ALU_ROR;
651 
                w_mem_wr = `EN;
652 
                w_w_wr = `DIS;
653 
                w_z_wr = `DIS;
654 
                w_c_wr = `EN;
655 
                w_brc_ctl = `BG_NOP;
656 
            end //end of RRF_F ;
657 
 
658 
            //
659 
            12'b0011_010X_XXXX:
660 
                //REPLACE ID = RLF_W
661 
                //REPLACE ID = RLF_W
662 
            begin
663 
                w_pc_gen_ctl = `PC_NEXT;
664 
                w_stk_op = `STK_NOP;
665 
                w_muxa_ctl = `MUXA_IGN;
666 
                w_muxb_ctl = `MUXB_REG;
667 
                w_alu_op = `ALU_ROL;
668 
                w_mem_wr = `DIS;
669 
                w_w_wr = `EN;
670 
                w_z_wr = `DIS;
671 
                w_c_wr = `EN;
672 
                w_brc_ctl = `BG_NOP;
673 
            end //end of RLF_W ;
674 
 
675 
            12'b0011_011X_XXXX:
676 
                //REPLACE ID = RLF_F
677 
                //REPLACE ID = RLF_F
678 
            begin
679 
                w_pc_gen_ctl = `PC_NEXT;
680 
                w_stk_op = `STK_NOP;
681 
                w_muxa_ctl = `MUXA_IGN;
682 
                w_muxb_ctl = `MUXB_REG;
683 
                w_alu_op = `ALU_ROL;
684 
                w_mem_wr = `EN;
685 
                w_w_wr = `DIS;
686 
                w_z_wr = `DIS;
687 
                w_c_wr = `EN;
688 
                w_brc_ctl = `BG_NOP;
689 
            end //end of RLF_F ;
690 
 
691 
            12'b0011_100X_XXXX:
692 
                //REPLACE ID = SWAPF_W
693 
                //REPLACE ID = SWAPF_W
694 
            begin
695 
                w_pc_gen_ctl = `PC_NEXT;
696 
                w_stk_op = `STK_NOP;
697 
                w_muxa_ctl = `MUXA_IGN;
698 
                w_muxb_ctl = `MUXB_REG;
699 
                w_alu_op = `ALU_SWAP;
700 
                w_mem_wr = `DIS;
701 
                w_w_wr = `EN;
702 
                w_z_wr = `DIS;
703 
                w_c_wr = `DIS;
704 
                w_brc_ctl = `BG_NOP;
705 
            end //end of SWAPF_F ;
706 
 
707 
            12'b0011_101X_XXXX:
708 
                //REPLACE ID = SWAPF_F
709 
                //REPLACE ID = SWAPF_F
710 
            begin
711 
                w_pc_gen_ctl = `PC_NEXT;
712 
                w_stk_op = `STK_NOP;
713 
                w_muxa_ctl = `MUXA_IGN;
714 
                w_muxb_ctl = `MUXB_REG;
715 
                w_alu_op = `ALU_SWAP;
716 
                w_mem_wr = `EN;
717 
                w_w_wr = `DIS;
718 
                w_z_wr = `DIS;
719 
                w_c_wr = `DIS;
720 
                w_brc_ctl = `BG_NOP;
721 
            end //end of SWAPF_F ;
722 
 
723 
            12'b0011_110X_XXXX:
724 
                //REPLACE ID = INCFSZ_W
725 
                //REPLACE ID = INCFSZ_W
726 
            begin
727 
                w_pc_gen_ctl = `PC_NEXT;
728 
                w_stk_op = `STK_NOP;
729 
                w_muxa_ctl = `MUXA_W;
730 
                w_muxb_ctl = `MUXB_REG;
731 
                w_alu_op = `ALU_INC;
732 
                w_mem_wr = `DIS;
733 
                w_w_wr = `EN;
734 
                w_z_wr = `DIS;
735 
                w_c_wr = `DIS;
736 
                w_brc_ctl = `BG_ZERO;
737 
            end //end of INCFSZ_W ;
738 
 
739 
            12'b0011_111X_XXXX:
740 
                //REPLACE ID = INCFSZ_F
741 
                //REPLACE ID = INCFSZ_F
742 
            begin
743 
                w_pc_gen_ctl = `PC_NEXT;
744 
                w_stk_op = `STK_NOP;
745 
                w_muxa_ctl = `MUXA_W;
746 
                w_muxb_ctl = `MUXB_REG;
747 
                w_alu_op = `ALU_INC;
748 
                w_mem_wr = `EN;
749 
                w_w_wr = `DIS;
750 
                w_z_wr = `DIS;
751 
                w_c_wr = `DIS;
752 
                w_brc_ctl = `BG_ZERO;
753 
            end //end of INCFSZ_F ;
754 
 
755 
            12'b0100_XXXX_XXXX:
756 
                //REPLACE ID = BCF
757 
                //REPLACE ID = BCF
758 
            begin
759 
                w_pc_gen_ctl = `PC_NEXT;
760 
                w_stk_op = `STK_NOP;
761 
                w_muxa_ctl = `MUXA_BD;
762 
                w_muxb_ctl = `MUXB_REG;
763 
                w_alu_op = `ALU_BCF;
764 
                w_mem_wr = `EN;
765 
                w_w_wr = `DIS;
766 
                w_z_wr = `DIS;
767 
                w_c_wr = `DIS;
768 
                w_brc_ctl = `BG_NOP;
769 
            end //end of BCF ;
770 
 
771 
            12'b0101_XXXX_XXXX:
772 
                //REPLACE ID = BSF
773 
                //REPLACE ID = BSF
774 
            begin
775 
                w_pc_gen_ctl = `PC_NEXT;
776 
                w_stk_op = `STK_NOP;
777 
                w_muxa_ctl = `MUXA_BD;
778 
                w_muxb_ctl = `MUXB_REG;
779 
                w_alu_op = `ALU_BSF;
780 
                w_mem_wr = `EN;
781 
                w_w_wr = `DIS;
782 
                w_z_wr = `DIS;
783 
                w_c_wr = `DIS;
784 
                w_brc_ctl = `BG_NOP;
785 
            end //end of BSF ;
786 
            /**/
787 
 
788 
            12'b0110_XXXX_XXXX:
789 
                //REPLACE ID = BTFSC
790 
                //REPLACE ID = BTFSC
791 
            begin
792 
                w_pc_gen_ctl = `PC_NEXT;
793 
                w_stk_op = `STK_NOP;
794 
                w_muxa_ctl = `MUXA_BD;
795 
                w_muxb_ctl = `MUXB_REG;
796 
                w_alu_op = `ALU_BTFSC;//ALU_BTFSC
797 
                w_mem_wr = `DIS;
798 
                w_w_wr = `DIS;
799 
                w_z_wr = `DIS;
800 
                w_c_wr = `DIS;
801 
                w_brc_ctl = `BG_ZERO;
802 
            end //end of BTFSC ;
803 
 
804 
            12'b0111_XXXX_XXXX:
805 
                //REPLACE ID = BTFSS
806 
                //REPLACE ID = BTFSS
807 
            begin
808 
                w_pc_gen_ctl = `PC_NEXT;
809 
                w_stk_op = `STK_NOP;
810 
                w_muxa_ctl = `MUXA_BD;
811 
                w_muxb_ctl = `MUXB_REG;
812 
                w_alu_op = `ALU_BTFSS;
813 
                w_mem_wr = `DIS;
814 
                w_w_wr = `DIS;
815 
                w_z_wr = `DIS;
816 
                w_c_wr = `DIS;
817 
                w_brc_ctl = `BG_NZERO;
818 
            end //end of BTFSS ;
819 
 
820 
            12'b1000_XXXX_XXXX:
821 
                //REPLACE ID = RETLW
822 
                //REPLACE ID = RETLW
823 
            begin
824 
                w_pc_gen_ctl = `PC_NEXT;
825 
                w_stk_op = `STK_POP;
826 
                w_muxa_ctl = `MUXA_IGN;
827 
                w_muxb_ctl = `MUXB_EK;
828 
                w_alu_op = `ALU_PB;
829 
                w_mem_wr = `DIS;
830 
                w_w_wr = `EN;
831 
                w_z_wr = `DIS;
832 
                w_c_wr = `DIS;
833 
                w_brc_ctl = `BG_NOP;
834 
            end //end of RETLW ;
835 
 
836 
            12'b1001_XXXX_XXXX:
837 
                //REPLACE ID = CALL
838 
                //REPLACE ID = CALL
839 
            begin
840 
                w_pc_gen_ctl = `PC_GOTO;
841 
                w_stk_op = `STK_PSH;
842 
                w_muxa_ctl = `MUXA_IGN;
843 
                w_muxb_ctl = `MUXB_IGN;
844 
                w_alu_op = `ALU_NOP;
845 
                w_mem_wr = `DIS;
846 
                w_w_wr = `DIS;
847 
                w_z_wr = `DIS;
848 
                w_c_wr = `DIS;
849 
                w_brc_ctl = `BG_NOP;
850 
            end //end of CALL ;
851 
 
852 
            12'b101X_XXXX_XXXX:
853 
                //REPLACE ID = GOTO
854 
                //REPLACE ID = GOTO
855 
            begin
856 
                w_pc_gen_ctl = `PC_GOTO;
857 
                w_stk_op = `STK_NOP;
858 
                w_muxa_ctl = `MUXA_IGN;
859 
                w_muxb_ctl = `MUXB_IGN;
860 
                w_alu_op = `ALU_NOP;
861 
                w_mem_wr = `DIS;
862 
                w_w_wr = `DIS;
863 
                w_z_wr = `DIS;
864 
                w_c_wr = `DIS;
865 
                w_brc_ctl = `BG_NOP;
866 
            end //end of GOTO ;
867 
 
868 
            12'b1100_XXXX_XXXX:
869 
                //REPLACE ID = MOVLW
870 
                //REPLACE ID = MOVLW
871 
            begin
872 
                w_pc_gen_ctl = `PC_NEXT;
873 
                w_stk_op = `STK_NOP;
874 
                w_muxa_ctl = `MUXA_IGN;
875 
                w_muxb_ctl = `MUXB_EK;
876 
                w_alu_op = `ALU_PB;
877 
                w_mem_wr = `DIS;
878 
                w_w_wr = `EN;
879 
                w_z_wr = `DIS;
880 
                w_c_wr = `DIS;
881 
                w_brc_ctl = `BG_NOP;
882 
            end //end of MOVLW ;
883 
 
884 
            12'b1101_XXXX_XXXX:
885 
                //REPLACE ID = IORLW
886 
                //REPLACE ID = IORLW
887 
            begin
888 
                w_pc_gen_ctl = `PC_NEXT;
889 
                w_stk_op = `STK_NOP;
890 
                w_muxa_ctl = `MUXA_W;
891 
                w_muxb_ctl = `MUXB_EK;
892 
                w_alu_op = `ALU_OR;
893 
                w_mem_wr = `DIS;
894 
                w_w_wr = `EN;
895 
                w_z_wr = `EN;
896 
                w_c_wr = `DIS;
897 
                w_brc_ctl = `BG_NOP;
898 
            end //end of IORLW ;
899 
 
900 
            12'b1110_XXXX_XXXX:
901 
                //REPLACE ID = ANDLW
902 
                //REPLACE ID = ANDLW
903 
            begin
904 
                w_pc_gen_ctl = `PC_NEXT;
905 
                w_stk_op = `STK_NOP;
906 
                w_muxa_ctl = `MUXA_W;
907 
                w_muxb_ctl = `MUXB_EK;
908 
                w_alu_op = `ALU_AND;
909 
                w_mem_wr = `DIS;
910 
                w_w_wr = `EN;
911 
                w_z_wr = `EN;
912 
                w_c_wr = `DIS;
913 
                w_brc_ctl = `BG_NOP;
914 
            end //end of ANDLW ;
915 
 
916 
            12'b1111_XXXX_XXXX:
917 
                //REPLACE ID = XORLW
918 
                //REPLACE ID = XORLW
919 
            begin
920 
                w_pc_gen_ctl = `PC_NEXT;
921 
                w_stk_op = `STK_NOP;
922 
                w_muxa_ctl = `MUXA_W;
923 
                w_muxb_ctl = `MUXB_EK;
924 
                w_alu_op = `ALU_XOR;
925 
                w_mem_wr = `DIS;
926 
                w_w_wr = `EN;
927 
                w_z_wr = `EN;
928 
                w_c_wr = `DIS;
929 
                w_brc_ctl = `BG_NOP;
930 
            end //end of XORLW ;
931 
 
932 
 
933 
            default:
934 
                //REPLACE ID = NOP
935 
            begin
936 
                w_pc_gen_ctl = `PC_NEXT;
937 
                w_stk_op = `STK_NOP;
938 
                w_muxa_ctl = `MUXA_IGN;
939 
                w_muxb_ctl = `MUXB_IGN;
940 
                w_alu_op = `ALU_NOP;
941 
                w_mem_wr = `DIS;
942 
                w_w_wr = `DIS;
943 
                w_z_wr = `DIS;
944 
                w_c_wr = `DIS;
945 
                w_brc_ctl = `BG_NOP;
946 
            end //end of NOP ;
947 
        endcase
948 
    end
949 
 
950 
endmodule

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