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[/] [lwrisc/] [trunk/] [RTL/] [risc_core.v] - Blame information for rev 7

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`include "clairisc_def.h"
module ClaiRISC_core (
        input clk,
        input rst               ,
        input [7:0] in0,
        input [7:0] in1,
        output [7:0] out0,
        output [7:0] out1
    );
 
    supply0 GND;
    wire w_c_2alu;
    wire w_c_2mem;
    reg w_c_wr;
    reg w_c_wr_r;
    reg w_mem_wr;
    reg w_mem_wr_r;
    reg w_muxa_ctl;
    reg w_muxa_ctl_r;
    reg w_muxb_ctl;
    reg w_reg_muxb_r;
    reg w_skip;
    reg w_w_wr;
    reg w_w_wr_r;
    wire w_z;
    reg w_z_wr;
    reg w_z_wr_r;
    reg [7:0] w_alu_in_a;
    reg [7:0] w_alu_in_b;
    reg [4:0] w_alu_op;
    reg [4:0] w_alu_op_r;
    reg [7:0] w_alu_res;
    wire [1:0] w_bank;
    reg [7:0] w_bd_r;
    reg [1:0] w_brc_ctl;
    reg [1:0] w_br_ctl_r;
    reg [8:0] w_ek_r;
    wire [7:0] w_file_o;
    wire [11:0] w_ins;
    reg [10:0] w_pc;
    reg [2:0] w_pc_gen_ctl;
    reg [10:0] w_pc_nxt;
    wire [6:0] w_rd_addr;
    wire [7:0] w_status;
    reg [1:0] w_stk_op;
    wire [10:0] w_stk_pc;
    reg[4:0] w_wbadd_r;
    wire [4:0] w_wd_addr;
    reg [7:0] w_wreg;
    wire [6:0] w_wr_addr;
 
    always @(posedge clk)
        w_pc<=w_pc_nxt;
 
    reg [10:0]   stack1, stack2, stack3, stack4;
    assign w_stk_pc = stack1;
 
    always @(posedge clk)
    begin
        case (w_stk_op)
            `STK_PSH    :// PUSH stack
            begin
                stack4 <= stack3;
                stack3 <= stack2;
                stack2 <= stack1;
                stack1 <= w_pc;
            end
            `STK_POP    :// POP stack
            begin
                stack1 <= stack2;
                stack2 <= stack3;
                stack3 <= stack4;
            end
            //  default ://do nothing
        endcase
    end
 
    assign         w_rd_addr ={ w_bank[1:0],w_wd_addr[4:0]};
 
    wb_mem_man   mem_man
                 (
                     .bank(w_bank),
                     .c_wr(w_c_wr_r),
                     .ci(w_c_2mem),
                     .clk(clk),
                     .co(w_c_2alu),
                     .din(w_alu_res),
                     .dout(w_file_o),
                     .rd_addr(w_rd_addr),
                     .rst(rst),
                     .status(w_status),
                     .wr_addr(w_wr_addr),
                     .wr_en(w_mem_wr_r),
                     .z_wr(w_z_wr_r),
                     .zi(w_z),
                     .in0(in0),
                     .in1(in1),
                     .out0(out0),
                     .out1(out1)
                 );
 
    always @(posedge clk)
        if (w_skip==1)
            w_alu_op_r<=0;
        else
            w_alu_op_r<=w_alu_op;
 
    always@(posedge clk)
        if (w_skip==1)    w_br_ctl_r<=0;
        else w_br_ctl_r<=w_brc_ctl;
 
    always@(posedge clk)
        if (w_skip==1)    w_z_wr_r<=0;
        else  w_z_wr_r<=w_z_wr;
 
    always @ (posedge clk)
        if (w_skip==1)
            w_c_wr_r<=0;
        else
            w_c_wr_r<=w_c_wr;
 
    always @(posedge clk)
        if(w_skip==1)
            w_mem_wr_r<=0;
        else
            w_mem_wr_r<=w_mem_wr;
 
    always @(posedge clk)
        if (w_w_wr_r==1)
            w_wreg<=w_alu_res;
 
        always @ (posedge clk)
                w_bd_r<=1<<w_ins[7:5];
 
    always @(posedge clk)
        w_w_wr_r <=w_w_wr ;
 
    always @(posedge clk)
        w_ek_r<=w_ins[8:0];
 
    assign w_wd_addr = w_ins[4:0];
 
    always@(posedge clk)
        w_wbadd_r<=w_wd_addr;
 
    assign w_wr_addr = {w_bank[1:0],w_wbadd_r[4:0]};
 
 
    reg         addercout;
    always @(*) begin
        case (w_alu_op_r) // synsys parallel_case
            `ALU_ADD:   {addercout,  w_alu_res}  = w_alu_in_a + w_alu_in_b;
            `ALU_SUB:  {addercout,  w_alu_res}  = w_alu_in_b - w_alu_in_a;
            `ALU_ROR:  {addercout,  w_alu_res}  = {w_alu_in_b[0], w_c_2alu, w_alu_in_b[7:1]};
            `ALU_ROL:  {addercout,  w_alu_res}  = {w_alu_in_b[7],w_alu_in_b[6:0], w_c_2alu};
            `ALU_OR:   {addercout,  w_alu_res}  = {1'bx, w_alu_in_a | w_alu_in_b};
            `ALU_XOR:  {addercout,  w_alu_res}  = {1'bx, w_alu_in_a ^ w_alu_in_b};
            `ALU_COM:  {addercout,  w_alu_res}  = {1'bx, ~w_alu_in_b};
            `ALU_SWAP: {addercout,  w_alu_res}  = {1'bx, w_alu_in_b[3:0], w_alu_in_b[7:4]};
            `ALU_AND,//:  {addercout,  y}  = {1'bx, a & b};
            `ALU_BTFSC,//:  {addercout,  y}  = {1'bx, a & b };
            `ALU_BTFSS: {addercout,  w_alu_res}  = {1'bx, w_alu_in_a & w_alu_in_b };
            `ALU_DEC:   {addercout,  w_alu_res}  = {1'bx, w_alu_in_b - 1};
            `ALU_INC:   {addercout,  w_alu_res}  = {1'bx, 1 + w_alu_in_b};
            `ALU_PA :   {addercout,  w_alu_res}  = {1'bx, w_alu_in_a};
            `ALU_PB :   {addercout,  w_alu_res}  = {1'bx, w_alu_in_b};
            `ALU_BSF :  {addercout,  w_alu_res}  = {1'Bx,w_alu_in_a | w_alu_in_b};
            `ALU_BCF :  {addercout,  w_alu_res}  = {1'bx,~w_alu_in_a & w_alu_in_b};
            default:     {addercout, w_alu_res}  = {1'bx, 8'h00};
        endcase
    end
    assign  w_z = (w_alu_res== 8'h00);
    assign  w_c_2mem =  (w_alu_op_r == `ALU_SUB) ?  ~addercout : addercout;
 
    always @(posedge clk)
        if( w_skip)      w_muxa_ctl_r<=0;
        else
            w_muxa_ctl_r<=       w_muxa_ctl;
 
    always @ (posedge clk)
        if (w_skip)              w_reg_muxb_r<=0;
        else
            w_reg_muxb_r<=      w_muxb_ctl;
 
 
    always@(*)
        if (w_muxa_ctl_r==`MUXA_W)
            w_alu_in_a=w_wreg;
        else
            w_alu_in_a=w_bd_r;
 
 
    always @(*)
        if (w_reg_muxb_r==`MUXB_EK)
            w_alu_in_b=w_ek_r[7:0];
        else w_alu_in_b=w_file_o;
 
    always @(*)
    case (w_br_ctl_r)
        //Z==1 means the ALU result is 0
        //Z==0 means the ALU result is not 0
        `BG_ZERO :w_skip =  (w_z==1);   //if the ALU result is 0 then the next instrction will be discarded
        `BG_NZERO :w_skip = (w_z==0);     //if the ALU result is not zero
        //then skip the next instruction
        default w_skip = 0;
    endcase
 
 
    pram program_rom
         (
             .clk(clk),
             .dout(w_ins),
             .rd_addr(w_pc_nxt)
         );
 
    always @ (*)
        if (rst)
            w_pc_nxt=0;//'h1ff;            //THE RST ENTRY
        else
            if(w_skip)
            begin
                w_pc_nxt = w_pc+1;
            end
            else
            begin
                case(w_pc_gen_ctl)
                    `PC_GOTO,
                    `PC_CALL:    w_pc_nxt= {w_status[7:6],w_ins[8:0]};
                    `PC_RET:    w_pc_nxt= w_stk_pc;
                    default
                    w_pc_nxt= w_pc+1;
                endcase
            end
 
    always @(*) begin
        casex (w_ins)
 
            12'b0000_001X_XXXX:
                //REPLACE ID = MOVWF
                //REPLACE ID = MOVWF
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_IGN;
                w_alu_op = `ALU_PA;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of MOVWF ;
 
            12'b0000_0100_0000:
                //REPLACE ID = CLRW
                //REPLACE ID = CLRW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_IGN;
                w_alu_op = `ALU_ZERO;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of CLRW ;
 
            12'b0000_011X_XXXX:
                //REPLACE ID = CLRF
                //REPLACE ID = CLRF
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_IGN;
                w_alu_op = `ALU_ZERO;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of CLRF ;
 
            12'b0000_100X_XXXX:
                //REPLACE ID = SUBWF_W
                //REPLACE ID = SUBWF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_SUB;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of SUBWF_W ;
 
            12'b0000_101X_XXXX:
                //REPLACE ID = SUBWF_F
                //REPLACE ID = SUBWF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_SUB;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of SUBWF_F ;
 
            12'b0000_110X_XXXX:
                //REPLACE ID = DECF_W
                //REPLACE ID = DECF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_DEC;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of DECF_W ;
 
 
            12'b0000_111X_XXXX:
                //REPLACE ID = DECF_F
                //REPLACE ID = DECF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_DEC;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of DECF_F ;
 
            12'b0001_000X_XXXX:
                //REPLACE ID = IORWF_W
                //REPLACE ID = IORWF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_EK;
                w_alu_op = `ALU_OR;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of IORWF_W ;
 
 
 
            12'b0001_001X_XXXX:
                //REPLACE ID = IORWF_F
                //REPLACE ID = IORWF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_EK;
                w_alu_op = `ALU_OR;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of IORWF_F ;
 
            12'b0001_010X_XXXX:
                //REPLACE ID = ANDWF_W
                //REPLACE ID = ANDWF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_EK;
                w_alu_op = `ALU_AND;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of ANDWF_W ;
 
            12'b0001_011X_XXXX:
                //REPLACE ID = ANDWF_F
                //REPLACE ID = ANDWF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_EK;
                w_alu_op = `ALU_AND;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of ANDWF_F ;
 
            12'b0001_100X_XXXX:
                //REPLACE ID = XORWF_W
                //REPLACE ID = XORWF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_XOR;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of XORWF_W ;
 
            12'b0001_101X_XXXX:
                //REPLACE ID = XORWF_F
                //REPLACE ID = XORWF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_XOR;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of XORWF_F ;
 
            12'b0001_110X_XXXX:
                //REPLACE ID = ADDWF_W
                //REPLACE ID = ADDWF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_ADD;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of ADDWF_W ;
 
            12'b0001_111X_XXXX:
                //REPLACE ID = ADDWF_F
                //REPLACE ID = ADDWF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_ADD;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of ADDWF_F ;
 
            12'b0010_000X_XXXX:
                //REPLACE ID = MOVF_W
                //REPLACE ID = MOVF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_PB;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of MOVF_W ;
 
 
            12'b0010_001X_XXXX:
                //REPLACE ID = MOVF_F
                //REPLACE ID = MOVF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_PB;
                w_mem_wr = `DIS;//Also can be set as EN
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of MOVF_F ;
 
            12'b0010_010X_XXXX:
                //REPLACE ID = COMF_W
                //REPLACE ID = COMF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_COM;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of COMF_W ;
 
            12'b0010_011X_XXXX:
                //REPLACE ID = COMF_F
                //REPLACE ID = COMF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_COM;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of COMF_F ;
 
            12'b0010_100X_XXXX:
                //REPLACE ID = INCF_W
                //REPLACE ID = INCF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_INC;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of INCF_W ;
 
            12'b0010_101X_XXXX:
                //REPLACE ID = INCF_F
                //REPLACE ID = INCF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_INC;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of INCF_F ;
 
            12'b0010_110X_XXXX:
                //REPLACE ID = DECFSZ_W
                //REPLACE ID = DECFSZ_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_DEC;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_ZERO;            //if the result is 0 then the next w_insrction will be discarded
            end //end of DECFSZ_W ;
 
            12'b0010_111X_XXXX:
                //REPLACE ID = DECFSZ_F
                //REPLACE ID = DECFSZ_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_DEC;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_ZERO;             //if the result is 0 then the next w_insrction will be discarded
            end //end of DECFSZ_F ;
            //checked
 
            12'b0011_000X_XXXX:
                //REPLACE ID = RRF_W
                //REPLACE ID = RRF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_ROR;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of RRF_W ;
            //checked
 
            12'b0011_001X_XXXX:
                //REPLACE ID = RRF_F
                //REPLACE ID = RRF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_ROR;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of RRF_F ;
 
            //
            12'b0011_010X_XXXX:
                //REPLACE ID = RLF_W
                //REPLACE ID = RLF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_ROL;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of RLF_W ;
 
            12'b0011_011X_XXXX:
                //REPLACE ID = RLF_F
                //REPLACE ID = RLF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_ROL;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `EN;
                w_brc_ctl = `BG_NOP;
            end //end of RLF_F ;
 
            12'b0011_100X_XXXX:
                //REPLACE ID = SWAPF_W
                //REPLACE ID = SWAPF_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_SWAP;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of SWAPF_F ;
 
            12'b0011_101X_XXXX:
                //REPLACE ID = SWAPF_F
                //REPLACE ID = SWAPF_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_SWAP;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of SWAPF_F ;
 
            12'b0011_110X_XXXX:
                //REPLACE ID = INCFSZ_W
                //REPLACE ID = INCFSZ_W
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_INC;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_ZERO;
            end //end of INCFSZ_W ;
 
            12'b0011_111X_XXXX:
                //REPLACE ID = INCFSZ_F
                //REPLACE ID = INCFSZ_F
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_INC;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_ZERO;
            end //end of INCFSZ_F ;
 
            12'b0100_XXXX_XXXX:
                //REPLACE ID = BCF
                //REPLACE ID = BCF
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_BD;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_BCF;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of BCF ;
 
            12'b0101_XXXX_XXXX:
                //REPLACE ID = BSF
                //REPLACE ID = BSF
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_BD;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_BSF;
                w_mem_wr = `EN;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of BSF ;
            /**/
 
            12'b0110_XXXX_XXXX:
                //REPLACE ID = BTFSC
                //REPLACE ID = BTFSC
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_BD;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_BTFSC;//ALU_BTFSC
                w_mem_wr = `DIS;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_ZERO;
            end //end of BTFSC ;
 
            12'b0111_XXXX_XXXX:
                //REPLACE ID = BTFSS
                //REPLACE ID = BTFSS
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_BD;
                w_muxb_ctl = `MUXB_REG;
                w_alu_op = `ALU_BTFSS;
                w_mem_wr = `DIS;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NZERO;
            end //end of BTFSS ;
 
            12'b1000_XXXX_XXXX:
                //REPLACE ID = RETLW
                //REPLACE ID = RETLW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_POP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_EK;
                w_alu_op = `ALU_PB;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of RETLW ;
 
            12'b1001_XXXX_XXXX:
                //REPLACE ID = CALL
                //REPLACE ID = CALL
            begin
                w_pc_gen_ctl = `PC_GOTO;
                w_stk_op = `STK_PSH;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_IGN;
                w_alu_op = `ALU_NOP;
                w_mem_wr = `DIS;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of CALL ;
 
            12'b101X_XXXX_XXXX:
                //REPLACE ID = GOTO
                //REPLACE ID = GOTO
            begin
                w_pc_gen_ctl = `PC_GOTO;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_IGN;
                w_alu_op = `ALU_NOP;
                w_mem_wr = `DIS;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of GOTO ;
 
            12'b1100_XXXX_XXXX:
                //REPLACE ID = MOVLW
                //REPLACE ID = MOVLW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_EK;
                w_alu_op = `ALU_PB;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of MOVLW ;
 
            12'b1101_XXXX_XXXX:
                //REPLACE ID = IORLW
                //REPLACE ID = IORLW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_EK;
                w_alu_op = `ALU_OR;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of IORLW ;
 
            12'b1110_XXXX_XXXX:
                //REPLACE ID = ANDLW
                //REPLACE ID = ANDLW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_EK;
                w_alu_op = `ALU_AND;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of ANDLW ;
 
            12'b1111_XXXX_XXXX:
                //REPLACE ID = XORLW
                //REPLACE ID = XORLW
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_W;
                w_muxb_ctl = `MUXB_EK;
                w_alu_op = `ALU_XOR;
                w_mem_wr = `DIS;
                w_w_wr = `EN;
                w_z_wr = `EN;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of XORLW ;
 
 
            default:
                //REPLACE ID = NOP
            begin
                w_pc_gen_ctl = `PC_NEXT;
                w_stk_op = `STK_NOP;
                w_muxa_ctl = `MUXA_IGN;
                w_muxb_ctl = `MUXB_IGN;
                w_alu_op = `ALU_NOP;
                w_mem_wr = `DIS;
                w_w_wr = `DIS;
                w_z_wr = `DIS;
                w_c_wr = `DIS;
                w_brc_ctl = `BG_NOP;
            end //end of NOP ;
        endcase
    end
 
endmodule

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[/] [lwrisc/] [trunk/] [RTL/] [risc_core.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	mcupro	`include "clairisc_def.h"
2			`module ClaiRISC_core (`
3			`input clk,`
4			`input rst ,`
5			`input [7:0] in0,`
6			`input [7:0] in1,`
7			`output [7:0] out0,`
8			`output [7:0] out1`
9			`);`
10
11			`supply0 GND;`
12			`wire w_c_2alu;`
13			`wire w_c_2mem;`
14			`reg w_c_wr;`
15			`reg w_c_wr_r;`
16			`reg w_mem_wr;`
17			`reg w_mem_wr_r;`
18			`reg w_muxa_ctl;`
19			`reg w_muxa_ctl_r;`
20			`reg w_muxb_ctl;`
21			`reg w_reg_muxb_r;`
22			`reg w_skip;`
23			`reg w_w_wr;`
24			`reg w_w_wr_r;`
25			`wire w_z;`
26			`reg w_z_wr;`
27			`reg w_z_wr_r;`
28			`reg [7:0] w_alu_in_a;`
29			`reg [7:0] w_alu_in_b;`
30			`reg [4:0] w_alu_op;`
31			`reg [4:0] w_alu_op_r;`
32			`reg [7:0] w_alu_res;`
33			`wire [1:0] w_bank;`
34			`reg [7:0] w_bd_r;`
35			`reg [1:0] w_brc_ctl;`
36			`reg [1:0] w_br_ctl_r;`
37			`reg [8:0] w_ek_r;`
38			`wire [7:0] w_file_o;`
39			`wire [11:0] w_ins;`
40			`reg [10:0] w_pc;`
41			`reg [2:0] w_pc_gen_ctl;`
42			`reg [10:0] w_pc_nxt;`
43			`wire [6:0] w_rd_addr;`
44			`wire [7:0] w_status;`
45			`reg [1:0] w_stk_op;`
46			`wire [10:0] w_stk_pc;`
47			`reg[4:0] w_wbadd_r;`
48			`wire [4:0] w_wd_addr;`
49			`reg [7:0] w_wreg;`
50			`wire [6:0] w_wr_addr;`
51
52			`always @(posedge clk)`
53			`w_pc<=w_pc_nxt;`
54
55			`reg [10:0] stack1, stack2, stack3, stack4;`
56			`assign w_stk_pc = stack1;`
57
58			`always @(posedge clk)`
59			`begin`
60			`case (w_stk_op)`
61			`STK_PSH :// PUSH stack
62			`begin`
63			`stack4 <= stack3;`
64			`stack3 <= stack2;`
65			`stack2 <= stack1;`
66			`stack1 <= w_pc;`
67			`end`
68			`STK_POP :// POP stack
69			`begin`
70			`stack1 <= stack2;`
71			`stack2 <= stack3;`
72			`stack3 <= stack4;`
73			`end`
74			`// default ://do nothing`
75			`endcase`
76			`end`
77
78			`assign w_rd_addr ={ w_bank[1:0],w_wd_addr[4:0]};`
79
80			`wb_mem_man mem_man`
81			`(`
82			`.bank(w_bank),`
83			`.c_wr(w_c_wr_r),`
84			`.ci(w_c_2mem),`
85			`.clk(clk),`
86			`.co(w_c_2alu),`
87			`.din(w_alu_res),`
88			`.dout(w_file_o),`
89			`.rd_addr(w_rd_addr),`
90			`.rst(rst),`
91			`.status(w_status),`
92			`.wr_addr(w_wr_addr),`
93			`.wr_en(w_mem_wr_r),`
94			`.z_wr(w_z_wr_r),`
95			`.zi(w_z),`
96			`.in0(in0),`
97			`.in1(in1),`
98			`.out0(out0),`
99			`.out1(out1)`
100			`);`
101
102			`always @(posedge clk)`
103			`if (w_skip==1)`
104			`w_alu_op_r<=0;`
105			`else`
106			`w_alu_op_r<=w_alu_op;`
107
108			`always@(posedge clk)`
109			`if (w_skip==1) w_br_ctl_r<=0;`
110			`else w_br_ctl_r<=w_brc_ctl;`
111
112			`always@(posedge clk)`
113			`if (w_skip==1) w_z_wr_r<=0;`
114			`else w_z_wr_r<=w_z_wr;`
115
116			`always @ (posedge clk)`
117			`if (w_skip==1)`
118			`w_c_wr_r<=0;`
119			`else`
120			`w_c_wr_r<=w_c_wr;`
121
122			`always @(posedge clk)`
123			`if(w_skip==1)`
124			`w_mem_wr_r<=0;`
125			`else`
126			`w_mem_wr_r<=w_mem_wr;`
127
128			`always @(posedge clk)`
129			`if (w_w_wr_r==1)`
130			`w_wreg<=w_alu_res;`
131
132			`always @ (posedge clk)`
133			`w_bd_r<=1<<w_ins[7:5];`
134
135			`always @(posedge clk)`
136			`w_w_wr_r <=w_w_wr ;`
137
138			`always @(posedge clk)`
139			`w_ek_r<=w_ins[8:0];`
140
141			`assign w_wd_addr = w_ins[4:0];`
142
143			`always@(posedge clk)`
144			`w_wbadd_r<=w_wd_addr;`
145
146			`assign w_wr_addr = {w_bank[1:0],w_wbadd_r[4:0]};`
147
148
149			`reg addercout;`
150			`always @(*) begin`
151			`case (w_alu_op_r) // synsys parallel_case`
152			`ALU_ADD: {addercout, w_alu_res} = w_alu_in_a + w_alu_in_b;
153			`ALU_SUB: {addercout, w_alu_res} = w_alu_in_b - w_alu_in_a;
154			`ALU_ROR: {addercout, w_alu_res} = {w_alu_in_b[0], w_c_2alu, w_alu_in_b[7:1]};
155			`ALU_ROL: {addercout, w_alu_res} = {w_alu_in_b[7],w_alu_in_b[6:0], w_c_2alu};
156			`ALU_OR: {addercout, w_alu_res} = {1'bx, w_alu_in_a \| w_alu_in_b};
157			`ALU_XOR: {addercout, w_alu_res} = {1'bx, w_alu_in_a ^ w_alu_in_b};
158			`ALU_COM: {addercout, w_alu_res} = {1'bx, ~w_alu_in_b};
159			`ALU_SWAP: {addercout, w_alu_res} = {1'bx, w_alu_in_b[3:0], w_alu_in_b[7:4]};
160			`ALU_AND,//: {addercout, y} = {1'bx, a & b};
161			`ALU_BTFSC,//: {addercout, y} = {1'bx, a & b };
162			`ALU_BTFSS: {addercout, w_alu_res} = {1'bx, w_alu_in_a & w_alu_in_b };
163			`ALU_DEC: {addercout, w_alu_res} = {1'bx, w_alu_in_b - 1};
164			`ALU_INC: {addercout, w_alu_res} = {1'bx, 1 + w_alu_in_b};
165			`ALU_PA : {addercout, w_alu_res} = {1'bx, w_alu_in_a};
166			`ALU_PB : {addercout, w_alu_res} = {1'bx, w_alu_in_b};
167			`ALU_BSF : {addercout, w_alu_res} = {1'Bx,w_alu_in_a \| w_alu_in_b};
168			`ALU_BCF : {addercout, w_alu_res} = {1'bx,~w_alu_in_a & w_alu_in_b};
169			`default: {addercout, w_alu_res} = {1'bx, 8'h00};`
170			`endcase`
171			`end`
172			`assign w_z = (w_alu_res== 8'h00);`
173			assign w_c_2mem = (w_alu_op_r == `ALU_SUB) ? ~addercout : addercout;
174
175			`always @(posedge clk)`
176			`if( w_skip) w_muxa_ctl_r<=0;`
177			`else`
178			`w_muxa_ctl_r<= w_muxa_ctl;`
179
180			`always @ (posedge clk)`
181			`if (w_skip) w_reg_muxb_r<=0;`
182			`else`
183			`w_reg_muxb_r<= w_muxb_ctl;`
184
185
186			`always@(*)`
187			if (w_muxa_ctl_r==`MUXA_W)
188			`w_alu_in_a=w_wreg;`
189			`else`
190			`w_alu_in_a=w_bd_r;`
191
192
193			`always @(*)`
194			if (w_reg_muxb_r==`MUXB_EK)
195			`w_alu_in_b=w_ek_r[7:0];`
196			`else w_alu_in_b=w_file_o;`
197
198			`always @(*)`
199			`case (w_br_ctl_r)`
200			`//Z==1 means the ALU result is 0`
201			`//Z==0 means the ALU result is not 0`
202			`BG_ZERO :w_skip = (w_z==1); //if the ALU result is 0 then the next instrction will be discarded
203			`BG_NZERO :w_skip = (w_z==0); //if the ALU result is not zero
204			`//then skip the next instruction`
205			`default w_skip = 0;`
206			`endcase`
207
208
209			`pram program_rom`
210			`(`
211			`.clk(clk),`
212			`.dout(w_ins),`
213			`.rd_addr(w_pc_nxt)`
214			`);`
215
216			`always @ (*)`
217			`if (rst)`
218			`w_pc_nxt=0;//'h1ff; //THE RST ENTRY`
219			`else`
220			`if(w_skip)`
221			`begin`
222			`w_pc_nxt = w_pc+1;`
223			`end`
224			`else`
225			`begin`
226			`case(w_pc_gen_ctl)`
227			`PC_GOTO,
228			`PC_CALL: w_pc_nxt= {w_status[7:6],w_ins[8:0]};
229			`PC_RET: w_pc_nxt= w_stk_pc;
230			`default`
231			`w_pc_nxt= w_pc+1;`
232			`endcase`
233			`end`
234
235			`always @(*) begin`
236			`casex (w_ins)`
237
238			`12'b0000_001X_XXXX:`
239			`//REPLACE ID = MOVWF`
240			`//REPLACE ID = MOVWF`
241			`begin`
242			w_pc_gen_ctl = `PC_NEXT;
243			w_stk_op = `STK_NOP;
244			w_muxa_ctl = `MUXA_W;
245			w_muxb_ctl = `MUXB_IGN;
246			w_alu_op = `ALU_PA;
247			w_mem_wr = `EN;
248			w_w_wr = `DIS;
249			w_z_wr = `DIS;
250			w_c_wr = `DIS;
251			w_brc_ctl = `BG_NOP;
252			`end //end of MOVWF ;`
253
254			`12'b0000_0100_0000:`
255			`//REPLACE ID = CLRW`
256			`//REPLACE ID = CLRW`
257			`begin`
258			w_pc_gen_ctl = `PC_NEXT;
259			w_stk_op = `STK_NOP;
260			w_muxa_ctl = `MUXA_IGN;
261			w_muxb_ctl = `MUXB_IGN;
262			w_alu_op = `ALU_ZERO;
263			w_mem_wr = `DIS;
264			w_w_wr = `EN;
265			w_z_wr = `EN;
266			w_c_wr = `DIS;
267			w_brc_ctl = `BG_NOP;
268			`end //end of CLRW ;`
269
270			`12'b0000_011X_XXXX:`
271			`//REPLACE ID = CLRF`
272			`//REPLACE ID = CLRF`
273			`begin`
274			w_pc_gen_ctl = `PC_NEXT;
275			w_stk_op = `STK_NOP;
276			w_muxa_ctl = `MUXA_IGN;
277			w_muxb_ctl = `MUXB_IGN;
278			w_alu_op = `ALU_ZERO;
279			w_mem_wr = `EN;
280			w_w_wr = `DIS;
281			w_z_wr = `EN;
282			w_c_wr = `DIS;
283			w_brc_ctl = `BG_NOP;
284			`end //end of CLRF ;`
285
286			`12'b0000_100X_XXXX:`
287			`//REPLACE ID = SUBWF_W`
288			`//REPLACE ID = SUBWF_W`
289			`begin`
290			w_pc_gen_ctl = `PC_NEXT;
291			w_stk_op = `STK_NOP;
292			w_muxa_ctl = `MUXA_W;
293			w_muxb_ctl = `MUXB_REG;
294			w_alu_op = `ALU_SUB;
295			w_mem_wr = `DIS;
296			w_w_wr = `EN;
297			w_z_wr = `EN;
298			w_c_wr = `EN;
299			w_brc_ctl = `BG_NOP;
300			`end //end of SUBWF_W ;`
301
302			`12'b0000_101X_XXXX:`
303			`//REPLACE ID = SUBWF_F`
304			`//REPLACE ID = SUBWF_F`
305			`begin`
306			w_pc_gen_ctl = `PC_NEXT;
307			w_stk_op = `STK_NOP;
308			w_muxa_ctl = `MUXA_W;
309			w_muxb_ctl = `MUXB_REG;
310			w_alu_op = `ALU_SUB;
311			w_mem_wr = `EN;
312			w_w_wr = `DIS;
313			w_z_wr = `EN;
314			w_c_wr = `EN;
315			w_brc_ctl = `BG_NOP;
316			`end //end of SUBWF_F ;`
317
318			`12'b0000_110X_XXXX:`
319			`//REPLACE ID = DECF_W`
320			`//REPLACE ID = DECF_W`
321			`begin`
322			w_pc_gen_ctl = `PC_NEXT;
323			w_stk_op = `STK_NOP;
324			w_muxa_ctl = `MUXA_IGN;
325			w_muxb_ctl = `MUXB_REG;
326			w_alu_op = `ALU_DEC;
327			w_mem_wr = `DIS;
328			w_w_wr = `EN;
329			w_z_wr = `EN;
330			w_c_wr = `DIS;
331			w_brc_ctl = `BG_NOP;
332			`end //end of DECF_W ;`
333
334
335			`12'b0000_111X_XXXX:`
336			`//REPLACE ID = DECF_F`
337			`//REPLACE ID = DECF_F`
338			`begin`
339			w_pc_gen_ctl = `PC_NEXT;
340			w_stk_op = `STK_NOP;
341			w_muxa_ctl = `MUXA_IGN;
342			w_muxb_ctl = `MUXB_REG;
343			w_alu_op = `ALU_DEC;
344			w_mem_wr = `EN;
345			w_w_wr = `DIS;
346			w_z_wr = `EN;
347			w_c_wr = `DIS;
348			w_brc_ctl = `BG_NOP;
349			`end //end of DECF_F ;`
350
351			`12'b0001_000X_XXXX:`
352			`//REPLACE ID = IORWF_W`
353			`//REPLACE ID = IORWF_W`
354			`begin`
355			w_pc_gen_ctl = `PC_NEXT;
356			w_stk_op = `STK_NOP;
357			w_muxa_ctl = `MUXA_W;
358			w_muxb_ctl = `MUXB_EK;
359			w_alu_op = `ALU_OR;
360			w_mem_wr = `DIS;
361			w_w_wr = `EN;
362			w_z_wr = `EN;
363			w_c_wr = `DIS;
364			w_brc_ctl = `BG_NOP;
365			`end //end of IORWF_W ;`
366
367
368
369			`12'b0001_001X_XXXX:`
370			`//REPLACE ID = IORWF_F`
371			`//REPLACE ID = IORWF_F`
372			`begin`
373			w_pc_gen_ctl = `PC_NEXT;
374			w_stk_op = `STK_NOP;
375			w_muxa_ctl = `MUXA_W;
376			w_muxb_ctl = `MUXB_EK;
377			w_alu_op = `ALU_OR;
378			w_mem_wr = `EN;
379			w_w_wr = `DIS;
380			w_z_wr = `EN;
381			w_c_wr = `DIS;
382			w_brc_ctl = `BG_NOP;
383			`end //end of IORWF_F ;`
384
385			`12'b0001_010X_XXXX:`
386			`//REPLACE ID = ANDWF_W`
387			`//REPLACE ID = ANDWF_W`
388			`begin`
389			w_pc_gen_ctl = `PC_NEXT;
390			w_stk_op = `STK_NOP;
391			w_muxa_ctl = `MUXA_W;
392			w_muxb_ctl = `MUXB_EK;
393			w_alu_op = `ALU_AND;
394			w_mem_wr = `DIS;
395			w_w_wr = `EN;
396			w_z_wr = `EN;
397			w_c_wr = `DIS;
398			w_brc_ctl = `BG_NOP;
399			`end //end of ANDWF_W ;`
400
401			`12'b0001_011X_XXXX:`
402			`//REPLACE ID = ANDWF_F`
403			`//REPLACE ID = ANDWF_F`
404			`begin`
405			w_pc_gen_ctl = `PC_NEXT;
406			w_stk_op = `STK_NOP;
407			w_muxa_ctl = `MUXA_W;
408			w_muxb_ctl = `MUXB_EK;
409			w_alu_op = `ALU_AND;
410			w_mem_wr = `EN;
411			w_w_wr = `DIS;
412			w_z_wr = `EN;
413			w_c_wr = `DIS;
414			w_brc_ctl = `BG_NOP;
415			`end //end of ANDWF_F ;`
416
417			`12'b0001_100X_XXXX:`
418			`//REPLACE ID = XORWF_W`
419			`//REPLACE ID = XORWF_W`
420			`begin`
421			w_pc_gen_ctl = `PC_NEXT;
422			w_stk_op = `STK_NOP;
423			w_muxa_ctl = `MUXA_W;
424			w_muxb_ctl = `MUXB_REG;
425			w_alu_op = `ALU_XOR;
426			w_mem_wr = `DIS;
427			w_w_wr = `EN;
428			w_z_wr = `EN;
429			w_c_wr = `DIS;
430			w_brc_ctl = `BG_NOP;
431			`end //end of XORWF_W ;`
432
433			`12'b0001_101X_XXXX:`
434			`//REPLACE ID = XORWF_F`
435			`//REPLACE ID = XORWF_F`
436			`begin`
437			w_pc_gen_ctl = `PC_NEXT;
438			w_stk_op = `STK_NOP;
439			w_muxa_ctl = `MUXA_W;
440			w_muxb_ctl = `MUXB_REG;
441			w_alu_op = `ALU_XOR;
442			w_mem_wr = `EN;
443			w_w_wr = `DIS;
444			w_z_wr = `EN;
445			w_c_wr = `DIS;
446			w_brc_ctl = `BG_NOP;
447			`end //end of XORWF_F ;`
448
449			`12'b0001_110X_XXXX:`
450			`//REPLACE ID = ADDWF_W`
451			`//REPLACE ID = ADDWF_W`
452			`begin`
453			w_pc_gen_ctl = `PC_NEXT;
454			w_stk_op = `STK_NOP;
455			w_muxa_ctl = `MUXA_W;
456			w_muxb_ctl = `MUXB_REG;
457			w_alu_op = `ALU_ADD;
458			w_mem_wr = `DIS;
459			w_w_wr = `EN;
460			w_z_wr = `EN;
461			w_c_wr = `EN;
462			w_brc_ctl = `BG_NOP;
463			`end //end of ADDWF_W ;`
464
465			`12'b0001_111X_XXXX:`
466			`//REPLACE ID = ADDWF_F`
467			`//REPLACE ID = ADDWF_F`
468			`begin`
469			w_pc_gen_ctl = `PC_NEXT;
470			w_stk_op = `STK_NOP;
471			w_muxa_ctl = `MUXA_W;
472			w_muxb_ctl = `MUXB_REG;
473			w_alu_op = `ALU_ADD;
474			w_mem_wr = `EN;
475			w_w_wr = `DIS;
476			w_z_wr = `EN;
477			w_c_wr = `EN;
478			w_brc_ctl = `BG_NOP;
479			`end //end of ADDWF_F ;`
480
481			`12'b0010_000X_XXXX:`
482			`//REPLACE ID = MOVF_W`
483			`//REPLACE ID = MOVF_W`
484			`begin`
485			w_pc_gen_ctl = `PC_NEXT;
486			w_stk_op = `STK_NOP;
487			w_muxa_ctl = `MUXA_IGN;
488			w_muxb_ctl = `MUXB_REG;
489			w_alu_op = `ALU_PB;
490			w_mem_wr = `DIS;
491			w_w_wr = `EN;
492			w_z_wr = `EN;
493			w_c_wr = `DIS;
494			w_brc_ctl = `BG_NOP;
495			`end //end of MOVF_W ;`
496
497
498			`12'b0010_001X_XXXX:`
499			`//REPLACE ID = MOVF_F`
500			`//REPLACE ID = MOVF_F`
501			`begin`
502			w_pc_gen_ctl = `PC_NEXT;
503			w_stk_op = `STK_NOP;
504			w_muxa_ctl = `MUXA_W;
505			w_muxb_ctl = `MUXB_REG;
506			w_alu_op = `ALU_PB;
507			w_mem_wr = `DIS;//Also can be set as EN
508			w_w_wr = `DIS;
509			w_z_wr = `EN;
510			w_c_wr = `DIS;
511			w_brc_ctl = `BG_NOP;
512			`end //end of MOVF_F ;`
513
514			`12'b0010_010X_XXXX:`
515			`//REPLACE ID = COMF_W`
516			`//REPLACE ID = COMF_W`
517			`begin`
518			w_pc_gen_ctl = `PC_NEXT;
519			w_stk_op = `STK_NOP;
520			w_muxa_ctl = `MUXA_W;
521			w_muxb_ctl = `MUXB_REG;
522			w_alu_op = `ALU_COM;
523			w_mem_wr = `DIS;
524			w_w_wr = `EN;
525			w_z_wr = `EN;
526			w_c_wr = `DIS;
527			w_brc_ctl = `BG_NOP;
528			`end //end of COMF_W ;`
529
530			`12'b0010_011X_XXXX:`
531			`//REPLACE ID = COMF_F`
532			`//REPLACE ID = COMF_F`
533			`begin`
534			w_pc_gen_ctl = `PC_NEXT;
535			w_stk_op = `STK_NOP;
536			w_muxa_ctl = `MUXA_IGN;
537			w_muxb_ctl = `MUXB_REG;
538			w_alu_op = `ALU_COM;
539			w_mem_wr = `EN;
540			w_w_wr = `DIS;
541			w_z_wr = `EN;
542			w_c_wr = `DIS;
543			w_brc_ctl = `BG_NOP;
544			`end //end of COMF_F ;`
545
546			`12'b0010_100X_XXXX:`
547			`//REPLACE ID = INCF_W`
548			`//REPLACE ID = INCF_W`
549			`begin`
550			w_pc_gen_ctl = `PC_NEXT;
551			w_stk_op = `STK_NOP;
552			w_muxa_ctl = `MUXA_IGN;
553			w_muxb_ctl = `MUXB_REG;
554			w_alu_op = `ALU_INC;
555			w_mem_wr = `DIS;
556			w_w_wr = `EN;
557			w_z_wr = `EN;
558			w_c_wr = `DIS;
559			w_brc_ctl = `BG_NOP;
560			`end //end of INCF_W ;`
561
562			`12'b0010_101X_XXXX:`
563			`//REPLACE ID = INCF_F`
564			`//REPLACE ID = INCF_F`
565			`begin`
566			w_pc_gen_ctl = `PC_NEXT;
567			w_stk_op = `STK_NOP;
568			w_muxa_ctl = `MUXA_IGN;
569			w_muxb_ctl = `MUXB_REG;
570			w_alu_op = `ALU_INC;
571			w_mem_wr = `EN;
572			w_w_wr = `DIS;
573			w_z_wr = `EN;
574			w_c_wr = `DIS;
575			w_brc_ctl = `BG_NOP;
576			`end //end of INCF_F ;`
577
578			`12'b0010_110X_XXXX:`
579			`//REPLACE ID = DECFSZ_W`
580			`//REPLACE ID = DECFSZ_W`
581			`begin`
582			w_pc_gen_ctl = `PC_NEXT;
583			w_stk_op = `STK_NOP;
584			w_muxa_ctl = `MUXA_IGN;
585			w_muxb_ctl = `MUXB_REG;
586			w_alu_op = `ALU_DEC;
587			w_mem_wr = `DIS;
588			w_w_wr = `EN;
589			w_z_wr = `DIS;
590			w_c_wr = `DIS;
591			w_brc_ctl = `BG_ZERO; //if the result is 0 then the next w_insrction will be discarded
592			`end //end of DECFSZ_W ;`
593
594			`12'b0010_111X_XXXX:`
595			`//REPLACE ID = DECFSZ_F`
596			`//REPLACE ID = DECFSZ_F`
597			`begin`
598			w_pc_gen_ctl = `PC_NEXT;
599			w_stk_op = `STK_NOP;
600			w_muxa_ctl = `MUXA_IGN;
601			w_muxb_ctl = `MUXB_REG;
602			w_alu_op = `ALU_DEC;
603			w_mem_wr = `EN;
604			w_w_wr = `DIS;
605			w_z_wr = `DIS;
606			w_c_wr = `DIS;
607			w_brc_ctl = `BG_ZERO; //if the result is 0 then the next w_insrction will be discarded
608			`end //end of DECFSZ_F ;`
609			`//checked`
610
611			`12'b0011_000X_XXXX:`
612			`//REPLACE ID = RRF_W`
613			`//REPLACE ID = RRF_W`
614			`begin`
615			w_pc_gen_ctl = `PC_NEXT;
616			w_stk_op = `STK_NOP;
617			w_muxa_ctl = `MUXA_IGN;
618			w_muxb_ctl = `MUXB_REG;
619			w_alu_op = `ALU_ROR;
620			w_mem_wr = `DIS;
621			w_w_wr = `EN;
622			w_z_wr = `DIS;
623			w_c_wr = `EN;
624			w_brc_ctl = `BG_NOP;
625			`end //end of RRF_W ;`
626			`//checked`
627
628			`12'b0011_001X_XXXX:`
629			`//REPLACE ID = RRF_F`
630			`//REPLACE ID = RRF_F`
631			`begin`
632			w_pc_gen_ctl = `PC_NEXT;
633			w_stk_op = `STK_NOP;
634			w_muxa_ctl = `MUXA_IGN;
635			w_muxb_ctl = `MUXB_REG;
636			w_alu_op = `ALU_ROR;
637			w_mem_wr = `EN;
638			w_w_wr = `DIS;
639			w_z_wr = `DIS;
640			w_c_wr = `EN;
641			w_brc_ctl = `BG_NOP;
642			`end //end of RRF_F ;`
643
644			`//`
645			`12'b0011_010X_XXXX:`
646			`//REPLACE ID = RLF_W`
647			`//REPLACE ID = RLF_W`
648			`begin`
649			w_pc_gen_ctl = `PC_NEXT;
650			w_stk_op = `STK_NOP;
651			w_muxa_ctl = `MUXA_IGN;
652			w_muxb_ctl = `MUXB_REG;
653			w_alu_op = `ALU_ROL;
654			w_mem_wr = `DIS;
655			w_w_wr = `EN;
656			w_z_wr = `DIS;
657			w_c_wr = `EN;
658			w_brc_ctl = `BG_NOP;
659			`end //end of RLF_W ;`
660
661			`12'b0011_011X_XXXX:`
662			`//REPLACE ID = RLF_F`
663			`//REPLACE ID = RLF_F`
664			`begin`
665			w_pc_gen_ctl = `PC_NEXT;
666			w_stk_op = `STK_NOP;
667			w_muxa_ctl = `MUXA_IGN;
668			w_muxb_ctl = `MUXB_REG;
669			w_alu_op = `ALU_ROL;
670			w_mem_wr = `EN;
671			w_w_wr = `DIS;
672			w_z_wr = `DIS;
673			w_c_wr = `EN;
674			w_brc_ctl = `BG_NOP;
675			`end //end of RLF_F ;`
676
677			`12'b0011_100X_XXXX:`
678			`//REPLACE ID = SWAPF_W`
679			`//REPLACE ID = SWAPF_W`
680			`begin`
681			w_pc_gen_ctl = `PC_NEXT;
682			w_stk_op = `STK_NOP;
683			w_muxa_ctl = `MUXA_IGN;
684			w_muxb_ctl = `MUXB_REG;
685			w_alu_op = `ALU_SWAP;
686			w_mem_wr = `DIS;
687			w_w_wr = `EN;
688			w_z_wr = `DIS;
689			w_c_wr = `DIS;
690			w_brc_ctl = `BG_NOP;
691			`end //end of SWAPF_F ;`
692
693			`12'b0011_101X_XXXX:`
694			`//REPLACE ID = SWAPF_F`
695			`//REPLACE ID = SWAPF_F`
696			`begin`
697			w_pc_gen_ctl = `PC_NEXT;
698			w_stk_op = `STK_NOP;
699			w_muxa_ctl = `MUXA_IGN;
700			w_muxb_ctl = `MUXB_REG;
701			w_alu_op = `ALU_SWAP;
702			w_mem_wr = `EN;
703			w_w_wr = `DIS;
704			w_z_wr = `DIS;
705			w_c_wr = `DIS;
706			w_brc_ctl = `BG_NOP;
707			`end //end of SWAPF_F ;`
708
709			`12'b0011_110X_XXXX:`
710			`//REPLACE ID = INCFSZ_W`
711			`//REPLACE ID = INCFSZ_W`
712			`begin`
713			w_pc_gen_ctl = `PC_NEXT;
714			w_stk_op = `STK_NOP;
715			w_muxa_ctl = `MUXA_W;
716			w_muxb_ctl = `MUXB_REG;
717			w_alu_op = `ALU_INC;
718			w_mem_wr = `DIS;
719			w_w_wr = `EN;
720			w_z_wr = `DIS;
721			w_c_wr = `DIS;
722			w_brc_ctl = `BG_ZERO;
723			`end //end of INCFSZ_W ;`
724
725			`12'b0011_111X_XXXX:`
726			`//REPLACE ID = INCFSZ_F`
727			`//REPLACE ID = INCFSZ_F`
728			`begin`
729			w_pc_gen_ctl = `PC_NEXT;
730			w_stk_op = `STK_NOP;
731			w_muxa_ctl = `MUXA_W;
732			w_muxb_ctl = `MUXB_REG;
733			w_alu_op = `ALU_INC;
734			w_mem_wr = `EN;
735			w_w_wr = `DIS;
736			w_z_wr = `DIS;
737			w_c_wr = `DIS;
738			w_brc_ctl = `BG_ZERO;
739			`end //end of INCFSZ_F ;`
740
741			`12'b0100_XXXX_XXXX:`
742			`//REPLACE ID = BCF`
743			`//REPLACE ID = BCF`
744			`begin`
745			w_pc_gen_ctl = `PC_NEXT;
746			w_stk_op = `STK_NOP;
747			w_muxa_ctl = `MUXA_BD;
748			w_muxb_ctl = `MUXB_REG;
749			w_alu_op = `ALU_BCF;
750			w_mem_wr = `EN;
751			w_w_wr = `DIS;
752			w_z_wr = `DIS;
753			w_c_wr = `DIS;
754			w_brc_ctl = `BG_NOP;
755			`end //end of BCF ;`
756
757			`12'b0101_XXXX_XXXX:`
758			`//REPLACE ID = BSF`
759			`//REPLACE ID = BSF`
760			`begin`
761			w_pc_gen_ctl = `PC_NEXT;
762			w_stk_op = `STK_NOP;
763			w_muxa_ctl = `MUXA_BD;
764			w_muxb_ctl = `MUXB_REG;
765			w_alu_op = `ALU_BSF;
766			w_mem_wr = `EN;
767			w_w_wr = `DIS;
768			w_z_wr = `DIS;
769			w_c_wr = `DIS;
770			w_brc_ctl = `BG_NOP;
771			`end //end of BSF ;`
772			`/**/`
773
774			`12'b0110_XXXX_XXXX:`
775			`//REPLACE ID = BTFSC`
776			`//REPLACE ID = BTFSC`
777			`begin`
778			w_pc_gen_ctl = `PC_NEXT;
779			w_stk_op = `STK_NOP;
780			w_muxa_ctl = `MUXA_BD;
781			w_muxb_ctl = `MUXB_REG;
782			w_alu_op = `ALU_BTFSC;//ALU_BTFSC
783			w_mem_wr = `DIS;
784			w_w_wr = `DIS;
785			w_z_wr = `DIS;
786			w_c_wr = `DIS;
787			w_brc_ctl = `BG_ZERO;
788			`end //end of BTFSC ;`
789
790			`12'b0111_XXXX_XXXX:`
791			`//REPLACE ID = BTFSS`
792			`//REPLACE ID = BTFSS`
793			`begin`
794			w_pc_gen_ctl = `PC_NEXT;
795			w_stk_op = `STK_NOP;
796			w_muxa_ctl = `MUXA_BD;
797			w_muxb_ctl = `MUXB_REG;
798			w_alu_op = `ALU_BTFSS;
799			w_mem_wr = `DIS;
800			w_w_wr = `DIS;
801			w_z_wr = `DIS;
802			w_c_wr = `DIS;
803			w_brc_ctl = `BG_NZERO;
804			`end //end of BTFSS ;`
805
806			`12'b1000_XXXX_XXXX:`
807			`//REPLACE ID = RETLW`
808			`//REPLACE ID = RETLW`
809			`begin`
810			w_pc_gen_ctl = `PC_NEXT;
811			w_stk_op = `STK_POP;
812			w_muxa_ctl = `MUXA_IGN;
813			w_muxb_ctl = `MUXB_EK;
814			w_alu_op = `ALU_PB;
815			w_mem_wr = `DIS;
816			w_w_wr = `EN;
817			w_z_wr = `DIS;
818			w_c_wr = `DIS;
819			w_brc_ctl = `BG_NOP;
820			`end //end of RETLW ;`
821
822			`12'b1001_XXXX_XXXX:`
823			`//REPLACE ID = CALL`
824			`//REPLACE ID = CALL`
825			`begin`
826			w_pc_gen_ctl = `PC_GOTO;
827			w_stk_op = `STK_PSH;
828			w_muxa_ctl = `MUXA_IGN;
829			w_muxb_ctl = `MUXB_IGN;
830			w_alu_op = `ALU_NOP;
831			w_mem_wr = `DIS;
832			w_w_wr = `DIS;
833			w_z_wr = `DIS;
834			w_c_wr = `DIS;
835			w_brc_ctl = `BG_NOP;
836			`end //end of CALL ;`
837
838			`12'b101X_XXXX_XXXX:`
839			`//REPLACE ID = GOTO`
840			`//REPLACE ID = GOTO`
841			`begin`
842			w_pc_gen_ctl = `PC_GOTO;
843			w_stk_op = `STK_NOP;
844			w_muxa_ctl = `MUXA_IGN;
845			w_muxb_ctl = `MUXB_IGN;
846			w_alu_op = `ALU_NOP;
847			w_mem_wr = `DIS;
848			w_w_wr = `DIS;
849			w_z_wr = `DIS;
850			w_c_wr = `DIS;
851			w_brc_ctl = `BG_NOP;
852			`end //end of GOTO ;`
853
854			`12'b1100_XXXX_XXXX:`
855			`//REPLACE ID = MOVLW`
856			`//REPLACE ID = MOVLW`
857			`begin`
858			w_pc_gen_ctl = `PC_NEXT;
859			w_stk_op = `STK_NOP;
860			w_muxa_ctl = `MUXA_IGN;
861			w_muxb_ctl = `MUXB_EK;
862			w_alu_op = `ALU_PB;
863			w_mem_wr = `DIS;
864			w_w_wr = `EN;
865			w_z_wr = `DIS;
866			w_c_wr = `DIS;
867			w_brc_ctl = `BG_NOP;
868			`end //end of MOVLW ;`
869
870			`12'b1101_XXXX_XXXX:`
871			`//REPLACE ID = IORLW`
872			`//REPLACE ID = IORLW`
873			`begin`
874			w_pc_gen_ctl = `PC_NEXT;
875			w_stk_op = `STK_NOP;
876			w_muxa_ctl = `MUXA_W;
877			w_muxb_ctl = `MUXB_EK;
878			w_alu_op = `ALU_OR;
879			w_mem_wr = `DIS;
880			w_w_wr = `EN;
881			w_z_wr = `EN;
882			w_c_wr = `DIS;
883			w_brc_ctl = `BG_NOP;
884			`end //end of IORLW ;`
885
886			`12'b1110_XXXX_XXXX:`
887			`//REPLACE ID = ANDLW`
888			`//REPLACE ID = ANDLW`
889			`begin`
890			w_pc_gen_ctl = `PC_NEXT;
891			w_stk_op = `STK_NOP;
892			w_muxa_ctl = `MUXA_W;
893			w_muxb_ctl = `MUXB_EK;
894			w_alu_op = `ALU_AND;
895			w_mem_wr = `DIS;
896			w_w_wr = `EN;
897			w_z_wr = `EN;
898			w_c_wr = `DIS;
899			w_brc_ctl = `BG_NOP;
900			`end //end of ANDLW ;`
901
902			`12'b1111_XXXX_XXXX:`
903			`//REPLACE ID = XORLW`
904			`//REPLACE ID = XORLW`
905			`begin`
906			w_pc_gen_ctl = `PC_NEXT;
907			w_stk_op = `STK_NOP;
908			w_muxa_ctl = `MUXA_W;
909			w_muxb_ctl = `MUXB_EK;
910			w_alu_op = `ALU_XOR;
911			w_mem_wr = `DIS;
912			w_w_wr = `EN;
913			w_z_wr = `EN;
914			w_c_wr = `DIS;
915			w_brc_ctl = `BG_NOP;
916			`end //end of XORLW ;`
917
918
919			`default:`
920			`//REPLACE ID = NOP`
921			`begin`
922			w_pc_gen_ctl = `PC_NEXT;
923			w_stk_op = `STK_NOP;
924			w_muxa_ctl = `MUXA_IGN;
925			w_muxb_ctl = `MUXB_IGN;
926			w_alu_op = `ALU_NOP;
927			w_mem_wr = `DIS;
928			w_w_wr = `DIS;
929			w_z_wr = `DIS;
930			w_c_wr = `DIS;
931			w_brc_ctl = `BG_NOP;
932			`end //end of NOP ;`
933			`endcase`
934			`end`
935
936			`endmodule`