URL https://opencores.org/ocsvn/lwrisc/lwrisc/trunk

Subversion Repositories lwrisc

[/] [lwrisc/] [trunk/] [RTL/] [test.v] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log


`timescale 10ns / 10ns
 
module test;
 
    reg clk;
    reg  rst;
 
    initial     begin
        #1 clk = 0;
        #10 rst = 0;
        #10 rst = 1;
        #10 rst = 0;
    end
 
    always #1 clk=~clk ;
 
    ClaiRISC_core I_ClaiRISC_core
                    (
                        .clk(clk),
                        .rst(rst)
                    ) ;
 
endmodule

Line No.	Rev	Author	Line
1	7	mcupro	`timescale 10ns / 10ns
2
3			`module test;`
4
5			`reg clk;`
6			`reg rst;`
7
8			`initial begin`
9			`#1 clk = 0;`
10			`#10 rst = 0;`
11			`#10 rst = 1;`
12			`#10 rst = 0;`
13			`end`
14
15			`always #1 clk=~clk ;`
16
17			`ClaiRISC_core I_ClaiRISC_core`
18			`(`
19			`.clk(clk),`
20			`.rst(rst)`
21			`) ;`
22
23			`endmodule`

Browse

Tools

Subversion Repositories lwrisc

[/] [lwrisc/] [trunk/] [RTL/] [test.v] - Blame information for rev 7