Subversion Repositories lwrisc

//

// Written by Synplify

// Synplify 8.1.0, Build 539R.

// Mon Mar 10 17:23:16 2008

//

// Source file index table:

// Object locations will have the form :

// file 0 "noname"

// file 1 "\c:\program files\synplicity\fpga_81\lib\altera\altera.v "

// file 2 "\c:\program files\synplicity\fpga_81\lib\altera\cyclone.v "

// file 3 "\c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v "

// file 4 "\c:\program files\synplicity\fpga_81\lib\altera\altera_lpm.v "

// file 5 "\d:\lwrisc\rtl\sim_rom.v "

// file 6 "\d:\lwrisc\rtl\test.v "

// file 7 "\d:\lwrisc\rtl\mem_man.v "

// file 8 "\d:\lwrisc\rtl\clairisc_def.h "

// file 9 "\d:\lwrisc\rtl\memory.v "

// file 10 "\d:\lwrisc\rtl\rom_set.h "

// file 11 "\d:\lwrisc\rtl\risc_core.v "

// file 12 "\d:\lwrisc\rtl\altera\rom512x12.v "

// file 13 "\d:\lwrisc\rtl\altera\rom1024x12.v "

// file 14 "\d:\lwrisc\rtl\altera\rom2048x12.v "

// file 15 "\d:\lwrisc\rtl\altera\ram128x8.v "

// file 16 "\d:\lwrisc\rtl\altera\rom32x12.v "

// file 17 "\d:\lwrisc\rtl\altera\rom64x12.v "

// file 18 "\d:\lwrisc\rtl\altera\rom128x12.v "

// file 19 "\d:\lwrisc\rtl\altera\rom256x12.v "

// VQM4.1+

module altsyncram_Z1 (

  wren_a,

  data_a,

  address_a,

  address_b,

  clock0,

  q_a,

  q_b

);

input wren_a ;

input [7:0] data_a ;

input [6:0] address_a ;

input [6:0] address_b ;

input clock0 ;

output [7:0] q_a ;

output [7:0] q_b ;

altsyncram U1 (

  .wren_a(wren_a),

  .data_a(data_a),

  .address_a(address_a),

  .address_b(address_b),

  .clock0(clock0),

  .q_a(q_a),

  .q_b(q_b)

 );

defparam U1.intended_device_family =  "Cyclone";

defparam U1.read_during_write_mode_mixed_ports =  "DONT_CARE";

defparam U1.operation_mode =  "DUAL_PORT";

defparam U1.address_aclr_b =  "NONE";

defparam U1.outdata_aclr_b =  "NONE";

defparam U1.outdata_reg_b =  "UNREGISTERED";

defparam U1.address_reg_b =  "CLOCK0";

defparam U1.numwords_b =  128;

defparam U1.widthad_b =  7;

defparam U1.width_b =  8;

defparam U1.width_byteena_a =  1;

defparam U1.wrcontrol_aclr_a =  "NONE";

defparam U1.indata_aclr_a =  "NONE";

defparam U1.address_aclr_a =  "NONE";

defparam U1.numwords_a =  128;

defparam U1.widthad_a =  7;

defparam U1.width_a =  8;

endmodule /* altsyncram_Z1 */

// VQM4.1+

module ram128x8 (

  alt_ram_q_7,

  alt_ram_q_6,

  alt_ram_q_5,

  alt_ram_q_4,

  alt_ram_q_3,

  alt_ram_q_2,

  alt_ram_q_1,

  alt_ram_q_0,

  w_ins_4,

  w_ins_3,

  w_ins_2,

  w_ins_1,

  w_ins_0,

  fsr_1,

  fsr_0,

  w_ek_r_4,

  w_ek_r_3,

  w_ek_r_2,

  w_ek_r_1,

  w_ek_r_0,

  w_alu_res_1_6_2,

  w_alu_res_1_6_1,

  w_alu_res_1_6_0,

  w_alu_res_1_3_0,

  w_alu_res_1_1_0,

  w_alu_res_1_0_2,

  w_alu_res_1_0_1,

  w_alu_res_1_0_0,

  clk_c,

  w_mem_wr_r

);

output alt_ram_q_7 ;

output alt_ram_q_6 ;

output alt_ram_q_5 ;

output alt_ram_q_4 ;

output alt_ram_q_3 ;

output alt_ram_q_2 ;

output alt_ram_q_1 ;

output alt_ram_q_0 ;

input w_ins_4 ;

input w_ins_3 ;

input w_ins_2 ;

input w_ins_1 ;

input w_ins_0 ;

input fsr_1 ;

input fsr_0 ;

input w_ek_r_4 ;

input w_ek_r_3 ;

input w_ek_r_2 ;

input w_ek_r_1 ;

input w_ek_r_0 ;

input w_alu_res_1_6_2 ;

input w_alu_res_1_6_1 ;

input w_alu_res_1_6_0 ;

input w_alu_res_1_3_0 ;

input w_alu_res_1_1_0 ;

input w_alu_res_1_0_2 ;

input w_alu_res_1_0_1 ;

input w_alu_res_1_0_0 ;

input clk_c ;

input w_mem_wr_r ;

wire alt_ram_q_7 ;

wire alt_ram_q_6 ;

wire alt_ram_q_5 ;

wire alt_ram_q_4 ;

wire alt_ram_q_3 ;

wire alt_ram_q_2 ;

wire alt_ram_q_1 ;

wire alt_ram_q_0 ;

wire w_ins_4 ;

wire w_ins_3 ;

wire w_ins_2 ;

wire w_ins_1 ;

wire w_ins_0 ;

wire fsr_1 ;

wire fsr_0 ;

wire w_ek_r_4 ;

wire w_ek_r_3 ;

wire w_ek_r_2 ;

wire w_ek_r_1 ;

wire w_ek_r_0 ;

wire w_alu_res_1_6_2 ;

wire w_alu_res_1_6_1 ;

wire w_alu_res_1_6_0 ;

wire w_alu_res_1_3_0 ;

wire w_alu_res_1_1_0 ;

wire w_alu_res_1_0_2 ;

wire w_alu_res_1_0_1 ;

wire w_alu_res_1_0_0 ;

wire clk_c ;

wire w_mem_wr_r ;

wire [7:0] q_a;

wire NC0 ;

wire NC1 ;

wire NC2 ;

wire NC3 ;

wire NC4 ;

wire NC5 ;

wire NC6 ;

wire NC7 ;

wire NC8 ;

wire NC9 ;

wire NC10 ;

wire NC11 ;

wire NC12 ;

wire NC13 ;

wire NC14 ;

wire NC15 ;

wire NC16 ;

wire NC17 ;

wire NC18 ;

wire GND ;

wire VCC ;

  assign VCC = 1'b1;

  assign GND = 1'b0;

// @15:162

  altsyncram_Z1 altsyncram_component_Z (

        .wren_a(w_mem_wr_r),

        .data_a({w_alu_res_1_6_2, w_alu_res_1_6_1, w_alu_res_1_6_0, w_alu_res_1_3_0,

   w_alu_res_1_1_0, w_alu_res_1_0_2, w_alu_res_1_0_1, w_alu_res_1_0_0}),

        .address_a({fsr_1, fsr_0, w_ek_r_4, w_ek_r_3, w_ek_r_2, w_ek_r_1, w_ek_r_0}),

        .address_b({fsr_1, fsr_0, w_ins_4, w_ins_3, w_ins_2, w_ins_1, w_ins_0}),

        .clock0(clk_c),

        .q_a({q_a[7], q_a[6], q_a[5], q_a[4], q_a[3], q_a[2], q_a[1], q_a[0]}),

        .q_b({alt_ram_q_7, alt_ram_q_6, alt_ram_q_5, alt_ram_q_4, alt_ram_q_3,

   alt_ram_q_2, alt_ram_q_1, alt_ram_q_0})

);

endmodule /* ram128x8 */

// VQM4.1+

module wb_mem_man (

  w_ins_0,

  w_ins_1,

  w_ins_2,

  w_ins_3,

  w_ins_4,

  out0_0,

  out0_1,

  out0_2,

  out0_3,

  out0_4,

  out0_5,

  out0_6,

  out0_7,

  out1_0,

  out1_1,

  out1_2,

  out1_3,

  out1_4,

  out1_5,

  out1_6,

  out1_7,

  w_alu_res_1_1_0,

  w_alu_res_1_3_0,

  w_alu_res_1_6_0,

  w_alu_res_1_6_1,

  w_alu_res_1_6_2,

  in0_c_0,

  in0_c_1,

  in0_c_2,

  in0_c_3,

  in0_c_4,

  in0_c_5,

  in0_c_6,

  in0_c_7,

  w_alu_res_1_0_1,

  w_alu_res_1_0_2,

  w_alu_res_1_0_0,

  w_alu_res_1_0_a2_1_0,

  w_alu_res_1_0_a2_1_1,

  dout_4,

  dout_7,

  dout_5,

  dout_3,

  dout_2,

  dout_6,

  dout_0,

  dout_1,

  w_alu_res_1_0_a2_2_0_0,

  w_alu_res_1_0_a2_2_0_1,

  w_alu_res_1_0_0_0,

  w_alu_res_1_0_a2_0_0,

  w_alu_res_1_0_a2_0_1,

  w_alu_res_1_0_a2_0_2,

  w_alu_res_1_1_a_0,

  w_alu_res_1_1_1_0,

  w_alu_res_1_3_a_0,

  w_alu_res_1_3_1_0,

  w_alu_res_1_6_a_2,

  w_alu_res_1_6_a_0,

  w_alu_res_1_6_a_1,

  w_alu_res_1_6_1_2,

  w_alu_res_1_6_1_0,

  w_alu_res_1_6_1_1,

  in1_c_7,

  in1_c_6,

  in1_c_5,

  in1_c_4,

  in1_c_3,

  in1_c_2,

  in1_c_1,

  in1_c_0,

  w_ek_r_4,

  w_ek_r_3,

  w_ek_r_2,

  w_ek_r_1,

  w_ek_r_0,

  write_out0_0_a3_0_o2,

  rst_c,

  un11_w_alu_res_carry_7,

  w_c_2mem_i_a2_0_0,

  N_796,

  w_c_wr_r,

  w_z_0_a2,

  w_z_wr_r,

  G_287,

  G_279,

  G_271,

  rst_i_i,

  un11_w_alu_res_add7,

  un11_w_alu_res_add3,

  un11_w_alu_res_add4,

  un11_w_alu_res_add5,

  un11_w_alu_res_add6,

  w_c_2mem_i_a3,

  w_mem_wr_r,

  clk_c

);

input w_ins_0 ;

input w_ins_1 ;

input w_ins_2 ;

input w_ins_3 ;

input w_ins_4 ;

output out0_0 ;

output out0_1 ;

output out0_2 ;

output out0_3 ;

output out0_4 ;

output out0_5 ;

output out0_6 ;

output out0_7 ;

output out1_0 ;

output out1_1 ;

output out1_2 ;

output out1_3 ;

output out1_4 ;

output out1_5 ;

output out1_6 ;

output out1_7 ;

input w_alu_res_1_1_0 ;

input w_alu_res_1_3_0 ;

input w_alu_res_1_6_0 ;

input w_alu_res_1_6_1 ;

input w_alu_res_1_6_2 ;

input in0_c_0 ;

input in0_c_1 ;

input in0_c_2 ;

input in0_c_3 ;

input in0_c_4 ;

input in0_c_5 ;

input in0_c_6 ;

input in0_c_7 ;

input w_alu_res_1_0_1 ;

input w_alu_res_1_0_2 ;

output w_alu_res_1_0_0 ;

input w_alu_res_1_0_a2_1_0 ;

input w_alu_res_1_0_a2_1_1 ;

output dout_4 ;

output dout_7 ;

output dout_5 ;

output dout_3 ;

output dout_2 ;

output dout_6 ;

output dout_0 ;

output dout_1 ;

input w_alu_res_1_0_a2_2_0_0 ;

input w_alu_res_1_0_a2_2_0_1 ;

input w_alu_res_1_0_0_0 ;

input w_alu_res_1_0_a2_0_0 ;

input w_alu_res_1_0_a2_0_1 ;

input w_alu_res_1_0_a2_0_2 ;

input w_alu_res_1_1_a_0 ;

input w_alu_res_1_1_1_0 ;

input w_alu_res_1_3_a_0 ;

input w_alu_res_1_3_1_0 ;

input w_alu_res_1_6_a_2 ;

input w_alu_res_1_6_a_0 ;

input w_alu_res_1_6_a_1 ;

input w_alu_res_1_6_1_2 ;

input w_alu_res_1_6_1_0 ;

input w_alu_res_1_6_1_1 ;

input in1_c_7 ;

input in1_c_6 ;

input in1_c_5 ;

input in1_c_4 ;

input in1_c_3 ;

input in1_c_2 ;

input in1_c_1 ;

input in1_c_0 ;

input w_ek_r_4 ;

input w_ek_r_3 ;

input w_ek_r_2 ;

input w_ek_r_1 ;

input w_ek_r_0 ;

output write_out0_0_a3_0_o2 ;

input rst_c ;

input un11_w_alu_res_carry_7 ;

input w_c_2mem_i_a2_0_0 ;

input N_796 ;

input w_c_wr_r ;

input w_z_0_a2 ;

input w_z_wr_r ;

input G_287 ;

input G_279 ;

input G_271 ;

input rst_i_i ;

input un11_w_alu_res_add7 ;

input un11_w_alu_res_add3 ;

input un11_w_alu_res_add4 ;

input un11_w_alu_res_add5 ;

input un11_w_alu_res_add6 ;

input w_c_2mem_i_a3 ;

input w_mem_wr_r ;

input clk_c ;

wire w_ins_0 ;

wire w_ins_1 ;

wire w_ins_2 ;

wire w_ins_3 ;

wire w_ins_4 ;

wire out0_0 ;

wire out0_1 ;

wire out0_2 ;

wire out0_3 ;

wire out0_4 ;

wire out0_5 ;

wire out0_6 ;

wire out0_7 ;

wire out1_0 ;

wire out1_1 ;

wire out1_2 ;

wire out1_3 ;

wire out1_4 ;

wire out1_5 ;

wire out1_6 ;

wire out1_7 ;

wire w_alu_res_1_1_0 ;

wire w_alu_res_1_3_0 ;

wire w_alu_res_1_6_0 ;

wire w_alu_res_1_6_1 ;

wire w_alu_res_1_6_2 ;

wire in0_c_0 ;

wire in0_c_1 ;

wire in0_c_2 ;

wire in0_c_3 ;

wire in0_c_4 ;

wire in0_c_5 ;

wire in0_c_6 ;

wire in0_c_7 ;

wire w_alu_res_1_0_1 ;

wire w_alu_res_1_0_2 ;

wire w_alu_res_1_0_0 ;

wire w_alu_res_1_0_a2_1_0 ;

wire w_alu_res_1_0_a2_1_1 ;

wire dout_4 ;

wire dout_7 ;

wire dout_5 ;

wire dout_3 ;

wire dout_2 ;

wire dout_6 ;

wire dout_0 ;

wire dout_1 ;

wire w_alu_res_1_0_a2_2_0_0 ;

wire w_alu_res_1_0_a2_2_0_1 ;

wire w_alu_res_1_0_0_0 ;

wire w_alu_res_1_0_a2_0_0 ;

wire w_alu_res_1_0_a2_0_1 ;

wire w_alu_res_1_0_a2_0_2 ;

wire w_alu_res_1_1_a_0 ;

wire w_alu_res_1_1_1_0 ;

wire w_alu_res_1_3_a_0 ;

wire w_alu_res_1_3_1_0 ;

wire w_alu_res_1_6_a_2 ;

wire w_alu_res_1_6_a_0 ;

wire w_alu_res_1_6_a_1 ;

wire w_alu_res_1_6_1_2 ;

wire w_alu_res_1_6_1_0 ;

wire w_alu_res_1_6_1_1 ;

wire in1_c_7 ;

wire in1_c_6 ;

wire in1_c_5 ;

wire in1_c_4 ;

wire in1_c_3 ;

wire in1_c_2 ;

wire in1_c_1 ;

wire in1_c_0 ;

wire w_ek_r_4 ;

wire w_ek_r_3 ;

wire w_ek_r_2 ;

wire w_ek_r_1 ;

wire w_ek_r_0 ;

wire write_out0_0_a3_0_o2 ;

wire rst_c ;

wire un11_w_alu_res_carry_7 ;

wire w_c_2mem_i_a2_0_0 ;

wire N_796 ;

wire w_c_wr_r ;

wire w_z_0_a2 ;

wire w_z_wr_r ;

wire G_287 ;

wire G_279 ;

wire G_271 ;

wire rst_i_i ;

wire un11_w_alu_res_add7 ;

wire un11_w_alu_res_add3 ;

wire un11_w_alu_res_add4 ;

wire un11_w_alu_res_add5 ;

wire un11_w_alu_res_add6 ;

wire w_c_2mem_i_a3 ;

wire w_mem_wr_r ;

wire clk_c ;

wire [4:0] wr_addr_r;

wire [7:0] dout_1_Z;

wire [7:0] reg_in0;

wire [6:0] din_r;

wire [7:0] status;

wire [6:6] status_0_0_0_a2_1;

wire [6:6] status_0_0_0_a2_2;

wire [2:2] status_0_i_0_a;

wire [0:0] status_6;

wire [7:0] fsr;

wire [0:0] status_6_a;

wire [7:0] alt_ram_q;

wire [6:0] dout_a;

wire [7:0] dout_3_Z;

wire [7:0] dout_3_a;

wire ram_q_a ;

wire VCC ;

wire dout10 ;

wire ram_q ;

wire un1_ram_q_NE_2 ;

wire un1_ram_q_NE_2_a ;

wire dout_sn_m5_e_0_a2 ;

wire dout_sn_m5_e_0_a2_a ;

wire dout10_2 ;

wire dout8 ;

wire dout_sn_m6_0_a2 ;

wire dout7_1 ;

wire N_64 ;

wire N_63 ;

wire GND ;

wire rst_i_i_i ;

//@1:1

  assign VCC = 1'b1;

  assign GND = 1'b0;

// @7:36

  cyclone_lcell wr_en_r_Z (

        .combout(ram_q_a),

        .clk(clk_c),

        .dataa(wr_addr_r[0]),

        .datab(w_ek_r_0),

        .datac(w_mem_wr_r),

        .datad(VCC),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam wr_en_r_Z.operation_mode="normal";

defparam wr_en_r_Z.output_mode="comb_only";

defparam wr_en_r_Z.lut_mask="6f6f";

defparam wr_en_r_Z.synch_mode="on";

defparam wr_en_r_Z.sum_lutc_input="qfbk";

// @7:109

  cyclone_lcell reg_in1_0__Z (

        .combout(dout_1_Z[0]),

        .clk(clk_c),

        .dataa(reg_in0[0]),

        .datab(dout10),

        .datac(in1_c_0),

        .datad(VCC),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam reg_in1_0__Z.operation_mode="normal";

defparam reg_in1_0__Z.output_mode="comb_only";

defparam reg_in1_0__Z.lut_mask="e2e2";

defparam reg_in1_0__Z.synch_mode="on";

defparam reg_in1_0__Z.sum_lutc_input="qfbk";

// @7:109

  cyclone_lcell reg_in1_1__Z (

        .combout(dout_1_Z[1]),

        .clk(clk_c),

        .dataa(reg_in0[1]),

        .datab(dout10),

        .datac(in1_c_1),

        .datad(VCC),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam reg_in1_1__Z.operation_mode="normal";

defparam reg_in1_1__Z.output_mode="comb_only";

defparam reg_in1_1__Z.lut_mask="e2e2";

defparam reg_in1_1__Z.synch_mode="on";

defparam reg_in1_1__Z.sum_lutc_input="qfbk";

// @7:109

  cyclone_lcell reg_in1_2__Z (

        .combout(dout_1_Z[2]),

        .clk(clk_c),

        .dataa(reg_in0[2]),

        .datab(dout10),

        .datac(in1_c_2),

        .datad(VCC),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam reg_in1_2__Z.operation_mode="normal";

defparam reg_in1_2__Z.output_mode="comb_only";

defparam reg_in1_2__Z.lut_mask="e2e2";

defparam reg_in1_2__Z.synch_mode="on";

defparam reg_in1_2__Z.sum_lutc_input="qfbk";

// @7:109

  cyclone_lcell reg_in1_3__Z (

        .combout(dout_1_Z[3]),

        .clk(clk_c),

        .dataa(reg_in0[3]),

        .datab(dout10),

        .datac(in1_c_3),

        .datad(VCC),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam reg_in1_3__Z.operation_mode="normal";

defparam reg_in1_3__Z.output_mode="comb_only";

defparam reg_in1_3__Z.lut_mask="e2e2";

defparam reg_in1_3__Z.synch_mode="on";

defparam reg_in1_3__Z.sum_lutc_input="qfbk";

// @7:109

  cyclone_lcell reg_in1_4__Z (

        .combout(dout_1_Z[4]),

        .clk(clk_c),

        .dataa(reg_in0[4]),

        .datab(dout10),

        .datac(in1_c_4),

        .datad(VCC),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam reg_in1_4__Z.operation_mode="normal";

defparam reg_in1_4__Z.output_mode="comb_only";

defparam reg_in1_4__Z.lut_mask="e2e2";

defparam reg_in1_4__Z.synch_mode="on";

defparam reg_in1_4__Z.sum_lutc_input="qfbk";

// @7:109

  cyclone_lcell reg_in1_5__Z (

        .combout(dout_1_Z[5]),

        .clk(clk_c),

        .dataa(reg_in0[5]),

        .datab(dout10),

        .datac(in1_c_5),

        .datad(VCC),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam reg_in1_5__Z.operation_mode="normal";

defparam reg_in1_5__Z.output_mode="comb_only";

defparam reg_in1_5__Z.lut_mask="e2e2";

defparam reg_in1_5__Z.synch_mode="on";

defparam reg_in1_5__Z.sum_lutc_input="qfbk";

// @7:109

  cyclone_lcell reg_in1_6__Z (

        .combout(dout_1_Z[6]),

        .clk(clk_c),

        .dataa(reg_in0[6]),

        .datab(dout10),

        .datac(in1_c_6),

        .datad(VCC),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam reg_in1_6__Z.operation_mode="normal";

defparam reg_in1_6__Z.output_mode="comb_only";

defparam reg_in1_6__Z.lut_mask="e2e2";

defparam reg_in1_6__Z.synch_mode="on";

defparam reg_in1_6__Z.sum_lutc_input="qfbk";

// @7:109

  cyclone_lcell reg_in1_7__Z (

        .combout(dout_1_Z[7]),

        .clk(clk_c),

        .dataa(reg_in0[7]),

        .datab(dout10),

        .datac(in1_c_7),

        .datad(VCC),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam reg_in1_7__Z.operation_mode="normal";

defparam reg_in1_7__Z.output_mode="comb_only";

defparam reg_in1_7__Z.lut_mask="e2e2";

defparam reg_in1_7__Z.synch_mode="on";

defparam reg_in1_7__Z.sum_lutc_input="qfbk";

// @7:36

  cyclone_lcell wr_addr_r_1__Z (

        .combout(ram_q),

        .clk(clk_c),

        .dataa(w_ek_r_1),

        .datab(ram_q_a),

        .datac(w_ek_r_1),

        .datad(un1_ram_q_NE_2),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam wr_addr_r_1__Z.operation_mode="normal";

defparam wr_addr_r_1__Z.output_mode="comb_only";

defparam wr_addr_r_1__Z.lut_mask="0021";

defparam wr_addr_r_1__Z.synch_mode="on";

defparam wr_addr_r_1__Z.sum_lutc_input="qfbk";

// @7:36

  cyclone_lcell wr_addr_r_2__Z (

        .combout(un1_ram_q_NE_2),

        .clk(clk_c),

        .dataa(w_ek_r_2),

        .datab(un1_ram_q_NE_2_a),

        .datac(w_ek_r_2),

        .datad(VCC),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam wr_addr_r_2__Z.operation_mode="normal";

defparam wr_addr_r_2__Z.output_mode="comb_only";

defparam wr_addr_r_2__Z.lut_mask="dede";

defparam wr_addr_r_2__Z.synch_mode="on";

defparam wr_addr_r_2__Z.sum_lutc_input="qfbk";

// @7:36

  cyclone_lcell wr_addr_r_3__Z (

        .combout(un1_ram_q_NE_2_a),

        .clk(clk_c),

        .dataa(wr_addr_r[4]),

        .datab(w_ek_r_3),

        .datac(w_ek_r_3),

        .datad(w_ek_r_4),

        .aclr(GND),

        .sclr(GND),

        .sload(VCC),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam wr_addr_r_3__Z.operation_mode="normal";

defparam wr_addr_r_3__Z.output_mode="comb_only";

defparam wr_addr_r_3__Z.lut_mask="7dbe";

defparam wr_addr_r_3__Z.synch_mode="on";

defparam wr_addr_r_3__Z.sum_lutc_input="qfbk";

// @7:36

  cyclone_lcell din_r_6__Z (

        .regout(din_r[6]),

        .clk(clk_c),

        .dataa(w_c_2mem_i_a3),

        .datab(un11_w_alu_res_add6),

        .datac(w_alu_res_1_6_1_1),

        .datad(w_alu_res_1_6_a_1),

        .aclr(GND),

        .sclr(GND),

        .sload(GND),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam din_r_6__Z.operation_mode="normal";

defparam din_r_6__Z.output_mode="reg_only";

defparam din_r_6__Z.lut_mask="f8ff";

defparam din_r_6__Z.synch_mode="off";

defparam din_r_6__Z.sum_lutc_input="datac";

// @7:36

  cyclone_lcell din_r_5__Z (

        .regout(din_r[5]),

        .clk(clk_c),

        .dataa(w_c_2mem_i_a3),

        .datab(un11_w_alu_res_add5),

        .datac(w_alu_res_1_6_1_0),

        .datad(w_alu_res_1_6_a_0),

        .aclr(GND),

        .sclr(GND),

        .sload(GND),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam din_r_5__Z.operation_mode="normal";

defparam din_r_5__Z.output_mode="reg_only";

defparam din_r_5__Z.lut_mask="f8ff";

defparam din_r_5__Z.synch_mode="off";

defparam din_r_5__Z.sum_lutc_input="datac";

// @7:36

  cyclone_lcell din_r_4__Z (

        .regout(din_r[4]),

        .clk(clk_c),

        .dataa(w_c_2mem_i_a3),

        .datab(un11_w_alu_res_add4),

        .datac(w_alu_res_1_3_1_0),

        .datad(w_alu_res_1_3_a_0),

        .aclr(GND),

        .sclr(GND),

        .sload(GND),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam din_r_4__Z.operation_mode="normal";

defparam din_r_4__Z.output_mode="reg_only";

defparam din_r_4__Z.lut_mask="f8ff";

defparam din_r_4__Z.synch_mode="off";

defparam din_r_4__Z.sum_lutc_input="datac";

// @7:36

  cyclone_lcell din_r_3__Z (

        .regout(din_r[3]),

        .clk(clk_c),

        .dataa(w_c_2mem_i_a3),

        .datab(un11_w_alu_res_add3),

        .datac(w_alu_res_1_1_1_0),

        .datad(w_alu_res_1_1_a_0),

        .aclr(GND),

        .sclr(GND),

        .sload(GND),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam din_r_3__Z.operation_mode="normal";

defparam din_r_3__Z.output_mode="reg_only";

defparam din_r_3__Z.lut_mask="f8ff";

defparam din_r_3__Z.synch_mode="off";

defparam din_r_3__Z.sum_lutc_input="datac";

// @7:36

  cyclone_lcell din_r_2__Z (

        .regout(din_r[2]),

        .clk(clk_c),

        .dataa(VCC),

        .datab(VCC),

        .datac(w_alu_res_1_0_a2_0_2),

        .datad(w_alu_res_1_0_0_0),

        .aclr(GND),

        .sclr(GND),

        .sload(GND),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam din_r_2__Z.operation_mode="normal";

defparam din_r_2__Z.output_mode="reg_only";

defparam din_r_2__Z.lut_mask="fff0";

defparam din_r_2__Z.synch_mode="off";

defparam din_r_2__Z.sum_lutc_input="datac";

// @7:36

  cyclone_lcell din_r_1__Z (

        .regout(din_r[1]),

        .clk(clk_c),

        .dataa(w_alu_res_1_0_a2_2_0_1),

        .datab(dout_1),

        .datac(w_alu_res_1_0_a2_1_1),

        .datad(w_alu_res_1_0_a2_0_1),

        .aclr(GND),

        .sclr(GND),

        .sload(GND),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam din_r_1__Z.operation_mode="normal";

defparam din_r_1__Z.output_mode="reg_only";

defparam din_r_1__Z.lut_mask="fff8";

defparam din_r_1__Z.synch_mode="off";

defparam din_r_1__Z.sum_lutc_input="datac";

// @7:36

  cyclone_lcell din_r_0__Z (

        .combout(w_alu_res_1_0_0),

        .regout(din_r[0]),

        .clk(clk_c),

        .dataa(w_alu_res_1_0_a2_2_0_0),

        .datab(dout_0),

        .datac(w_alu_res_1_0_a2_0_0),

        .datad(w_alu_res_1_0_a2_1_0),

        .aclr(GND),

        .sclr(GND),

        .sload(GND),

        .ena(VCC),

        .inverta(GND),

        .aload(GND),

        .regcascin(GND)

);

defparam din_r_0__Z.operation_mode="normal";

defparam din_r_0__Z.output_mode="reg_and_comb";

defparam din_r_0__Z.lut_mask="fff8";

defparam din_r_0__Z.synch_mode="off";

defparam din_r_0__Z.sum_lutc_input="datac";

// @7:36

  cyclone_lcell wr_addr_r_4__Z (

        .regout(wr_addr_r[4]),

        .clk(clk_c),

        .dataa(VCC),

        .datab(VCC),

        .datac(VCC),

        .datad(w_ek_r_4),

        .aclr(GND),

        .sclr(GND),