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mcupro |
#
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# Synplicity Verification Interface File
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# Generated using Synplify-pro
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#
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# Copyright (c) 1996-2005 Synplicity, Inc.
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# All rights reserved
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#
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# Set logfile options
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vif_set_result_file ClaiRISC_core.vlf
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# Set technology for TCL script
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vif_set_technology -architecture FPGA -vendor Altera
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# RTL and technology files
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vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
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vif_add_file -original -verilog ../../RTL/sim_rom.v
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vif_add_file -original -verilog ../../RTL/test.v
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vif_add_file -original -verilog ../../RTL/mem_man.v
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vif_add_file -original -verilog ../../RTL/memory.v
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vif_add_file -original -verilog ../../RTL/risc_core.v
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vif_add_file -original -verilog ../../RTL/altera/rom512x12.v
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vif_add_file -original -verilog ../../RTL/altera/rom1024x12.v
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vif_add_file -original -verilog ../../RTL/altera/rom2048x12.v
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vif_add_file -original -verilog ../../RTL/altera/ram128x8.v
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vif_add_file -original -verilog ../../RTL/altera/rom32x12.v
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vif_add_file -original -verilog ../../RTL/altera/rom64x12.v
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vif_add_file -original -verilog ../../RTL/altera/rom128x12.v
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vif_add_file -original -verilog ../../RTL/altera/rom256x12.v
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vif_set_top_module -original -top ClaiRISC_core
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vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
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vif_add_file -translated -verilog ClaiRISC_core.vqm
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vif_set_top_module -translated -top ClaiRISC_core
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# Read FSM encoding
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# Memory map points
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# SRL map points
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# Compiler constant registers
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# Compiler constant latches
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# Compiler RTL sequential redundancies
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# RTL sequential redundancies
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vif_set_merge -original w_c_wr_r w_alu_op_r[1]
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vif_set_merge -original w_alu_op_r[3] w_alu_op_r[2]
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vif_set_merge -original w_ek_r[0] mem_man/rd_addr_r[0]
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vif_set_merge -original w_ek_r[0] w_wbadd_r[0]
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vif_set_merge -original w_ek_r[1] mem_man/rd_addr_r[1]
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vif_set_merge -original w_ek_r[1] w_wbadd_r[1]
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vif_set_merge -original w_ek_r[2] mem_man/rd_addr_r[2]
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vif_set_merge -original w_ek_r[2] w_wbadd_r[2]
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vif_set_merge -original w_ek_r[3] mem_man/rd_addr_r[3]
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vif_set_merge -original w_ek_r[3] w_wbadd_r[3]
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vif_set_merge -original w_ek_r[4] mem_man/rd_addr_r[4]
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vif_set_merge -original w_ek_r[4] w_wbadd_r[4]
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# Technology sequential redundancies
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# Inversion map points
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# Port mappping and directions
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# Black box mapping
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vif_set_black_box altsyncram
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vif_set_map_point -blackbox -original mem_man/i_reg_file/altsyncram_component -translated mem_man/i_reg_file/altsyncram_component
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vif_set_map_point -blackbox -original program_rom/i_alt_ram/altsyncram_component -translated program_rom/i_alt_ram/altsyncram_component
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# Other sequential cells, including multidimensional arrays
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# Constant Registers
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vif_set_constant -original -1 mem_man/wr_addr_r[6]
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vif_set_constant -original -1 mem_man/rd_addr_r[6]
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vif_set_constant -original -1 mem_man/wr_addr_r[5]
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vif_set_constant -original -1 mem_man/rd_addr_r[5]
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vif_set_constant -original 1 w_reg_muxb_r
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# Retimed Registers
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vif_set_sequential_verify -retimed -register -original mem_man/status[0] -translated mem_man/status_0__Z
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vif_set_sequential_verify -retimed -register -original mem_man/status[1] -translated mem_man/status_1__Z
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vif_set_sequential_verify -retimed -register -original mem_man/status[2] -translated mem_man/status_2__Z
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vif_set_sequential_verify -retimed -register -original mem_man/status[3] -translated mem_man/status_3__Z
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vif_set_sequential_verify -retimed -register -original mem_man/status[4] -translated mem_man/status_4__Z
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vif_set_sequential_verify -retimed -register -original mem_man/status[5] -translated mem_man/status_5__Z
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vif_set_sequential_verify -retimed -register -original mem_man/status[6] -translated mem_man/status_6__Z
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vif_set_sequential_verify -retimed -register -original mem_man/status[7] -translated mem_man/status_7__Z
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[0] -translated mem_man/reg_in0_0__Z
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[1] -translated mem_man/reg_in0_1__Z
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[2] -translated mem_man/reg_in0_2__Z
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[3] -translated mem_man/reg_in0_3__Z
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[4] -translated mem_man/reg_in0_4__Z
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[5] -translated mem_man/reg_in0_5__Z
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[6] -translated mem_man/reg_in0_6__Z
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[7] -translated mem_man/reg_in0_7__Z
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vif_set_sequential_verify -retimed -register -original mem_man/wr_addr_r[0] -translated mem_man/wr_addr_r_0__Z
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vif_set_sequential_verify -retimed -register -original mem_man/wr_addr_r[4] -translated mem_man/wr_addr_r_4__Z
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vif_set_sequential_verify -retimed -register -original mem_man/din_r[0] -translated mem_man/din_r_0__Z
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| 102 |
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vif_set_sequential_verify -retimed -register -original mem_man/din_r[1] -translated mem_man/din_r_1__Z
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| 103 |
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vif_set_sequential_verify -retimed -register -original mem_man/din_r[2] -translated mem_man/din_r_2__Z
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| 104 |
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vif_set_sequential_verify -retimed -register -original mem_man/din_r[3] -translated mem_man/din_r_3__Z
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| 105 |
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vif_set_sequential_verify -retimed -register -original mem_man/din_r[4] -translated mem_man/din_r_4__Z
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| 106 |
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vif_set_sequential_verify -retimed -register -original mem_man/din_r[5] -translated mem_man/din_r_5__Z
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| 107 |
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vif_set_sequential_verify -retimed -register -original mem_man/din_r[6] -translated mem_man/din_r_6__Z
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| 108 |
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vif_set_sequential_verify -retimed -register -original mem_man/wr_addr_r[3] -translated mem_man/wr_addr_r_3__Z
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| 109 |
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vif_set_sequential_verify -retimed -register -original mem_man/wr_addr_r[2] -translated mem_man/wr_addr_r_2__Z
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| 110 |
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vif_set_sequential_verify -retimed -register -original mem_man/wr_addr_r[1] -translated mem_man/wr_addr_r_1__Z
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| 111 |
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[7] -translated mem_man/reg_in1_7__Z
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| 112 |
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[6] -translated mem_man/reg_in1_6__Z
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| 113 |
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[5] -translated mem_man/reg_in1_5__Z
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| 114 |
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[4] -translated mem_man/reg_in1_4__Z
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| 115 |
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[3] -translated mem_man/reg_in1_3__Z
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| 116 |
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[2] -translated mem_man/reg_in1_2__Z
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| 117 |
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[1] -translated mem_man/reg_in1_1__Z
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| 118 |
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vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[0] -translated mem_man/reg_in1_0__Z
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| 119 |
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vif_set_sequential_verify -retimed -register -original mem_man/wr_en_r -translated mem_man/wr_en_r_Z
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vif_set_sequential_verify -retimed -register -original w_w_wr_r -translated w_w_wr_r_Z
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vif_set_sequential_verify -retimed -register -original w_c_wr_r -translated w_c_wr_r_Z
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vif_set_sequential_verify -retimed -register -original w_mem_wr_r -translated w_mem_wr_r_Z
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vif_set_sequential_verify -retimed -register -original w_z_wr_r -translated w_z_wr_r_Z
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vif_set_sequential_verify -retimed -register -original w_alu_op_r[0] -translated w_alu_op_r_0__Z
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vif_set_sequential_verify -retimed -register -original w_alu_op_r[3] -translated w_alu_op_r_3__Z
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| 126 |
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vif_set_sequential_verify -retimed -register -original w_alu_op_r[4] -translated w_alu_op_r_4__Z
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| 127 |
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vif_set_sequential_verify -retimed -register -original w_wreg[0] -translated w_wreg_0__Z
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| 128 |
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vif_set_sequential_verify -retimed -register -original w_wreg[1] -translated w_wreg_1__Z
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| 129 |
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vif_set_sequential_verify -retimed -register -original w_wreg[2] -translated w_wreg_2__Z
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| 130 |
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vif_set_sequential_verify -retimed -register -original w_wreg[3] -translated w_wreg_3__Z
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| 131 |
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vif_set_sequential_verify -retimed -register -original w_wreg[4] -translated w_wreg_4__Z
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| 132 |
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vif_set_sequential_verify -retimed -register -original w_wreg[5] -translated w_wreg_5__Z
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| 133 |
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vif_set_sequential_verify -retimed -register -original w_wreg[6] -translated w_wreg_6__Z
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| 134 |
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vif_set_sequential_verify -retimed -register -original w_wreg[7] -translated w_wreg_7__Z
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| 135 |
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vif_set_sequential_verify -retimed -register -original w_ek_r[0] -translated w_ek_r_0__Z
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| 136 |
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vif_set_sequential_verify -retimed -register -original w_ek_r[1] -translated w_ek_r_1__Z
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| 137 |
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vif_set_sequential_verify -retimed -register -original w_ek_r[2] -translated w_ek_r_2__Z
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| 138 |
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vif_set_sequential_verify -retimed -register -original w_ek_r[3] -translated w_ek_r_3__Z
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| 139 |
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vif_set_sequential_verify -retimed -register -original w_ek_r[4] -translated w_ek_r_4__Z
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| 140 |
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vif_set_sequential_verify -retimed -register -original w_pc[0] -translated w_pc_0__Z
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| 141 |
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vif_set_sequential_verify -retimed -register -original w_pc[1] -translated w_pc_1__Z
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| 142 |
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vif_set_sequential_verify -retimed -register -original w_pc[2] -translated w_pc_2__Z
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| 143 |
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vif_set_sequential_verify -retimed -register -original w_pc[3] -translated w_pc_3__Z
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| 144 |
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vif_set_sequential_verify -retimed -register -original w_pc[4] -translated w_pc_4__Z
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| 145 |
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vif_set_sequential_verify -retimed -register -original w_pc[5] -translated w_pc_5__Z
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| 146 |
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vif_set_sequential_verify -retimed -register -original w_pc[6] -translated w_pc_6__Z
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| 147 |
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# Altera MAC annotations
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