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[/] [lwrisc/] [trunk/] [SYN/] [rev_1/] [verif/] [ClaiRISC_core_bb.v] - Blame information for rev 19

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1 9 mcupro 
module altsyncram_Z1 (wren_a,wren_b,rden_b,data_a,data_b,address_a,address_b,clock0,clock1,clocken0,clocken1,aclr0,aclr1,byteena_a,byteena_b,addressstall_a,addressstall_b,q_a,q_b);
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input wren_a;
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input wren_b;
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input rden_b;
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input [7:0]data_a;
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input [7:0]data_b;
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input [6:0]address_a;
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input [6:0]address_b;
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input clock0;
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input clock1;
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input clocken0;
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input clocken1;
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input aclr0;
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input aclr1;
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input [0:0]byteena_a;
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input [0:0]byteena_b;
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input addressstall_a;
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input addressstall_b;
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output [7:0]q_a;
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output [7:0]q_b;
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endmodule
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module altsyncram_Z2 (wren_a,wren_b,rden_b,data_a,data_b,address_a,address_b,clock0,clock1,clocken0,clocken1,aclr0,aclr1,byteena_a,byteena_b,addressstall_a,addressstall_b,q_a,q_b);
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input wren_a;
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input wren_b;
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input rden_b;
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input [7:0]data_a;
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input [0:0]data_b;
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input [6:0]address_a;
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input [0:0]address_b;
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input clock0;
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input clock1;
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input clocken0;
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input clocken1;
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input aclr0;
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input aclr1;
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input [0:0]byteena_a;
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input [0:0]byteena_b;
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input addressstall_a;
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input addressstall_b;
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output [7:0]q_a;
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output [0:0]q_b;
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endmodule
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