LXP32 is a small and FPGA friendly 32-bit CPU IP core based on a simple, original instruction set. Its key features include:
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* portability (described in behavioral VHDL, not tied to any particular vendor);
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* 3-stage hazard-free pipeline;
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* 256 registers implemented as a RAM block;
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* only 30 distinct opcodes;
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* separate instruction and data buses, optional instruction cache;
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* WISHBONE compatibility;
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* 8 interrupts with hardwired priorities;
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* optional divider.
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The LXP32 processor was successfully used in commercial projects, is [well documented](https://github.com/lxp32/lxp32-cpu/raw/develop/doc/lxp32-trm.pdf) and comes with a verification environment.
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LXP32 lacks some features of more advanced processors, such as nested interrupt handling, debugging support, floating-point and memory management units. LXP32 ISA (Instruction Set Architecture) does not currently have a C compiler, only assembly based workflow is supported.
