OpenCores
URL https://opencores.org/ocsvn/lxp32/lxp32/trunk

Subversion Repositories lxp32

[/] [lxp32/] [trunk/] [rtl/] [lxp32_interrupt_mux.vhd] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 ring0_mipt
---------------------------------------------------------------------
2
-- Interrupt multiplexer
3
--
4
-- Part of the LXP32 CPU
5
--
6
-- Copyright (c) 2016 by Alex I. Kuznetsov
7
--
8
-- Manages LXP32 interrupts. Interrupts with lower numbers have
9
-- higher priority.
10
---------------------------------------------------------------------
11
 
12
library ieee;
13
use ieee.std_logic_1164.all;
14
use ieee.numeric_std.all;
15
 
16
entity lxp32_interrupt_mux is
17
        port(
18
                clk_i: in std_logic;
19
                rst_i: in std_logic;
20
 
21
                irq_i: in std_logic_vector(7 downto 0);
22
 
23
                interrupts_enabled_i: in std_logic_vector(7 downto 0);
24
                interrupts_blocked_i: in std_logic_vector(7 downto 0);
25
 
26
                interrupt_valid_o: out std_logic;
27
                interrupt_vector_o: out std_logic_vector(2 downto 0);
28
                interrupt_ready_i: in std_logic;
29
                interrupt_return_i: in std_logic
30
        );
31
end entity;
32
 
33
architecture rtl of lxp32_interrupt_mux is
34
 
35
signal irq_reg: std_logic_vector(irq_i'range):=(others=>'0');
36
 
37
type state_type is (Ready,Requested,WaitForExit);
38
signal state: state_type:=Ready;
39
 
40
signal pending_interrupts: std_logic_vector(irq_i'range):=(others=>'0');
41
 
42
signal interrupt_valid: std_logic:='0';
43
 
44
begin
45
 
46
-- Note: "disabled" interrupts (i.e. for which interrupts_enabled_i(i)='0')
47
-- are ignored completely, meaning that the interrupt handler won't be
48
-- called even if the interrupt is enabled later. Conversely, "blocked"
49
-- interrupts are registered, but their handlers are not called until they
50
-- are unblocked.
51
 
52
process (clk_i) is
53
begin
54
        if rising_edge(clk_i) then
55
                if rst_i='1' then
56
                        irq_reg<=(others=>'0');
57
                        pending_interrupts<=(others=>'0');
58
                        state<=Ready;
59
                        interrupt_valid<='0';
60
                else
61
                        irq_reg<=irq_i;
62
 
63
                        pending_interrupts<=(pending_interrupts or
64
                                (irq_i and not irq_reg)) and
65
                                interrupts_enabled_i;
66
 
67
                        case state is
68
                        when Ready =>
69
                                for i in pending_interrupts'reverse_range loop -- lower interrupts have priority
70
                                        if pending_interrupts(i)='1' and interrupts_blocked_i(i)='0' then
71
                                                pending_interrupts(i)<='0';
72
                                                interrupt_valid<='1';
73
                                                interrupt_vector_o<=std_logic_vector(to_unsigned(i,3));
74
                                                state<=Requested;
75
                                                exit;
76
                                        end if;
77
                                end loop;
78
                        when Requested =>
79
                                if interrupt_ready_i='1' then
80
                                        interrupt_valid<='0';
81
                                        state<=WaitForExit;
82
                                end if;
83
                        when WaitForExit =>
84
                                if interrupt_return_i='1' then
85
                                        state<=Ready;
86
                                end if;
87
                        end case;
88
                end if;
89
        end if;
90
end process;
91
 
92
interrupt_valid_o<=interrupt_valid;
93
 
94
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.