OpenCores
URL https://opencores.org/ocsvn/lxp32/lxp32/trunk

Subversion Repositories lxp32

[/] [lxp32/] [trunk/] [rtl/] [lxp32_mul_seq.vhd] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 ring0_mipt
---------------------------------------------------------------------
2
-- Sequential multiplier
3
--
4
-- Part of the LXP32 CPU
5
--
6
-- Copyright (c) 2016 by Alex I. Kuznetsov
7
--
8
-- The smallest possible multiplier. Implemented using
9
-- an accumulator. One multiplication takes 34 cycles.
10
---------------------------------------------------------------------
11
 
12
library ieee;
13
use ieee.std_logic_1164.all;
14
use ieee.numeric_std.all;
15
 
16
entity lxp32_mul_seq is
17
        port(
18
                clk_i: in std_logic;
19
                rst_i: in std_logic;
20
                ce_i: in std_logic;
21
                op1_i: in std_logic_vector(31 downto 0);
22
                op2_i: in std_logic_vector(31 downto 0);
23
                ce_o: out std_logic;
24
                result_o: out std_logic_vector(31 downto 0)
25
        );
26
end entity;
27
 
28
architecture rtl of lxp32_mul_seq is
29
 
30
signal reg1: unsigned(op1_i'range);
31
signal reg2: unsigned(op2_i'range);
32
signal pp: unsigned(31 downto 0);
33
signal acc_sum: unsigned(31 downto 0);
34
signal cnt: integer range 0 to 32:=0;
35
signal ceo: std_logic:='0';
36
 
37
begin
38
 
39
pp<=reg1 when reg2(0)='1' else (others=>'0');
40
 
41
process (clk_i) is
42
begin
43
        if rising_edge(clk_i) then
44
                if rst_i='1' then
45
                        ceo<='0';
46
                        cnt<=0;
47
                else
48
                        ceo<='0';
49
                        if ce_i='1' then
50
                                cnt<=32;
51
                                reg1<=unsigned(op1_i);
52
                                reg2<=unsigned(op2_i);
53
                                acc_sum<=(others=>'0');
54
                        elsif cnt>0 then
55
                                acc_sum<=acc_sum+pp;
56
                                reg1<=reg1(reg1'high-1 downto 0)&"0";
57
                                reg2<="0"&reg2(reg2'high downto 1);
58
                                cnt<=cnt-1;
59
                                if cnt=1 then
60
                                        ceo<='1';
61
                                end if;
62
                        end if;
63
                end if;
64
        end if;
65
end process;
66
 
67
result_o<=std_logic_vector(acc_sum);
68
ce_o<=ceo;
69
 
70
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.