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[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [firmware/] [test007.asm] - Blame information for rev 6

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/*
 * This test verifies bitwise shift operations.
 */
 
        lc r100, 0x10000000 // test result output pointer
        lc r101, halt
        lc r102, failure
 
        lc r16, 0x10000004 // output pointer
 
// Test left shifts (by comparison with self-addition)
 
        lc r0, 0x12345678
        mov r3, r0 // for comparison
        lc r32, sl_loop
        mov r1, 0 // counter
 
sl_loop:
        sl r2, r0, r1
        sw r16, r2
        cjmpne r102, r2, r3
        add r1, r1, 1
        add r3, r3, r3
        cjmpul r32, r1, 32
 
// Test unsigned right shifts (by comparison with pre-calculated values)
 
        lc r32, sru_loop
        lc r17, sru_expected_data
        mov r1, 0 // counter
 
sru_loop:
        sru r2, r0, r1
        sw r16, r2
        lw r3, r17
        cjmpne r102, r2, r3
        add r1, r1, 1
        add r17, r17, 4
        cjmpul r32, r1, 32
 
// Test signed right shifts (by comparison with pre-calculated values)
 
        lc r0, 0x87654321
        lc r32, srs_loop
        lc r17, srs_expected_data
        mov r1, 0 // counter
 
srs_loop:
        srs r2, r0, r1
        sw r16, r2
        lw r3, r17
        cjmpne r102, r2, r3
        add r1, r1, 1
        add r17, r17, 4
        cjmpul r32, r1, 32
 
// Report success
        sw r100, 1
        jmp r101
 
failure:
        sw r100, 2
 
halt:
        hlt
        jmp r101
 
sru_expected_data:
        .word 0x12345678
        .word 0x091A2B3C
        .word 0x048D159E
        .word 0x02468ACF
        .word 0x01234567
        .word 0x0091A2B3
        .word 0x0048D159
        .word 0x002468AC
        .word 0x00123456
        .word 0x00091A2B
        .word 0x00048D15
        .word 0x0002468A
        .word 0x00012345
        .word 0x000091A2
        .word 0x000048D1
        .word 0x00002468
        .word 0x00001234
        .word 0x0000091A
        .word 0x0000048D
        .word 0x00000246
        .word 0x00000123
        .word 0x00000091
        .word 0x00000048
        .word 0x00000024
        .word 0x00000012
        .word 0x00000009
        .word 0x00000004
        .word 0x00000002
        .word 0x00000001
        .word 0x00000000
        .word 0x00000000
        .word 0x00000000
 
srs_expected_data:
        .word 0x87654321
        .word 0xC3B2A190
        .word 0xE1D950C8
        .word 0xF0ECA864
        .word 0xF8765432
        .word 0xFC3B2A19
        .word 0xFE1D950C
        .word 0xFF0ECA86
        .word 0xFF876543
        .word 0xFFC3B2A1
        .word 0xFFE1D950
        .word 0xFFF0ECA8
        .word 0xFFF87654
        .word 0xFFFC3B2A
        .word 0xFFFE1D95
        .word 0xFFFF0ECA
        .word 0xFFFF8765
        .word 0xFFFFC3B2
        .word 0xFFFFE1D9
        .word 0xFFFFF0EC
        .word 0xFFFFF876
        .word 0xFFFFFC3B
        .word 0xFFFFFE1D
        .word 0xFFFFFF0E
        .word 0xFFFFFF87
        .word 0xFFFFFFC3
        .word 0xFFFFFFE1
        .word 0xFFFFFFF0
        .word 0xFFFFFFF8
        .word 0xFFFFFFFC
        .word 0xFFFFFFFE
        .word 0xFFFFFFFF

Line No.	Rev	Author	Line
1	2	ring0_mipt	`/*`
2			`* This test verifies bitwise shift operations.`
3			`*/`
4
5			`lc r100, 0x10000000 // test result output pointer`
6			`lc r101, halt`
7			`lc r102, failure`
8
9			`lc r16, 0x10000004 // output pointer`
10
11			`// Test left shifts (by comparison with self-addition)`
12
13			`lc r0, 0x12345678`
14			`mov r3, r0 // for comparison`
15			`lc r32, sl_loop`
16			`mov r1, 0 // counter`
17
18			`sl_loop:`
19			`sl r2, r0, r1`
20			`sw r16, r2`
21			`cjmpne r102, r2, r3`
22			`add r1, r1, 1`
23			`add r3, r3, r3`
24			`cjmpul r32, r1, 32`
25
26			`// Test unsigned right shifts (by comparison with pre-calculated values)`
27
28			`lc r32, sru_loop`
29			`lc r17, sru_expected_data`
30			`mov r1, 0 // counter`
31
32			`sru_loop:`
33			`sru r2, r0, r1`
34			`sw r16, r2`
35			`lw r3, r17`
36			`cjmpne r102, r2, r3`
37			`add r1, r1, 1`
38			`add r17, r17, 4`
39			`cjmpul r32, r1, 32`
40
41			`// Test signed right shifts (by comparison with pre-calculated values)`
42
43			`lc r0, 0x87654321`
44			`lc r32, srs_loop`
45			`lc r17, srs_expected_data`
46			`mov r1, 0 // counter`
47
48			`srs_loop:`
49			`srs r2, r0, r1`
50			`sw r16, r2`
51			`lw r3, r17`
52			`cjmpne r102, r2, r3`
53			`add r1, r1, 1`
54			`add r17, r17, 4`
55			`cjmpul r32, r1, 32`
56
57			`// Report success`
58			`sw r100, 1`
59			`jmp r101`
60
61			`failure:`
62			`sw r100, 2`
63
64			`halt:`
65			`hlt`
66			`jmp r101`
67
68			`sru_expected_data:`
69			`.word 0x12345678`
70			`.word 0x091A2B3C`
71			`.word 0x048D159E`
72			`.word 0x02468ACF`
73			`.word 0x01234567`
74			`.word 0x0091A2B3`
75			`.word 0x0048D159`
76			`.word 0x002468AC`
77			`.word 0x00123456`
78			`.word 0x00091A2B`
79			`.word 0x00048D15`
80			`.word 0x0002468A`
81			`.word 0x00012345`
82			`.word 0x000091A2`
83			`.word 0x000048D1`
84			`.word 0x00002468`
85			`.word 0x00001234`
86			`.word 0x0000091A`
87			`.word 0x0000048D`
88			`.word 0x00000246`
89			`.word 0x00000123`
90			`.word 0x00000091`
91			`.word 0x00000048`
92			`.word 0x00000024`
93			`.word 0x00000012`
94			`.word 0x00000009`
95			`.word 0x00000004`
96			`.word 0x00000002`
97			`.word 0x00000001`
98			`.word 0x00000000`
99			`.word 0x00000000`
100			`.word 0x00000000`
101
102			`srs_expected_data:`
103			`.word 0x87654321`
104			`.word 0xC3B2A190`
105			`.word 0xE1D950C8`
106			`.word 0xF0ECA864`
107			`.word 0xF8765432`
108			`.word 0xFC3B2A19`
109			`.word 0xFE1D950C`
110			`.word 0xFF0ECA86`
111			`.word 0xFF876543`
112			`.word 0xFFC3B2A1`
113			`.word 0xFFE1D950`
114			`.word 0xFFF0ECA8`
115			`.word 0xFFF87654`
116			`.word 0xFFFC3B2A`
117			`.word 0xFFFE1D95`
118			`.word 0xFFFF0ECA`
119			`.word 0xFFFF8765`
120			`.word 0xFFFFC3B2`
121			`.word 0xFFFFE1D9`
122			`.word 0xFFFFF0EC`
123			`.word 0xFFFFF876`
124			`.word 0xFFFFFC3B`
125			`.word 0xFFFFFE1D`
126			`.word 0xFFFFFF0E`
127			`.word 0xFFFFFF87`
128			`.word 0xFFFFFFC3`
129			`.word 0xFFFFFFE1`
130			`.word 0xFFFFFFF0`
131			`.word 0xFFFFFFF8`
132			`.word 0xFFFFFFFC`
133			`.word 0xFFFFFFFE`
134			`.word 0xFFFFFFFF`

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[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [firmware/] [test007.asm] - Blame information for rev 6