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--/**************************************************************************************************************
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--*
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--* L Z R W 1 E N C O D E R C O R E
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--*
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--* A high throughput loss less data compression core.
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--*
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--* Copyright 2012-2013 Lukas Schrittwieser (LS)
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--*
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--* This program is free software: you can redistribute it and/or modify
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--* it under the terms of the GNU General Public License as published by
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--* the Free Software Foundation, either version 2 of the License, or
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--* (at your option) any later version.
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--*
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--* This program is distributed in the hope that it will be useful,
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--* but WITHOUT ANY WARRANTY; without even the implied warranty of
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--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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--* GNU General Public License for more details.
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--*
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--* You should have received a copy of the GNU General Public License
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--* along with this program; if not, write to the Free Software
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--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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--* Or see <http://www.gnu.org/licenses/>
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--*
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--***************************************************************************************************************
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--*
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--* Change Log:
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--*
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--* Version 1.0 - 2012/6/21 - LS
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--* started file
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--*
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--* Version 1.0 - 2013/04/05 - LS
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--* release
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--*
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--***************************************************************************************************************
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--*
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--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
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--*
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--***************************************************************************************************************
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--*
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--*
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--*
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--***************************************************************************************************************
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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library UNISIM;
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use UNISIM.VComponents.all;
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entity historyBuffer is
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port (
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ClkxCI : in std_logic;
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RstxRI : in std_logic;
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WriteInxDI : in std_logic_vector(7 downto 0);
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WExSI : in std_logic;
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NextWrAdrxDO : out std_logic_vector(11 downto 0); -- memory address at which the next byte will be written
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RExSI : in std_logic; -- initiate a memory read back
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ReadBackAdrxDI : in std_logic_vector(11 downto 2); -- for speed up read back is only word adressable
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ReadBackxDO : out std_logic_vector(16*8-1 downto 0);
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ReadBackDonexSO : out std_logic); -- indicates that requested read back data is available
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end historyBuffer;
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architecture Behavioral of historyBuffer is
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signal WrPtrxDN, WrPtrxDP : std_logic_vector(11 downto 0) := (others => '0');
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signal Ram0RdAdrAxD, Ram0RdAdrBxD : std_logic_vector(13 downto 0);
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signal Ram1RdAdrAxD, Ram1RdAdrBxD : std_logic_vector(13 downto 0);
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signal Ram0AdrAxD, Ram1AdrAxD : std_logic_vector(13 downto 0);
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signal RamWrDataxD : std_logic_vector(31 downto 0);
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signal Ram0OutAxD, Ram0OutBxD : std_logic_vector(31 downto 0);
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signal Ram1OutAxD, Ram1OutBxD : std_logic_vector(31 downto 0);
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signal Ram0WExS, Ram1WExS : std_logic_vector(3 downto 0);
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signal Ram0EnAxS, Ram1EnAxS : std_logic;
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signal RdAdrIntxD : integer; -- to split up long expressions (type casts)
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signal Ram0RdAdrBasexD, Ram1RdAdrBasexD : integer;
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signal DataReadyxSN, DataReadyxSP : std_logic;
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signal LastReadBackAdrxDN, LastReadBackAdrxDP : std_logic_vector(11 downto 2);
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begin
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-- Note: If the requested address is not a multiple of 8 (ie bit 2 is 1) the
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-- first word (4 bytes) we read is in ram 1. Therefore the adress for ram 0 has
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-- to be incremented by 1.
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RdAdrIntxD <= to_integer(unsigned(ReadBackAdrxDI(11 downto 3)));
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Ram0RdAdrBasexD <= RdAdrIntxD when ReadBackAdrxDI(2) = '0' else (RdAdrIntxD+1);
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Ram1RdAdrBasexD <= RdAdrIntxD;
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Ram0RdAdrAxD <= std_logic_vector(to_unsigned(Ram0RdAdrBasexD, 9)) & "00000";
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Ram0RdAdrBxD <= std_logic_vector(to_unsigned(Ram0RdAdrBasexD+1, 9)) & "00000";
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Ram1RdAdrAxD <= std_logic_vector(to_unsigned(Ram1RdAdrBasexD, 9)) & "00000";
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Ram1RdAdrBxD <= std_logic_vector(to_unsigned(Ram1RdAdrBasexD+1, 9)) & "00000";
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-- select port A address based on read/write mode
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Ram0AdrAxD <= Ram0RdAdrAxD when WExSI = '0' else (WrPtrxDP(11 downto 3)& "00000");
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Ram1AdrAxD <= Ram1RdAdrAxD when WExSI = '0' else (WrPtrxDP(11 downto 3) & "00000");
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-- Ram0AdrAxD <= Ram0RdAdrAxD when WExSI = '0' else (WrAdrxDI(11 downto 3)& "00000");
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-- Ram1AdrAxD <= Ram1RdAdrAxD when WExSI = '0' else (WrAdrxDI(11 downto 3) & "00000");
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RamWrDataxD <= WriteInxDI & WriteInxDI & WriteInxDI & WriteInxDI;
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-- The memory behaves like a register -> save requested adress for output decoder
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LastReadBackAdrxDN <= ReadBackAdrxDI;
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-- the read back value is reordered depending on wether the requested address
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-- is a multiple of 8 or not. See comment above.
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ReadBackxDO <= (Ram1OutBxD & Ram0OutBxD & Ram1OutAxD & Ram0OutAxD) when LastReadBackAdrxDP(2) = '0' else (Ram0OutBxD & Ram1OutBxD & Ram0OutAxD & Ram1OutAxD);
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Ram0EnAxS <= WExSI or RExSI;
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Ram1EnAxS <= WExSI or RExSI;
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-- implement a write address counter
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wrCntPrcs : process (WExSI, WrPtrxDP)
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begin
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WrPtrxDN <= WrPtrxDP;
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Ram0WExS <= "0000";
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Ram1WExS <= "0000";
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if WExSI = '1' then
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if WrPtrxDP = x"fff" then
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WrPtrxDN <= x"000";
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else
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WrPtrxDN <= std_logic_vector(to_unsigned(to_integer(unsigned(WrPtrxDP))+1, 12));
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end if;
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-- decode lower 3 bits to the 8 write enable lines
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if WrPtrxDP(2) = '0' then
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-- write to ram 0
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Ram0WExS(to_integer(unsigned(WrPtrxDP(1 downto 0)))) <= '1';
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else
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Ram1WExS(to_integer(unsigned(WrPtrxDP(1 downto 0)))) <= '1';
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end if;
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-- if WrAdrxDI(2) = '0' then
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-- -- write to ram 0
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-- Ram0WExS(to_integer(unsigned(WrAdrxDI(1 downto 0)))) <= '1';
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-- else
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-- Ram1WExS(to_integer(unsigned(WrAdrxDI(1 downto 0)))) <= '1';
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-- end if;
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end if;
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end process wrCntPrcs;
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DataReadyxSN <= RExSI; -- it takes one clock cycle to read the
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-- data, delay read enable for one cycle to create a output valid signal
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NextWrAdrxDO <= WrPtrxDP;
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ReadBackDonexSO <= DataReadyxSP;
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process (ClkxCI, RstxRI)
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begin -- process
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if RstxRI = '1' then
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LastReadBackAdrxDP <= (others => '0');
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WrPtrxDP <= (others => '0');
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DataReadyxSP <= '0';
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elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
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LastReadBackAdrxDP <= LastReadBackAdrxDN;
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WrPtrxDP <= WrPtrxDN;
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DataReadyxSP <= DataReadyxSN;
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end if;
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end process;
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-- port A is used to write and read (lower bytes) data, port B is for read only
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HistMem0Inst : RAMB16BWER
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generic map (
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-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
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DATA_WIDTH_A => 36,
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DATA_WIDTH_B => 36,
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-- DOA_REG/DOB_REG: Optional output register (0 or 1)
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DOA_REG => 0,
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DOB_REG => 0,
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-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
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EN_RSTRAM_A => true,
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EN_RSTRAM_B => true,
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-- INIT_A/INIT_B: Initial values on output port
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INIT_A => X"000000000",
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INIT_B => X"000000000",
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-- INIT_FILE: Optional file used to specify initial RAM contents
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INIT_FILE => "NONE",
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-- RSTTYPE: "SYNC" or "ASYNC"
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RSTTYPE => "SYNC",
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-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
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RST_PRIORITY_A => "CE",
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RST_PRIORITY_B => "CE",
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-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
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SIM_COLLISION_CHECK => "ALL",
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-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
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SIM_DEVICE => "SPARTAN6",
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-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
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SRVAL_A => X"000000000",
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SRVAL_B => X"000000000",
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-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
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WRITE_MODE_A => "WRITE_FIRST",
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WRITE_MODE_B => "WRITE_FIRST"
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)
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port map (
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-- Port A Data: 32-bit (each) Port A data
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DOA => Ram0OutAxD, -- 32-bit A port data output
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DOPA => open, -- 4-bit A port parity output
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-- Port B Data: 32-bit (each) Port B data
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DOB => Ram0OutBxD,
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DOPB => open,
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-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
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ADDRA => Ram0AdrAxD, -- 14-bit A port address input
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CLKA => ClkxCI, -- 1-bit A port clock input
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ENA => Ram0EnAxS, -- 1-bit A port enable input
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REGCEA => '1', -- 1-bit A port register clock enable input
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RSTA => RstxRI, -- 1-bit A port register set/reset input
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WEA => Ram0WExS, -- 4-bit Port A byte-wide write enable input
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-- Port A Data: 32-bit (each) Port A data
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DIA => RamWrDataxD, -- 32-bit A port data input
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DIPA => "0000", -- 4-bit A port parity input
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-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
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ADDRB => Ram0RdAdrBxD, -- 14-bit B port address input
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CLKB => ClkxCI, -- 1-bit B port clock input
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ENB => RExSI, -- 1-bit B port enable input
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REGCEB => '1', -- 1-bit B port register clock enable input
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RSTB => RstxRI, -- 1-bit B port register set/reset input
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WEB => x"0", -- 4-bit Port B byte-wide write enable input
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-- Port B Data: 32-bit (each) Port B data
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DIB => x"00000000", -- 32-bit B port data input
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DIPB => x"0" -- 4-bit B port parity input
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);
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-- RAM 1
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-- port A is used to write and read (lower bytes) data, port B is for read only
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HistMem1Inst : RAMB16BWER
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generic map (
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-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
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DATA_WIDTH_A => 36,
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DATA_WIDTH_B => 36,
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-- DOA_REG/DOB_REG: Optional output register (0 or 1)
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DOA_REG => 0,
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DOB_REG => 0,
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-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
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EN_RSTRAM_A => true,
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EN_RSTRAM_B => true,
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-- INIT_A/INIT_B: Initial values on output port
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INIT_A => X"000000000",
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INIT_B => X"000000000",
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-- INIT_FILE: Optional file used to specify initial RAM contents
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INIT_FILE => "NONE",
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-- RSTTYPE: "SYNC" or "ASYNC"
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RSTTYPE => "SYNC",
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-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
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RST_PRIORITY_A => "CE",
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RST_PRIORITY_B => "CE",
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-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
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SIM_COLLISION_CHECK => "ALL",
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-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
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SIM_DEVICE => "SPARTAN6",
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-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
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SRVAL_A => X"000000000",
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SRVAL_B => X"000000000",
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-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
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WRITE_MODE_A => "WRITE_FIRST",
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WRITE_MODE_B => "WRITE_FIRST"
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)
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port map (
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-- Port A Data: 32-bit (each) Port A data
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DOA => Ram1OutAxD, -- 32-bit A port data output
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DOPA => open, -- 4-bit A port parity output
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-- Port B Data: 32-bit (each) Port B data
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DOB => Ram1OutBxD,
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DOPB => open,
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-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
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ADDRA => Ram1AdrAxD, -- 14-bit A port address input
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CLKA => ClkxCI, -- 1-bit A port clock input
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ENA => Ram1EnAxS, -- 1-bit A port enable input
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REGCEA => '1', -- 1-bit A port register clock enable input
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RSTA => RstxRI, -- 1-bit A port register set/reset input
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WEA => Ram1WExS, -- 4-bit Port A byte-wide write enable input
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-- Port A Data: 32-bit (each) Port A data
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DIA => RamWrDataxD, -- 32-bit A port data input
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DIPA => "0000", -- 4-bit A port parity input
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-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
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ADDRB => Ram1RdAdrBxD, -- 14-bit B port address input
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CLKB => ClkxCI, -- 1-bit B port clock input
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ENB => RExSI, -- 1-bit B port enable input
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REGCEB => '1', -- 1-bit B port register clock enable input
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RSTB => RstxRI, -- 1-bit B port register set/reset input
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WEB => x"0", -- 4-bit Port B byte-wide write enable input
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-- Port B Data: 32-bit (each) Port B data
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DIB => x"00000000", -- 32-bit B port data input
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DIPB => x"0" -- 4-bit B port parity input
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);
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end Behavioral;
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