1 |
2 |
habicht |
--/**************************************************************************************************************
|
2 |
|
|
--*
|
3 |
|
|
--* L Z R W 1 E N C O D E R C O R E
|
4 |
|
|
--*
|
5 |
|
|
--* A high throughput loss less data compression core.
|
6 |
|
|
--*
|
7 |
|
|
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
|
8 |
|
|
--*
|
9 |
|
|
--* This program is free software: you can redistribute it and/or modify
|
10 |
|
|
--* it under the terms of the GNU General Public License as published by
|
11 |
|
|
--* the Free Software Foundation, either version 2 of the License, or
|
12 |
|
|
--* (at your option) any later version.
|
13 |
|
|
--*
|
14 |
|
|
--* This program is distributed in the hope that it will be useful,
|
15 |
|
|
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
16 |
|
|
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
17 |
|
|
--* GNU General Public License for more details.
|
18 |
|
|
--*
|
19 |
|
|
--* You should have received a copy of the GNU General Public License
|
20 |
|
|
--* along with this program; if not, write to the Free Software
|
21 |
|
|
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
22 |
|
|
--* Or see <http://www.gnu.org/licenses/>
|
23 |
|
|
--*
|
24 |
|
|
--***************************************************************************************************************
|
25 |
|
|
--*
|
26 |
|
|
--* Change Log:
|
27 |
|
|
--*
|
28 |
|
|
--* Version 1.0 - 2012/7/22 - LS
|
29 |
|
|
--* started file
|
30 |
|
|
--*
|
31 |
|
|
--* Version 1.0 - 2013/04/05 - LS
|
32 |
|
|
--* release
|
33 |
|
|
--*
|
34 |
|
|
--***************************************************************************************************************
|
35 |
|
|
--*
|
36 |
|
|
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
|
37 |
|
|
--*
|
38 |
|
|
--***************************************************************************************************************
|
39 |
|
|
--*
|
40 |
|
|
--* Implements a 4 byte input, 1 byte output FIFO buffer. Note: so far only writes where all 4 bytes contain
|
41 |
|
|
--* data are supported.
|
42 |
|
|
--*
|
43 |
|
|
--***************************************************************************************************************
|
44 |
|
|
|
45 |
|
|
library IEEE;
|
46 |
|
|
use IEEE.STD_LOGIC_1164.all;
|
47 |
|
|
use IEEE.NUMERIC_STD.all;
|
48 |
|
|
|
49 |
|
|
library UNISIM;
|
50 |
|
|
use UNISIM.VComponents.all;
|
51 |
|
|
|
52 |
|
|
entity InputFIFO is
|
53 |
|
|
|
54 |
|
|
port (
|
55 |
|
|
ClkxCI : in std_logic;
|
56 |
|
|
RstxRI : in std_logic;
|
57 |
|
|
DInxDI : in std_logic_vector(31 downto 0);
|
58 |
|
|
-- SelInxSI : in std_logic_vector(3 downto 0); -- not supported
|
59 |
|
|
WExSI : in std_logic;
|
60 |
|
|
StopOutputxSI : in std_logic;
|
61 |
|
|
BusyxSO : out std_logic;
|
62 |
|
|
DOutxDO : out std_logic_vector(7 downto 0);
|
63 |
|
|
OutStrobexSO : out std_logic;
|
64 |
|
|
LengthxDO : out integer range 0 to 2048);
|
65 |
|
|
|
66 |
|
|
end InputFIFO;
|
67 |
|
|
|
68 |
|
|
architecture Behavioral of InputFIFO is
|
69 |
|
|
|
70 |
|
|
constant ADR_BIT_LEN : integer := 11; -- addresses are in _bytes_
|
71 |
|
|
constant DEPTH : integer := 2048; -- max length of the fifo in _bytes_
|
72 |
|
|
|
73 |
|
|
signal LengthxDN, LengthxDP : integer range 0 to DEPTH := 0; -- number of _bytes_ in fifo
|
74 |
|
|
signal WrPtrxDN, WrPtrxDP : integer range 0 to DEPTH-1 := 0; -- write pointer in _bytes_
|
75 |
|
|
signal RdPtrxDN, RdPtrxDP : integer range 0 to DEPTH-1 := 0; -- read pointer in _bytes_
|
76 |
|
|
signal DoWritexS, DoReadxS : std_logic;
|
77 |
|
|
signal OutStrobexSN, OutStrobexSP : std_logic := '0';
|
78 |
|
|
signal BusyxSN, BusyxSP : std_logic := '0';
|
79 |
|
|
|
80 |
|
|
signal BRamDOutxD : std_logic_vector(31 downto 0);
|
81 |
|
|
signal BRamDInxD : std_logic_vector(31 downto 0);
|
82 |
|
|
signal BRamWrAdrxD : std_logic_vector(13 downto 0);
|
83 |
|
|
signal BRamRdAdrxD : std_logic_vector(13 downto 0);
|
84 |
|
|
|
85 |
|
|
begin -- Behavorial
|
86 |
|
|
|
87 |
|
|
-- implement write port logic
|
88 |
|
|
process (LengthxDP, WExSI, WrPtrxDP)
|
89 |
|
|
begin
|
90 |
|
|
WrPtrxDN <= WrPtrxDP;
|
91 |
|
|
BusyxSN <= '0';
|
92 |
|
|
BRamWrAdrxD <= std_logic_vector(to_unsigned(WrPtrxDP, ADR_BIT_LEN)) & "000";
|
93 |
|
|
DoWritexS <= '0';
|
94 |
|
|
|
95 |
|
|
if WExSI = '1' and LengthxDP <= (DEPTH-4) then
|
96 |
|
|
DoWritexS <= '1';
|
97 |
|
|
if WrPtrxDP < DEPTH-4 then
|
98 |
|
|
WrPtrxDN <= WrPtrxDP + 4;
|
99 |
|
|
else
|
100 |
|
|
WrPtrxDN <= 0;
|
101 |
|
|
end if;
|
102 |
|
|
end if;
|
103 |
|
|
-- use busy signal as an almost full indicator
|
104 |
|
|
if LengthxDP >= DEPTH-8 then -- indicate it when we have room for two or less writes
|
105 |
|
|
BusyxSN <= '1';
|
106 |
|
|
end if;
|
107 |
|
|
end process;
|
108 |
|
|
|
109 |
|
|
-- purpose: implement data output port logic
|
110 |
|
|
process (DInxDI, LengthxDP, RdPtrxDP, StopOutputxSI)
|
111 |
|
|
begin
|
112 |
|
|
RdPtrxDN <= RdPtrxDP;
|
113 |
|
|
DoReadxS <= '0';
|
114 |
|
|
OutStrobexSN <= '0';
|
115 |
|
|
BRamDInxD <= DInxDI;
|
116 |
|
|
BRamRdAdrxD <= std_logic_vector(to_unsigned(RdPtrxDP, ADR_BIT_LEN)) & "000";
|
117 |
|
|
|
118 |
|
|
if LengthxDP > 0 and StopOutputxSI = '0' then
|
119 |
|
|
DoReadxS <= '1';
|
120 |
|
|
OutStrobexSN <= '1'; -- bram delays data output by one clock cycle, do same for strobe
|
121 |
|
|
if RdPtrxDP < DEPTH-1 then
|
122 |
|
|
RdPtrxDN <= RdPtrxDP + 1;
|
123 |
|
|
else
|
124 |
|
|
RdPtrxDN <= 0;
|
125 |
|
|
end if;
|
126 |
|
|
end if;
|
127 |
|
|
|
128 |
|
|
end process;
|
129 |
|
|
|
130 |
|
|
-- purpose: implement a length counter
|
131 |
|
|
lenCntPrcs : process (DoReadxS, DoWritexS, LengthxDP)
|
132 |
|
|
begin
|
133 |
|
|
LengthxDN <= LengthxDP;
|
134 |
|
|
if DoWritexS = '1' and DoReadxS = '0' then
|
135 |
|
|
if LengthxDP <= (DEPTH-4) then
|
136 |
|
|
LengthxDN <= LengthxDP + 4;
|
137 |
|
|
else
|
138 |
|
|
assert false report "Input FIFO overrun" severity error;
|
139 |
|
|
end if;
|
140 |
|
|
end if;
|
141 |
|
|
if DoWritexS = '0' and DoReadxS = '1' then
|
142 |
|
|
assert LengthxDP > 0 report "input FIFO underrun" severity error;
|
143 |
|
|
LengthxDN <= LengthxDP - 1;
|
144 |
|
|
end if;
|
145 |
|
|
if DoWritexS = '1' and DoReadxS = '1' then
|
146 |
|
|
assert LengthxDP < DEPTH-3 report "Input FIFO underrun at simultaneous read and write" severity error;
|
147 |
|
|
LengthxDN <= LengthxDP + 4 - 1;
|
148 |
|
|
end if;
|
149 |
|
|
end process lenCntPrcs;
|
150 |
|
|
|
151 |
|
|
DOutxDO <= BRamDOutxD(7 downto 0);
|
152 |
|
|
LengthxDO <= LengthxDP;
|
153 |
|
|
OutStrobexSO <= OutStrobexSP;
|
154 |
|
|
BusyxSO <= BusyxSP;
|
155 |
|
|
|
156 |
|
|
-- purpose: implement registers
|
157 |
|
|
process (ClkxCI, RstxRI)
|
158 |
|
|
begin
|
159 |
|
|
if ClkxCI'event and ClkxCI = '1' then -- rising clock edge
|
160 |
|
|
if RstxRI = '1' then
|
161 |
|
|
LengthxDP <= 0;
|
162 |
|
|
WrPtrxDP <= 0;
|
163 |
|
|
RdPtrxDP <= 0;
|
164 |
|
|
OutStrobexSP <= '0';
|
165 |
|
|
BusyxSP <= '0';
|
166 |
|
|
else
|
167 |
|
|
LengthxDP <= LengthxDN;
|
168 |
|
|
WrPtrxDP <= WrPtrxDN;
|
169 |
|
|
RdPtrxDP <= RdPtrxDN;
|
170 |
|
|
OutStrobexSP <= OutStrobexSN;
|
171 |
|
|
BusyxSP <= BusyxSN;
|
172 |
|
|
end if;
|
173 |
|
|
end if;
|
174 |
|
|
end process;
|
175 |
|
|
|
176 |
|
|
FifoBRam : RAMB16BWER
|
177 |
|
|
generic map (
|
178 |
|
|
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
|
179 |
|
|
DATA_WIDTH_A => 36,
|
180 |
|
|
DATA_WIDTH_B => 9,
|
181 |
|
|
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
|
182 |
|
|
DOA_REG => 0,
|
183 |
|
|
DOB_REG => 0,
|
184 |
|
|
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
|
185 |
|
|
EN_RSTRAM_A => true,
|
186 |
|
|
EN_RSTRAM_B => true,
|
187 |
|
|
-- INIT_A/INIT_B: Initial values on output port
|
188 |
|
|
INIT_A => X"000000000",
|
189 |
|
|
INIT_B => X"000000000",
|
190 |
|
|
-- INIT_FILE: Optional file used to specify initial RAM contents
|
191 |
|
|
INIT_FILE => "NONE",
|
192 |
|
|
-- RSTTYPE: "SYNC" or "ASYNC"
|
193 |
|
|
RSTTYPE => "SYNC",
|
194 |
|
|
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
|
195 |
|
|
RST_PRIORITY_A => "CE",
|
196 |
|
|
RST_PRIORITY_B => "CE",
|
197 |
|
|
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
|
198 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
199 |
|
|
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
|
200 |
|
|
SIM_DEVICE => "SPARTAN6",
|
201 |
|
|
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
|
202 |
|
|
SRVAL_A => X"000000000",
|
203 |
|
|
SRVAL_B => X"000000000",
|
204 |
|
|
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
205 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
206 |
|
|
WRITE_MODE_B => "WRITE_FIRST"
|
207 |
|
|
)
|
208 |
|
|
port map (
|
209 |
|
|
-- Port A Data: 32-bit (each) Port A data
|
210 |
|
|
DOA => open, -- 32-bit A port data output
|
211 |
|
|
DOPA => open, -- 4-bit A port parity output
|
212 |
|
|
-- Port B Data: 32-bit (each) Port B data
|
213 |
|
|
DOB => BRamDOutxD, -- 32-bit B port data output
|
214 |
|
|
DOPB => open, -- 4-bit B port parity output
|
215 |
|
|
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
|
216 |
|
|
ADDRA => BRamWrAdrxD, -- 14-bit A port address input
|
217 |
|
|
CLKA => ClkxCI, -- 1-bit A port clock input
|
218 |
|
|
ENA => DoWritexS, -- 1-bit A port enable input
|
219 |
|
|
REGCEA => '1', -- 1-bit A port register clock enable input
|
220 |
|
|
RSTA => RstxRI, -- 1-bit A port register set/reset input
|
221 |
|
|
WEA => "1111", -- 4-bit Port A byte-wide write enable input
|
222 |
|
|
-- Port A Data: 32-bit (each) Port A data
|
223 |
|
|
DIA => DInxDI, -- 32-bit A port data input
|
224 |
|
|
DIPA => "0000", -- 4-bit A port parity input
|
225 |
|
|
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
|
226 |
|
|
ADDRB => BRamRdAdrxD, -- 14-bit B port address input
|
227 |
|
|
CLKB => ClkxCI, -- 1-bit B port clock input
|
228 |
|
|
ENB => DoReadxS, -- 1-bit B port enable input
|
229 |
|
|
REGCEB => '1', -- 1-bit B port register clock enable input
|
230 |
|
|
RSTB => RstxRI, -- 1-bit B port register set/reset input
|
231 |
|
|
WEB => "0000", -- 4-bit Port B byte-wide write enable input
|
232 |
|
|
-- Port B Data: 32-bit (each) Port B data
|
233 |
|
|
DIB => x"00000000", -- 32-bit B port data input
|
234 |
|
|
DIPB => "0000" -- 4-bit B port parity input
|
235 |
|
|
);
|
236 |
|
|
|
237 |
|
|
end Behavioral;
|