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habicht |
--/**************************************************************************************************************
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--*
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--* L Z R W 1 E N C O D E R C O R E
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--*
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--* A high throughput loss less data compression core.
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--*
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--* Copyright 2012-2013 Lukas Schrittwieser (LS)
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--*
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--* This program is free software: you can redistribute it and/or modify
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--* it under the terms of the GNU General Public License as published by
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--* the Free Software Foundation, either version 2 of the License, or
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--* (at your option) any later version.
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--*
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--* This program is distributed in the hope that it will be useful,
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--* but WITHOUT ANY WARRANTY; without even the implied warranty of
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--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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--* GNU General Public License for more details.
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--*
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--* You should have received a copy of the GNU General Public License
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--* along with this program; if not, write to the Free Software
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--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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--* Or see <http://www.gnu.org/licenses/>
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--*
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--***************************************************************************************************************
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--*
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--* Change Log:
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--*
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--* Version 1.0 - 2012/10/16 - LS
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--* started file
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--*
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--* Version 1.0 - 2013/04/05 - LS
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--* release
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--*
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--***************************************************************************************************************
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--*
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--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
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--*
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--***************************************************************************************************************
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--*
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--* Simple testbench for manual signal inspection for histroy buffer.
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--*
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--***************************************************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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-------------------------------------------------------------------------------
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entity historyBuffer_tb is
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end historyBuffer_tb;
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-------------------------------------------------------------------------------
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architecture tb of historyBuffer_tb is
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component historyBuffer
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port (
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ClkxCI : in std_logic;
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RstxRI : in std_logic;
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WriteInxDI : in std_logic_vector(7 downto 0);
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WExSI : in std_logic;
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NextWrAdrxDO : out std_logic_vector(11 downto 0);
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RExSI : in std_logic;
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ReadBackAdrxDI : in std_logic_vector(11 downto 2);
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ReadBackxDO : out std_logic_vector(16*8-1 downto 0);
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ReadBackDonexSO : out std_logic);
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end component;
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-- component ports
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signal ClkxCI : std_logic;
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signal RstxRI : std_logic := '1';
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signal WriteInxDI : std_logic_vector(7 downto 0) := (others => '0');
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signal WExSI : std_logic := '0';
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signal NextWrAdrxDO : std_logic_vector(11 downto 0);
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signal RExSI : std_logic := '0';
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signal ReadBackAdrxDI : std_logic_vector(11 downto 2) := (others => '0');
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signal ReadBackxDO : std_logic_vector(16*8-1 downto 0);
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signal ReadBackDonexSO : std_logic;
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-- clock
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signal Clk : std_logic := '1';
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begin -- tb
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-- component instantiation
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DUT: historyBuffer
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port map (
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ClkxCI => ClkxCI,
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RstxRI => RstxRI,
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WriteInxDI => WriteInxDI,
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WExSI => WExSI,
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NextWrAdrxDO => NextWrAdrxDO,
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RExSI => RExSI,
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ReadBackAdrxDI => ReadBackAdrxDI,
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ReadBackxDO => ReadBackxDO,
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ReadBackDonexSO => ReadBackDonexSO);
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-- clock generation
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Clk <= not Clk after 10 ns;
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ClkxCI <= Clk;
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-- waveform generation
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WaveGen_Proc: process
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begin
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wait for 10 ns;
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wait until Clk = '1';
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RstxRI <= '0';
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-- first: write some data to buffer
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"00";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"01";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"02";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"03";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"04";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"05";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"06";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"07";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"08";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"09";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"0a";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"0b";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"0c";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"0d";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"0e";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"0f";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"10";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"11";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"12";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WriteInxDI <= x"13";
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WExSI <= '1';
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wait until Clk'event and Clk='1';
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WExSI <= '0';
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-- now read back
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ReadBackAdrxDI <= "0000000000";
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wait until Clk'event and Clk='1';
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ReadBackAdrxDI <= "0000000001";
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wait until Clk'event and Clk='1';
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ReadBackAdrxDI <= "0000000010";
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wait until Clk'event and Clk='1';
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wait;
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end process WaveGen_Proc;
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end tb;
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-------------------------------------------------------------------------------
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configuration historyBuffer_tb_tb_cfg of historyBuffer_tb is
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for tb
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end for;
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end historyBuffer_tb_tb_cfg;
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-------------------------------------------------------------------------------
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