URL https://opencores.org/ocsvn/lzrw1-compressor-core/lzrw1-compressor-core/trunk

Subversion Repositories lzrw1-compressor-core

[/] [lzrw1-compressor-core/] [trunk/] [hw/] [xst_14_2/] [historyTb.vhd] - Blame information for rev 2

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library ieee;
use ieee.std_logic_1164.all;
 
-------------------------------------------------------------------------------
 
entity historyBuffer_tb is
 
end historyBuffer_tb;
 
-------------------------------------------------------------------------------
 
architecture tb of historyBuffer_tb is
 
  component historyBuffer
    port (
      ClkxCI          : in  std_logic;
      RstxRI          : in  std_logic;
      WriteInxDI      : in  std_logic_vector(7 downto 0);
      WExSI           : in  std_logic;
      NextWrAdrxDO    : out std_logic_vector(11 downto 0);
      RExSI           : in  std_logic;
      ReadBackAdrxDI  : in  std_logic_vector(11 downto 2);
      ReadBackxDO     : out std_logic_vector(16*8-1 downto 0);
      ReadBackDonexSO : out std_logic);
  end component;
 
  -- component ports
  signal ClkxCI          : std_logic;
  signal RstxRI          : std_logic := '1';
  signal WriteInxDI      : std_logic_vector(7 downto 0) := (others => '0');
  signal WExSI           : std_logic := '0';
  signal NextWrAdrxDO    : std_logic_vector(11 downto 0);
  signal RExSI           : std_logic := '0';
  signal ReadBackAdrxDI  : std_logic_vector(11 downto 2);
  signal ReadBackxDO     : std_logic_vector(16*8-1 downto 0);
  signal ReadBackDonexSO : std_logic;
 
  -- clock
  signal Clk : std_logic := '1';
 
begin  -- tb
 
  -- component instantiation
  DUT: historyBuffer
    port map (
      ClkxCI          => ClkxCI,
      RstxRI          => RstxRI,
      WriteInxDI      => WriteInxDI,
      WExSI           => WExSI,
      NextWrAdrxDO    => NextWrAdrxDO,
      RExSI           => RExSI,
      ReadBackAdrxDI  => ReadBackAdrxDI,
      ReadBackxDO     => ReadBackxDO,
      ReadBackDonexSO => ReadBackDonexSO);
 
  -- clock generation
  Clk <= not Clk after 10 ns;
  ClkxCI <= Clk;
 
  -- waveform generation
  WaveGen_Proc: process
  begin
    wait for 10 ns;
    wait until Clk = '1';
    RstxRI <= '0';
 
    -- first: write some data to buffer
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"00";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"01";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"02";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"03";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"04";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"05";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"06";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"07";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"08";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"09";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"0a";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"0b";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"0c";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"0d";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"0e";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"0f";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"10";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"11";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"12";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
 WriteInxDI <= x"13";
    WExSI <= '1';
    wait until Clk'event and Clk='1';
    WExSI <= '0';
 
    -- now read back
    ReadBackAdrxDI <= "0000000000";
    wait until Clk'event and Clk='1';
    ReadBackAdrxDI <= "0000000001";
    wait until Clk'event and Clk='1';
    ReadBackAdrxDI <= "0000000002";
    wait until Clk'event and Clk='1';
 
 
 
 
  end process WaveGen_Proc;
 
 
 
end tb;
 
-------------------------------------------------------------------------------
 
configuration historyBuffer_tb_tb_cfg of historyBuffer_tb is
  for tb
  end for;
end historyBuffer_tb_tb_cfg;
 
-------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	2	habicht
2
3			`library ieee;`
4			`use ieee.std_logic_1164.all;`
5
6			`-------------------------------------------------------------------------------`
7
8			`entity historyBuffer_tb is`
9
10			`end historyBuffer_tb;`
11
12			`-------------------------------------------------------------------------------`
13
14			`architecture tb of historyBuffer_tb is`
15
16			`component historyBuffer`
17			`port (`
18			`ClkxCI : in std_logic;`
19			`RstxRI : in std_logic;`
20			`WriteInxDI : in std_logic_vector(7 downto 0);`
21			`WExSI : in std_logic;`
22			`NextWrAdrxDO : out std_logic_vector(11 downto 0);`
23			`RExSI : in std_logic;`
24			`ReadBackAdrxDI : in std_logic_vector(11 downto 2);`
25			`ReadBackxDO : out std_logic_vector(16*8-1 downto 0);`
26			`ReadBackDonexSO : out std_logic);`
27			`end component;`
28
29			`-- component ports`
30			`signal ClkxCI : std_logic;`
31			`signal RstxRI : std_logic := '1';`
32			`signal WriteInxDI : std_logic_vector(7 downto 0) := (others => '0');`
33			`signal WExSI : std_logic := '0';`
34			`signal NextWrAdrxDO : std_logic_vector(11 downto 0);`
35			`signal RExSI : std_logic := '0';`
36			`signal ReadBackAdrxDI : std_logic_vector(11 downto 2);`
37			`signal ReadBackxDO : std_logic_vector(16*8-1 downto 0);`
38			`signal ReadBackDonexSO : std_logic;`
39
40			`-- clock`
41			`signal Clk : std_logic := '1';`
42
43			`begin -- tb`
44
45			`-- component instantiation`
46			`DUT: historyBuffer`
47			`port map (`
48			`ClkxCI => ClkxCI,`
49			`RstxRI => RstxRI,`
50			`WriteInxDI => WriteInxDI,`
51			`WExSI => WExSI,`
52			`NextWrAdrxDO => NextWrAdrxDO,`
53			`RExSI => RExSI,`
54			`ReadBackAdrxDI => ReadBackAdrxDI,`
55			`ReadBackxDO => ReadBackxDO,`
56			`ReadBackDonexSO => ReadBackDonexSO);`
57
58			`-- clock generation`
59			`Clk <= not Clk after 10 ns;`
60			`ClkxCI <= Clk;`
61
62			`-- waveform generation`
63			`WaveGen_Proc: process`
64			`begin`
65			`wait for 10 ns;`
66			`wait until Clk = '1';`
67			`RstxRI <= '0';`
68
69			`-- first: write some data to buffer`
70			`wait until Clk'event and Clk='1';`
71			`WriteInxDI <= x"00";`
72			`WExSI <= '1';`
73			`wait until Clk'event and Clk='1';`
74			`WriteInxDI <= x"01";`
75			`WExSI <= '1';`
76			`wait until Clk'event and Clk='1';`
77			`WriteInxDI <= x"02";`
78			`WExSI <= '1';`
79			`wait until Clk'event and Clk='1';`
80			`WriteInxDI <= x"03";`
81			`WExSI <= '1';`
82			`wait until Clk'event and Clk='1';`
83			`WriteInxDI <= x"04";`
84			`WExSI <= '1';`
85			`wait until Clk'event and Clk='1';`
86			`WriteInxDI <= x"05";`
87			`WExSI <= '1';`
88			`wait until Clk'event and Clk='1';`
89			`WriteInxDI <= x"06";`
90			`WExSI <= '1';`
91			`wait until Clk'event and Clk='1';`
92			`WriteInxDI <= x"07";`
93			`WExSI <= '1';`
94			`wait until Clk'event and Clk='1';`
95			`WriteInxDI <= x"08";`
96			`WExSI <= '1';`
97			`wait until Clk'event and Clk='1';`
98			`WriteInxDI <= x"09";`
99			`WExSI <= '1';`
100			`wait until Clk'event and Clk='1';`
101			`WriteInxDI <= x"0a";`
102			`WExSI <= '1';`
103			`wait until Clk'event and Clk='1';`
104			`WriteInxDI <= x"0b";`
105			`WExSI <= '1';`
106			`wait until Clk'event and Clk='1';`
107			`WriteInxDI <= x"0c";`
108			`WExSI <= '1';`
109			`wait until Clk'event and Clk='1';`
110			`WriteInxDI <= x"0d";`
111			`WExSI <= '1';`
112			`wait until Clk'event and Clk='1';`
113			`WriteInxDI <= x"0e";`
114			`WExSI <= '1';`
115			`wait until Clk'event and Clk='1';`
116			`WriteInxDI <= x"0f";`
117			`WExSI <= '1';`
118			`wait until Clk'event and Clk='1';`
119			`WriteInxDI <= x"10";`
120			`WExSI <= '1';`
121			`wait until Clk'event and Clk='1';`
122			`WriteInxDI <= x"11";`
123			`WExSI <= '1';`
124			`wait until Clk'event and Clk='1';`
125			`WriteInxDI <= x"12";`
126			`WExSI <= '1';`
127			`wait until Clk'event and Clk='1';`
128			`WriteInxDI <= x"13";`
129			`WExSI <= '1';`
130			`wait until Clk'event and Clk='1';`
131			`WExSI <= '0';`
132
133			`-- now read back`
134			`ReadBackAdrxDI <= "0000000000";`
135			`wait until Clk'event and Clk='1';`
136			`ReadBackAdrxDI <= "0000000001";`
137			`wait until Clk'event and Clk='1';`
138			`ReadBackAdrxDI <= "0000000002";`
139			`wait until Clk'event and Clk='1';`
140
141
142
143
144			`end process WaveGen_Proc;`
145
146
147
148			`end tb;`
149
150			`-------------------------------------------------------------------------------`
151
152			`configuration historyBuffer_tb_tb_cfg of historyBuffer_tb is`
153			`for tb`
154			`end for;`
155			`end historyBuffer_tb_tb_cfg;`
156
157			`-------------------------------------------------------------------------------`

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Subversion Repositories lzrw1-compressor-core

[/] [lzrw1-compressor-core/] [trunk/] [hw/] [xst_14_2/] [historyTb.vhd] - Blame information for rev 2