URL https://opencores.org/ocsvn/lzrw1-compressor-core/lzrw1-compressor-core/trunk

Subversion Repositories lzrw1-compressor-core

[/] [lzrw1-compressor-core/] [trunk/] [hw/] [xst_14_2/] [iseconfig/] [LZRWcompressor.projectmgr] - Blame information for rev 3

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         2
      
      
         CompressorTop - Behavioral (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/HDL/CompressorTop.vhd)
      
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      CompressorTop - Behavioral (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/HDL/CompressorTop.vhd)
   
   
      
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      hash.vhd
   
   
      
         1
         work
      
      
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      0
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      work
   
   
      
         1
         Configure Target Device
         Design Utilities
         Implement Design/Map
         Implement Design/Place & Route/Back-annotate Pin Locations
         Implement Design/Place & Route/Generate IBIS Model
         Implement Design/Place & Route/Generate Post-Place & Route Static Timing
         Implement Design/Translate
         User Constraints
      
      
         Implement Design
      
      4
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000
      false
      Implement Design
   
   
      
         2
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         /CompressorTop_tb - TB |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|CompressorTopTb.vhd
         /CompressorTop_tb - TB |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|CompressorTopTb.vhd/DUT - CompressorTop - Behavioral/LZRWcompressorInst - LZRWcompressor - Behavioral
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         /HashTable_tb - tb G:|e-|logic-analyzer|LZRW-compressor|hw|testbench|TbHash.vhd
         /HashTable_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor-OC|lzrw1-compressor-core|lzrw1-compressor-core|trunk|hw|testbench|HastTb.vhd
         /HashTable_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|TbHash.vhd
         /InputFIFO_tb - tb D:|e-|logic-analyzer|compression-test|hw|testbench|InputFIFOTb.vhd
         /InputFIFO_tb - tb G:|e-|logic-analyzer|LZRW-compressor|hw|testbench|InputFIFOTb.vhd
         /InputFIFO_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor-OC|lzrw1-compressor-core|lzrw1-compressor-core|trunk|hw|testbench|InputFIFOTb.vhd
         /InputFIFO_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|InputFIFOTb.vhd
         /LZRWcompressor_tb - tb D:|e-|logic-analyzer|compression-test|hw|testbench|LZRWcompressorTb.vhd
         /LZRWcompressor_tb - tb G:|e-|logic-analyzer|LZRW-compressor|hw|testbench|LZRWcompressorTb.vhd
         /LZRWcompressor_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor-OC|lzrw1-compressor-core|lzrw1-compressor-core|trunk|hw|testbench|LZRWcompressorTb.vhd
         /LZRWcompressor_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|LZRWcompressorTb.vhd
         /comparator_tb - Tb D:|e-|logic-analyzer|compression-test|hw|HDL|comparator_tb.vhd
         /comparator_tb - Tb G:|e-|logic-analyzer|LZRW-compressor|hw|HDL|comparator_tb.vhd
         /comparator_tb - Tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|HDL|comparator_tb.vhd
         /historyBuffer_tb - tb D:|e-|logic-analyzer|compression-test|hw|HDL|historyTb.vhd
         /historyBuffer_tb - tb G:|e-|logic-analyzer|LZRW-compressor|hw|HDL|historyTb.vhd
         /historyBuffer_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|HDL|historyTb.vhd
         /outputEncoder_tb - Tb D:|e-|logic-analyzer|compression-test|hw|testbench|outputEncoderTb.vhd
         /outputEncoder_tb - Tb G:|e-|logic-analyzer|LZRW-compressor|hw|testbench|outputEncoderTb.vhd
         /outputEncoder_tb - Tb |home|lukas|e-|logic-analyzer|LZRW-compressor-OC|lzrw1-compressor-core|lzrw1-compressor-core|trunk|hw|testbench|outputEncoderTb.vhd
         /outputEncoder_tb - Tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|outputEncoderTb.vhd
         /outputFIFO_tb - tb D:|e-|logic-analyzer|compression-test|hw|testbench|outputFIFOTb.vhd
         /outputFIFO_tb - tb G:|e-|logic-analyzer|LZRW-compressor|hw|testbench|outputFIFOTb.vhd
         /outputFIFO_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|outputFIFOTb.vhd
      
      
         LZRWcompressor_tb - tb (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/testbench/LZRWcompressorTb.vhd)
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000018e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000018e0000000100000000000000000000000100000000
      false
      LZRWcompressor_tb - tb (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/testbench/LZRWcompressorTb.vhd)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000
      false
      
   
   
      
         1
      
      
         Simulate Behavioral Model
      
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      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000
      false
      Simulate Behavioral Model
   
   000000ff0000000000000002000000c20000008b01000000060100000002
   Implementation
   
      
         1
      
      
         
      
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      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000
      false
      
   


Line No.	Rev	Author	Line
1	2	habicht
2
3
4
5
6
7
8
9			`2`
10
11
12	3	habicht	`CompressorTop - Behavioral (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/HDL/CompressorTop.vhd)`
13	2	habicht
14			`0`
15			`0`
16			`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000011e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000011e0000000100000000000000000000000100000000`
17			`true`
18	3	habicht	`CompressorTop - Behavioral (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/HDL/CompressorTop.vhd)`
19	2	habicht
20
21
22			`1`
23			`Design Utilities`
24
25
26
27
28			`0`
29			`0`
30			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000012d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012d0000000100000000`
31			`false`
32
33
34
35
36			`1`
37
38
39			`0`
40			`0`
41			`000000ff000000000000000100000000000000000100000000000000000000000000000000000002af000000040101000100000000000000000000000064ffffffff000000810000000000000004000000510000000100000000000000290000000100000000000000840000000100000000000001b10000000100000000`
42			`false`
43			`hash.vhd`
44
45
46
47			`1`
48			`work`
49
50
51			`0`
52			`0`
53			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000`
54			`false`
55			`work`
56
57
58
59			`1`
60			`Configure Target Device`
61			`Design Utilities`
62			`Implement Design/Map`
63			`Implement Design/Place & Route/Back-annotate Pin Locations`
64			`Implement Design/Place & Route/Generate IBIS Model`
65			`Implement Design/Place & Route/Generate Post-Place & Route Static Timing`
66			`Implement Design/Translate`
67			`User Constraints`
68
69
70	3	habicht	`Implement Design`
71	2	habicht
72	3	habicht	`4`
73	2	habicht	`0`
74			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000`
75			`false`
76	3	habicht	`Implement Design`
77	2	habicht
78
79
80			`2`
81	3	habicht	`/CompressorTop_tb - TB \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor-OC\|lzrw1-compressor-core\|lzrw1-compressor-core\|trunk\|hw\|testbench\|CompressorTopTb.vhd`
82	2	habicht	`/CompressorTop_tb - TB \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|CompressorTopTb.vhd`
83			`/CompressorTop_tb - TB \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|CompressorTopTb.vhd/DUT - CompressorTop - Behavioral/LZRWcompressorInst - LZRWcompressor - Behavioral`
84			`/HashTable_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|TbHash.vhd`
85			`/HashTable_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|TbHash.vhd`
86	3	habicht	`/HashTable_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor-OC\|lzrw1-compressor-core\|lzrw1-compressor-core\|trunk\|hw\|testbench\|HastTb.vhd`
87	2	habicht	`/HashTable_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|TbHash.vhd`
88			`/InputFIFO_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|InputFIFOTb.vhd`
89			`/InputFIFO_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|InputFIFOTb.vhd`
90	3	habicht	`/InputFIFO_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor-OC\|lzrw1-compressor-core\|lzrw1-compressor-core\|trunk\|hw\|testbench\|InputFIFOTb.vhd`
91	2	habicht	`/InputFIFO_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|InputFIFOTb.vhd`
92			`/LZRWcompressor_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|LZRWcompressorTb.vhd`
93			`/LZRWcompressor_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|LZRWcompressorTb.vhd`
94	3	habicht	`/LZRWcompressor_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor-OC\|lzrw1-compressor-core\|lzrw1-compressor-core\|trunk\|hw\|testbench\|LZRWcompressorTb.vhd`
95	2	habicht	`/LZRWcompressor_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|LZRWcompressorTb.vhd`
96			`/comparator_tb - Tb D:\|e-\|logic-analyzer\|compression-test\|hw\|HDL\|comparator_tb.vhd`
97			`/comparator_tb - Tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|comparator_tb.vhd`
98			`/comparator_tb - Tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|comparator_tb.vhd`
99			`/historyBuffer_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|HDL\|historyTb.vhd`
100			`/historyBuffer_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|historyTb.vhd`
101			`/historyBuffer_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|historyTb.vhd`
102			`/outputEncoder_tb - Tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|outputEncoderTb.vhd`
103			`/outputEncoder_tb - Tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputEncoderTb.vhd`
104	3	habicht	`/outputEncoder_tb - Tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor-OC\|lzrw1-compressor-core\|lzrw1-compressor-core\|trunk\|hw\|testbench\|outputEncoderTb.vhd`
105	2	habicht	`/outputEncoder_tb - Tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputEncoderTb.vhd`
106			`/outputFIFO_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|outputFIFOTb.vhd`
107			`/outputFIFO_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputFIFOTb.vhd`
108			`/outputFIFO_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputFIFOTb.vhd`
109
110
111	3	habicht	`LZRWcompressor_tb - tb (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/testbench/LZRWcompressorTb.vhd)`
112	2	habicht
113			`0`
114			`0`
115			`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000018e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000018e0000000100000000000000000000000100000000`
116			`false`
117	3	habicht	`LZRWcompressor_tb - tb (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/testbench/LZRWcompressorTb.vhd)`
118	2	habicht
119
120
121			`1`
122			`Design Utilities`
123
124
125
126
127			`0`
128			`0`
129			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000`
130			`false`
131
132
133
134
135			`1`
136
137
138			`Simulate Behavioral Model`
139
140			`0`
141			`0`
142	3	habicht	`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000`
143	2	habicht	`false`
144			`Simulate Behavioral Model`
145
146			`000000ff0000000000000002000000c20000008b01000000060100000002`
147	3	habicht	`Implementation`
148	2	habicht
149
150			`1`
151
152
153	3	habicht
154	2	habicht
155			`0`
156			`0`
157			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000`
158			`false`
159	3	habicht
160	2	habicht
161

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Subversion Repositories lzrw1-compressor-core

[/] [lzrw1-compressor-core/] [trunk/] [hw/] [xst_14_2/] [iseconfig/] [LZRWcompressor.projectmgr] - Blame information for rev 3