| 1 |
3 |
MichaelA |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 1
|
| 2 |
2 |
MichaelA |
|
| 3 |
|
|
|
| 4 |
|
|
LOC OBJECT CODE LINE SOURCE TEXT
|
| 5 |
|
|
VALUE
|
| 6 |
|
|
|
| 7 |
|
|
00001 ;*******************************************************************************
|
| 8 |
|
|
00002 ; M16C5x_Tst4.ASM
|
| 9 |
|
|
00003 ;
|
| 10 |
|
|
00004 ;
|
| 11 |
|
|
00005 ; This program tests the receive function of the SSP UART.
|
| 12 |
|
|
00006 ;
|
| 13 |
|
|
00007 ; The UART is polled to determine if there is a Rx character available. If a
|
| 14 |
|
|
00008 ; Rx character is available, the character is read from the UART RHR (Rx FIFO)
|
| 15 |
|
|
00009 ; into a temporary location in the register file. The received character is
|
| 16 |
|
|
00010 ; checked for upper/lower case. If it is an upper case character, the charac-
|
| 17 |
|
|
00011 ; ter is converted to lower case. If it is a lower case character, the charac-
|
| 18 |
|
|
00012 ; ter is converter to upper case. After conversion, the character is sent to
|
| 19 |
|
|
00013 ; the UART's Tx FIFO.
|
| 20 |
|
|
00014 ;
|
| 21 |
|
|
00015 ;*******************************************************************************
|
| 22 |
|
|
00016
|
| 23 |
|
|
00017 LIST P=16F59, R=DEC
|
| 24 |
|
|
00018
|
| 25 |
|
|
00019 ;-------------------------------------------------------------------------------
|
| 26 |
|
|
00020 ; Set ScratchPadRam here. If you are using a PIC16C5X device, use:
|
| 27 |
|
|
00021 ;ScratchPadRam EQU 0x10
|
| 28 |
|
|
00022 ; Otherwise, use:
|
| 29 |
|
|
00023 ;ScratchPadRam EQU 0x20
|
| 30 |
|
|
00024 ;-------------------------------------------------------------------------------
|
| 31 |
|
|
00025
|
| 32 |
|
|
00000010 00026 ScratchPadRAM EQU 0x10
|
| 33 |
|
|
00027
|
| 34 |
|
|
00028 ;-------------------------------------------------------------------------------
|
| 35 |
|
|
00029 ; Variables
|
| 36 |
|
|
00030 ;-------------------------------------------------------------------------------
|
| 37 |
|
|
00031
|
| 38 |
|
|
00000000 00032 INDF EQU 0 ; Indirect Register File Access Location
|
| 39 |
|
|
00000001 00033 Tmr0 EQU 1 ; Timer 0
|
| 40 |
|
|
00000002 00034 PCL EQU 2 ; Low Byte Program Counter
|
| 41 |
|
|
00000003 00035 Status EQU 3 ; Processor Status Register
|
| 42 |
|
|
00000004 00036 FSR EQU 4 ; File Select Register
|
| 43 |
|
|
00000005 00037 PortA EQU 5 ; I/O Port A Address
|
| 44 |
|
|
00000006 00038 PortB EQU 6 ; I/O Port B Address
|
| 45 |
|
|
00000007 00039 PortC EQU 7 ; I/O Port C Address
|
| 46 |
|
|
00040
|
| 47 |
|
|
0000000A 00041 SPI_CR EQU 0x0A ; SPI Control Register Shadow/Working Copy
|
| 48 |
|
|
0000000B 00042 SPI_SR EQU 0x0B ; SPI Status Register Shadow/Working Copy
|
| 49 |
|
|
0000000C 00043 SPI_DIO_H EQU 0x0C ; 1st byte To/From from SPI Rcv FIFO
|
| 50 |
|
|
0000000D 00044 SPI_DIO_L EQU 0x0D ; 2nd byte To/From from SPI Rcv FIFO
|
| 51 |
|
|
00045
|
| 52 |
|
|
0000000F 00046 DlyCntr EQU 0x0F ; General Purpose Delay Counter Register
|
| 53 |
|
|
00047
|
| 54 |
|
|
00048 ;-------------------------------------------------------------------------------
|
| 55 |
|
|
00049 ; SPI Control Register Bit Map (M16C5x TRIS A register)
|
| 56 |
|
|
00050 ;-------------------------------------------------------------------------------
|
| 57 |
|
|
00051
|
| 58 |
|
|
00000000 00052 SPI_CR_REn EQU 0 ; Enable MISO Data Capture
|
| 59 |
|
|
00000001 00053 SPI_CR_SSel EQU 1 ; Slv Select: 0 - Ext SEEPROM, 1 - SSP_UART
|
| 60 |
3 |
MichaelA |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 2
|
| 61 |
2 |
MichaelA |
|
| 62 |
|
|
|
| 63 |
|
|
LOC OBJECT CODE LINE SOURCE TEXT
|
| 64 |
|
|
VALUE
|
| 65 |
|
|
|
| 66 |
|
|
00000002 00054 SPI_CR_MD0 EQU 2 ; SPI Md[1:0]: UART - Mode 0 or Mode 3
|
| 67 |
|
|
00000003 00055 SPI_CR_MD1 EQU 3 ; SEEPROM - Mode 0 or Mode 3
|
| 68 |
|
|
00000004 00056 SPI_CR_BR0 EQU 4 ; SPI Baud Rate: 0 - Clk/2, ... Clk/128
|
| 69 |
|
|
00000005 00057 SPI_CR_BR1 EQU 5 ; Default: 110 - Clk/64
|
| 70 |
|
|
00000006 00058 SPI_CR_BR2 EQU 6 ; Clk/2 29.4912 MHz
|
| 71 |
|
|
00000007 00059 SPI_CR_DIR EQU 7 ; SPI Shift Direction: 0 - MSB, 1 - LSB
|
| 72 |
|
|
00060
|
| 73 |
|
|
00061 ;-------------------------------------------------------------------------------
|
| 74 |
|
|
00062 ; SPI Status Register Bit Map (M16C5x Port A input)
|
| 75 |
|
|
00063 ;-------------------------------------------------------------------------------
|
| 76 |
|
|
00064
|
| 77 |
|
|
00000000 00065 SPI_SR_TF_EF EQU 0 ; SPI TF Empty Flag (All Data Transmitted)
|
| 78 |
|
|
00000001 00066 SPI_SR_TF_FF EQU 1 ; SPI TF Full Flag (Possible Overrun Error)
|
| 79 |
|
|
00000002 00067 SPI_SR_RF_EF EQU 2 ; SPI RF Empty Flag (Data Available)
|
| 80 |
|
|
00000003 00068 SPI_SR_RF_FF EQU 3 ; SPI RF Full Flag (Possible Overrun Error)
|
| 81 |
|
|
00000004 00069 SPI_SR_DE EQU 4 ; SSP UART RS-485 Drive Enable
|
| 82 |
|
|
00000005 00070 SPI_SR_RTS EQU 5 ; SSP UART Request-To-Send Modem Control Out
|
| 83 |
|
|
00000006 00071 SPI_SR_CTS EQU 6 ; SSP UART Clear-To-Send Modem Control Input
|
| 84 |
|
|
00000007 00072 SPI_SR_IRQ EQU 7 ; SSP UART Interrupt Request Output
|
| 85 |
|
|
00073
|
| 86 |
|
|
00074 ;-------------------------------------------------------------------------------
|
| 87 |
|
|
00075 ; SSP UART Control Register (RA = 000) (16-bits Total) (Read-Write)
|
| 88 |
|
|
00076 ;-------------------------------------------------------------------------------
|
| 89 |
|
|
00077
|
| 90 |
|
|
00000003 00078 UART_CR_RA EQU 3 ; Bits 7:5 SPI_DIO_H
|
| 91 |
|
|
00000001 00079 UART_CR_WnR EQU 1 ; Bit 4 SPI_DIO_H, if Set Wr, else Rd
|
| 92 |
|
|
00000002 00080 UART_CR_MD EQU 2 ; Bits 3:2 SPI_DIO_H, UART Mode: 232/485
|
| 93 |
|
|
00000001 00081 UART_CR_RTSo EQU 1 ; Bit 1 SPI_DIO_H, Request-To-Send Output
|
| 94 |
|
|
00000001 00082 UART_CR_IE EQU 1 ; Bit 0 SPI_DIO_H, Interrupt Enable
|
| 95 |
|
|
00000004 00083 UART_CR_FMT EQU 4 ; Bits 7:4 SPI_DIO_L, Serial Frame Format
|
| 96 |
|
|
00000004 00084 UART_CR_BAUD EQU 4 ; Bits 3:0 SPI_DIO_L, Serial Baud Rate
|
| 97 |
|
|
00085
|
| 98 |
|
|
00086 ;-------------------------------------------------------------------------------
|
| 99 |
|
|
00087 ; SSP UART Status Register (RA = 001) (16-bits Total) (Read-Only)
|
| 100 |
|
|
00088 ;-------------------------------------------------------------------------------
|
| 101 |
|
|
00089
|
| 102 |
|
|
00000003 00090 UART_SR_RA EQU 3 ; Bits 7:5 SPI_DIO_H
|
| 103 |
|
|
00000001 00091 UART_SR_WnR EQU 1 ; Bit 4 SPI_DIO_H, Ignored if Set
|
| 104 |
|
|
00000002 00092 UART_SR_MD EQU 2 ; Bits 3:2 SPI_DIO_H, UART Mode
|
| 105 |
|
|
00000001 00093 UART_SR_RTSi EQU 1 ; Bit 1 SPI_DIO_H, RTS signal level
|
| 106 |
|
|
00000001 00094 UART_SR_CTSi EQU 1 ; Bit 0 SPI_DIO_H, CTS signal level
|
| 107 |
|
|
00000002 00095 UART_SR_RS EQU 2 ; Bits 7:6 SPI_DIO_L, Rx FIFO State
|
| 108 |
|
|
00000002 00096 UART_SR_TS EQU 2 ; Bits 5:4 SPI_DIO_L, Tx FIFO State
|
| 109 |
|
|
00000001 00097 UART_SR_iRTO EQU 1 ; Bit 3 SPI_DIO_L, Rcv Timeout Interrupt
|
| 110 |
|
|
00000001 00098 UART_SR_iRDA EQU 1 ; Bit 2 SPI_DIO_L, Rcv Data Available
|
| 111 |
|
|
00000001 00099 UART_SR_iTHE EQU 1 ; Bit 1 SPI_DIO_L, Tx FIFO Half Empty
|
| 112 |
|
|
00000001 00100 UART_SR_iTFE EQU 1 ; Bit 0 SPI_DIO_L, Tx FIFO Empty
|
| 113 |
|
|
00101
|
| 114 |
|
|
00102 ;-------------------------------------------------------------------------------
|
| 115 |
|
|
00103 ; SSP UART Baud Rate Register (RA = 001) (16-bits Total) (Write-Only)
|
| 116 |
|
|
00104 ;-------------------------------------------------------------------------------
|
| 117 |
|
|
00105
|
| 118 |
|
|
00000004 00106 UART_BR_PS EQU 4 ; Bits 11:8 : Baud rate prescaler - (M - 1)
|
| 119 |
3 |
MichaelA |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 3
|
| 120 |
2 |
MichaelA |
|
| 121 |
|
|
|
| 122 |
|
|
LOC OBJECT CODE LINE SOURCE TEXT
|
| 123 |
|
|
VALUE
|
| 124 |
|
|
|
| 125 |
|
|
00000008 00107 UART_BR_Div EQU 8 ; Bits 7:0 : Baud rate divider - (N - 1)
|
| 126 |
|
|
00108
|
| 127 |
|
|
00109 ;-------------------------------------------------------------------------------
|
| 128 |
|
|
00110 ; SSP UART Transmit Data Register (RA = 010) (16-bits Total) (Write-Only)
|
| 129 |
|
|
00111 ;-------------------------------------------------------------------------------
|
| 130 |
|
|
00112
|
| 131 |
|
|
00000003 00113 UART_TD_RA EQU 3 ; Bits 7:5 SPI_DIO_H
|
| 132 |
|
|
00000001 00114 UART_TD_WnR EQU 1 ; Bit 4 SPI_DIO_H, Ignored if Not Set
|
| 133 |
|
|
00000001 00115 UART_TD_TFC EQU 1 ; Bit 3 SPI_DIO_H, Transmit FIFO Clr/Rst
|
| 134 |
|
|
00000001 00116 UART_TD_RFC EQU 1 ; Bit 2 SPI_DIO_H, Receive FIFO Clr/Rst
|
| 135 |
|
|
00000001 00117 UART_TD_HLD EQU 1 ; Bit 1 SPI_DIO_H, Tx delayed if Set
|
| 136 |
|
|
00000001 00118 UART_TD_Rsvd EQU 1 ; Bit 0 SPI_DIO_H, Reserved
|
| 137 |
|
|
00000008 00119 UART_TD_DO EQU 8 ; Bits 7:0 SPI_DIO_L, Tx Data: 7 or 8 bits
|
| 138 |
|
|
00120
|
| 139 |
|
|
00121 ;-------------------------------------------------------------------------------
|
| 140 |
|
|
00122 ; SSP UART Recieve Data Register (RA = 011) (16-bits Total) (Read-Only)
|
| 141 |
|
|
00123 ;-------------------------------------------------------------------------------
|
| 142 |
|
|
00124
|
| 143 |
|
|
00000003 00125 UART_RD_RA EQU 3 ; Bits 7:5 SPI_DIO_H
|
| 144 |
|
|
00000001 00126 UART_RD_WnR EQU 1 ; Bit 4 SPI_DIO_H, Ignored if Set
|
| 145 |
|
|
00000001 00127 UART_RD_TRDY EQU 1 ; Bit 3 SPI_DIO_H, Transmit Ready
|
| 146 |
|
|
00000001 00128 UART_RD_RRDY EQU 1 ; Bit 2 SPI_DIO_H, Receive Ready
|
| 147 |
|
|
00000001 00129 UART_RD_RTO EQU 1 ; Bit 1 SPI_DIO_H, Receive Time Out Det.
|
| 148 |
|
|
00000001 00130 UART_RD_RERR EQU 1 ; Bit 0 SPI_DIO_H, Receive Error Detect
|
| 149 |
|
|
00000008 00131 UART_RD_DI EQU 8 ; Bits 7:0 SPI_DIO_L, Rx Data: 7 or 8 bits
|
| 150 |
|
|
00132
|
| 151 |
|
|
00133 ;-------------------------------------------------------------------------------
|
| 152 |
|
|
00134 ; Set Reset/WDT Vector
|
| 153 |
|
|
00135 ;-------------------------------------------------------------------------------
|
| 154 |
|
|
00136
|
| 155 |
|
|
07FF 00137 ORG 0x7FF
|
| 156 |
|
|
00138
|
| 157 |
|
|
Message[306]: Crossing page boundary -- ensure page bits are set.
|
| 158 |
|
|
07FF 0A00 00139 GOTO Start
|
| 159 |
|
|
00140
|
| 160 |
|
|
00141 ;-------------------------------------------------------------------------------
|
| 161 |
|
|
00142 ; Main Program
|
| 162 |
|
|
00143 ;-------------------------------------------------------------------------------
|
| 163 |
|
|
00144
|
| 164 |
|
|
0000 00145 ORG 0x000
|
| 165 |
|
|
00146
|
| 166 |
|
|
00147 ;-------------------------------------------------------------------------------
|
| 167 |
|
|
00148
|
| 168 |
|
|
0000 0CFF 00149 Start MOVLW 0xFF ; Initialize TRIS A and TRIS B to all 1s
|
| 169 |
|
|
0001 0005 00150 TRIS 5
|
| 170 |
|
|
0002 0006 00151 TRIS 6
|
| 171 |
|
|
00152
|
| 172 |
|
|
0003 0C1E 00153 MOVLW 0x1E ; Load W with SPI CR Initial Value
|
| 173 |
|
|
0004 002A 00154 MOVWF SPI_CR ; Save copy of value
|
| 174 |
|
|
0005 0007 00155 TRIS 7 ; Initialize SPI CR
|
| 175 |
|
|
00156
|
| 176 |
|
|
0006 0C08 00157 MOVLW 0x08 ; Delay before using SPI I/F
|
| 177 |
|
|
0007 002F 00158 MOVWF DlyCntr
|
| 178 |
3 |
MichaelA |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 4
|
| 179 |
2 |
MichaelA |
|
| 180 |
|
|
|
| 181 |
|
|
LOC OBJECT CODE LINE SOURCE TEXT
|
| 182 |
|
|
VALUE
|
| 183 |
|
|
|
| 184 |
|
|
0008 02EF 00159 SPI_Init_Dly DECFSZ DlyCntr,1
|
| 185 |
|
|
0009 0A08 00160 GOTO SPI_Init_Dly
|
| 186 |
|
|
00161
|
| 187 |
|
|
000A 0C13 00162 MOVLW 0x13 ; UART CR (Hi): RS232 2-wire, RTS, IE
|
| 188 |
|
|
000B 0027 00163 MOVWF PortC ; Output to SPI and to UART
|
| 189 |
|
|
000C 0C00 00164 MOVLW 0x00 ; UART CR (Lo) Set 8N1
|
| 190 |
|
|
000D 0027 00165 MOVWF PortC
|
| 191 |
|
|
00166
|
| 192 |
|
|
000E 0C30 00167 MOVLW 0x30 ; UART BRR (Hi) PS[3:0]
|
| 193 |
|
|
000F 0027 00168 MOVWF PortC ; Output to SPI and to UART
|
| 194 |
3 |
MichaelA |
0010 0C01 00169 MOVLW 0x01 ; UART BRR (Lo) Div[7:0] (921.6k baud)
|
| 195 |
2 |
MichaelA |
0011 0027 00170 MOVWF PortC
|
| 196 |
|
|
00171
|
| 197 |
|
|
0012 0705 00172 WaitLp1 BTFSS PortA,SPI_SR_TF_EF ; Wait for UART UCR, BRR output
|
| 198 |
|
|
0013 0A12 00173 GOTO WaitLp1
|
| 199 |
|
|
00174
|
| 200 |
|
|
00175 ;-------------------------------------------------------------------------------
|
| 201 |
|
|
00176
|
| 202 |
|
|
0014 050A 00177 Rd_UART_RF BSF SPI_CR,SPI_CR_REn ; Enable SPI IF Capture MISO data
|
| 203 |
|
|
00178
|
| 204 |
|
|
0015 020A 00179 MOVF SPI_CR,0 ; Load SPI CR Shadow
|
| 205 |
|
|
0016 0007 00180 TRIS 7 ; Enable SPI I/F Receive Function
|
| 206 |
|
|
00181
|
| 207 |
|
|
0017 0C60 00182 Poll_UART_RF MOVLW 0x60 ; UART RF (Hi) RA = 3, WnR = 0
|
| 208 |
|
|
0018 0027 00183 MOVWF PortC ; Output to SPI and to UART
|
| 209 |
|
|
0019 0CFF 00184 MOVLW 0xFF ; UART RD (Lo) 0xFF = "Del" or 0x00 (Nul)
|
| 210 |
|
|
001A 0027 00185 MOVWF PortC ; Output to SPI and to UART
|
| 211 |
|
|
00186
|
| 212 |
|
|
001B 0705 00187 WaitLp2 BTFSS PortA,SPI_SR_TF_EF ; Wait for SPI TF to be empty
|
| 213 |
|
|
001C 0A1B 00188 GOTO WaitLp2
|
| 214 |
|
|
00189
|
| 215 |
|
|
001D 0207 00190 MOVF PortC,0 ; Read SPI Receive FIFO
|
| 216 |
|
|
001E 002C 00191 MOVWF SPI_DIO_H ; Store UART SR (hi byte)
|
| 217 |
|
|
00192
|
| 218 |
|
|
001F 0645 00193 WaitLp3 BTFSC PortA,SPI_SR_RF_EF ; Wait for UART Return Data (Hi)
|
| 219 |
|
|
0020 0A1F 00194 GOTO WaitLp3
|
| 220 |
|
|
00195
|
| 221 |
|
|
0021 0207 00196 MOVF PortC,0 ; Read SPI Receive FIFO
|
| 222 |
|
|
0022 002D 00197 MOVWF SPI_DIO_L ; Store UART SR (hi byte)
|
| 223 |
|
|
00198
|
| 224 |
|
|
00199 ;-------------------------------------------------------------------------------
|
| 225 |
|
|
00200
|
| 226 |
|
|
0023 074C 00201 Test_RD BTFSS SPI_DIO_H,2 ; Test RRDY bit, if Set, process RD
|
| 227 |
|
|
0024 0A17 00202 GOTO Poll_UART_RF ; Loop until character received
|
| 228 |
|
|
0025 060C 00203 BTFSC SPI_DIO_H,0 ; Test RD for error; if Set, discard
|
| 229 |
|
|
0026 0A17 00204 GOTO Poll_UART_RF ; Loop until error-free character rcvd
|
| 230 |
|
|
00205
|
| 231 |
|
|
00206 ;-------------------------------------------------------------------------------
|
| 232 |
|
|
00207
|
| 233 |
|
|
0027 06ED 00208 Tst_ExtASCII BTFSC SPI_DIO_L,7 ; Ignore Extended ASCII characters
|
| 234 |
|
|
0028 0A3B 00209 GOTO Wr_UART_TF ; Transmit Extended ASCII as is
|
| 235 |
|
|
00210
|
| 236 |
|
|
0029 0C7B 00211 Tst_LowerCase MOVLW 0x7B ; Test against 'z' + 1
|
| 237 |
3 |
MichaelA |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 5
|
| 238 |
2 |
MichaelA |
|
| 239 |
|
|
|
| 240 |
|
|
LOC OBJECT CODE LINE SOURCE TEXT
|
| 241 |
|
|
VALUE
|
| 242 |
|
|
|
| 243 |
|
|
002A 008D 00212 SUBWF SPI_DIO_L,0 ; Compare RD against 'z'
|
| 244 |
|
|
002B 0603 00213 BTFSC Status,0 ; If Status.C, RD > 'z'
|
| 245 |
|
|
002C 0A3B 00214 GT_LowerCase GOTO Wr_UART_TF ; not upper or lower case, send data
|
| 246 |
|
|
002D 0C61 00215 MOVLW 0x61 ; Load 'a'
|
| 247 |
|
|
002E 008D 00216 SUBWF SPI_DIO_L,0 ; Compare RD against 'a'
|
| 248 |
|
|
002F 0603 00217 BTFSC Status,0 ; Carry Set if RD >= 'a'
|
| 249 |
|
|
0030 0A39 00218 Is_LowerCase GOTO ChangeCase ; Is upper case, change case to lower
|
| 250 |
|
|
00219
|
| 251 |
|
|
0031 0C5B 00220 Tst_UpperCase MOVLW 0x5B ; Test against 'Z' + 1
|
| 252 |
|
|
0032 008D 00221 SUBWF SPI_DIO_L,0 ; Compare RD against 'Z'
|
| 253 |
|
|
0033 0603 00222 BTFSC Status,0 ; Carry set if Rd > 'Z'
|
| 254 |
|
|
0034 0A3B 00223 Not_UpperLower GOTO Wr_UART_TF ; Not lower case
|
| 255 |
|
|
0035 0C41 00224 MOVLW 0x41 ; Load 'A'
|
| 256 |
|
|
0036 008D 00225 SUBWF SPI_DIO_L,0 ; Compare against 'A'
|
| 257 |
|
|
0037 0703 00226 BTFSS Status,0 ; Carry set if RD >= 'A'
|
| 258 |
|
|
0038 0A3B 00227 LT_UpperCase GOTO Wr_UART_TF ; Tests complete, send data
|
| 259 |
|
|
00228
|
| 260 |
|
|
0039 00229 Is_UpperCase
|
| 261 |
|
|
0039 0C20 00230 ChangeCase MOVLW 0x20 ; Change case: LC to UC, or UC to LC
|
| 262 |
|
|
003A 01AD 00231 XORWF SPI_DIO_L,1
|
| 263 |
|
|
00232
|
| 264 |
|
|
00233 ;-------------------------------------------------------------------------------
|
| 265 |
|
|
00234
|
| 266 |
|
|
003B 040A 00235 Wr_UART_TF BCF SPI_CR,SPI_CR_REn ; Disable SPI IF Capture MISO data
|
| 267 |
|
|
00236
|
| 268 |
|
|
003C 020A 00237 MOVF SPI_CR,0 ; Load SPI CR Shadow
|
| 269 |
|
|
003D 0007 00238 TRIS 7 ; Enable SPI I/F Receive Function
|
| 270 |
|
|
00239
|
| 271 |
|
|
003E 0C50 00240 MOVLW 0x50 ; UART TF (Hi) RA = 2, WnR = 1
|
| 272 |
|
|
003F 0027 00241 MOVWF PortC ; Output to SPI and to UART
|
| 273 |
|
|
0040 020D 00242 MOVF SPI_DIO_L,0 ; Read data to transmit
|
| 274 |
|
|
0041 0027 00243 MOVWF PortC ; Output to SPI TF and to UART
|
| 275 |
|
|
00244
|
| 276 |
|
|
0042 0705 00245 WaitLp4 BTFSS PortA,SPI_SR_TF_EF ; Wait for SPI TF to be empty
|
| 277 |
|
|
0043 0A42 00246 GOTO WaitLp4
|
| 278 |
|
|
00247
|
| 279 |
|
|
0044 0A14 00248 GOTO Rd_UART_RF ; Loop Forever, send 0x55 continously
|
| 280 |
|
|
00249
|
| 281 |
|
|
00250 ;-------------------------------------------------------------------------------
|
| 282 |
|
|
00251
|
| 283 |
|
|
00252 END
|
| 284 |
3 |
MichaelA |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 6
|
| 285 |
2 |
MichaelA |
|
| 286 |
|
|
|
| 287 |
|
|
SYMBOL TABLE
|
| 288 |
|
|
LABEL VALUE
|
| 289 |
|
|
|
| 290 |
|
|
ChangeCase 00000039
|
| 291 |
|
|
DlyCntr 0000000F
|
| 292 |
|
|
FSR 00000004
|
| 293 |
|
|
GT_LowerCase 0000002C
|
| 294 |
|
|
INDF 00000000
|
| 295 |
|
|
Is_LowerCase 00000030
|
| 296 |
|
|
Is_UpperCase 00000039
|
| 297 |
|
|
LT_UpperCase 00000038
|
| 298 |
|
|
Not_UpperLower 00000034
|
| 299 |
|
|
PCL 00000002
|
| 300 |
|
|
Poll_UART_RF 00000017
|
| 301 |
|
|
PortA 00000005
|
| 302 |
|
|
PortB 00000006
|
| 303 |
|
|
PortC 00000007
|
| 304 |
|
|
Rd_UART_RF 00000014
|
| 305 |
|
|
SPI_CR 0000000A
|
| 306 |
|
|
SPI_CR_BR0 00000004
|
| 307 |
|
|
SPI_CR_BR1 00000005
|
| 308 |
|
|
SPI_CR_BR2 00000006
|
| 309 |
|
|
SPI_CR_DIR 00000007
|
| 310 |
|
|
SPI_CR_MD0 00000002
|
| 311 |
|
|
SPI_CR_MD1 00000003
|
| 312 |
|
|
SPI_CR_REn 00000000
|
| 313 |
|
|
SPI_CR_SSel 00000001
|
| 314 |
|
|
SPI_DIO_H 0000000C
|
| 315 |
|
|
SPI_DIO_L 0000000D
|
| 316 |
|
|
SPI_Init_Dly 00000008
|
| 317 |
|
|
SPI_SR 0000000B
|
| 318 |
|
|
SPI_SR_CTS 00000006
|
| 319 |
|
|
SPI_SR_DE 00000004
|
| 320 |
|
|
SPI_SR_IRQ 00000007
|
| 321 |
|
|
SPI_SR_RF_EF 00000002
|
| 322 |
|
|
SPI_SR_RF_FF 00000003
|
| 323 |
|
|
SPI_SR_RTS 00000005
|
| 324 |
|
|
SPI_SR_TF_EF 00000000
|
| 325 |
|
|
SPI_SR_TF_FF 00000001
|
| 326 |
|
|
ScratchPadRAM 00000010
|
| 327 |
|
|
Start 00000000
|
| 328 |
|
|
Status 00000003
|
| 329 |
|
|
Test_RD 00000023
|
| 330 |
|
|
Tmr0 00000001
|
| 331 |
|
|
Tst_ExtASCII 00000027
|
| 332 |
|
|
Tst_LowerCase 00000029
|
| 333 |
|
|
Tst_UpperCase 00000031
|
| 334 |
|
|
UART_BR_Div 00000008
|
| 335 |
|
|
UART_BR_PS 00000004
|
| 336 |
|
|
UART_CR_BAUD 00000004
|
| 337 |
|
|
UART_CR_FMT 00000004
|
| 338 |
|
|
UART_CR_IE 00000001
|
| 339 |
|
|
UART_CR_MD 00000002
|
| 340 |
|
|
UART_CR_RA 00000003
|
| 341 |
|
|
UART_CR_RTSo 00000001
|
| 342 |
|
|
UART_CR_WnR 00000001
|
| 343 |
3 |
MichaelA |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 7
|
| 344 |
2 |
MichaelA |
|
| 345 |
|
|
|
| 346 |
|
|
SYMBOL TABLE
|
| 347 |
|
|
LABEL VALUE
|
| 348 |
|
|
|
| 349 |
|
|
UART_RD_DI 00000008
|
| 350 |
|
|
UART_RD_RA 00000003
|
| 351 |
|
|
UART_RD_RERR 00000001
|
| 352 |
|
|
UART_RD_RRDY 00000001
|
| 353 |
|
|
UART_RD_RTO 00000001
|
| 354 |
|
|
UART_RD_TRDY 00000001
|
| 355 |
|
|
UART_RD_WnR 00000001
|
| 356 |
|
|
UART_SR_CTSi 00000001
|
| 357 |
|
|
UART_SR_MD 00000002
|
| 358 |
|
|
UART_SR_RA 00000003
|
| 359 |
|
|
UART_SR_RS 00000002
|
| 360 |
|
|
UART_SR_RTSi 00000001
|
| 361 |
|
|
UART_SR_TS 00000002
|
| 362 |
|
|
UART_SR_WnR 00000001
|
| 363 |
|
|
UART_SR_iRDA 00000001
|
| 364 |
|
|
UART_SR_iRTO 00000001
|
| 365 |
|
|
UART_SR_iTFE 00000001
|
| 366 |
|
|
UART_SR_iTHE 00000001
|
| 367 |
|
|
UART_TD_DO 00000008
|
| 368 |
|
|
UART_TD_HLD 00000001
|
| 369 |
|
|
UART_TD_RA 00000003
|
| 370 |
|
|
UART_TD_RFC 00000001
|
| 371 |
|
|
UART_TD_Rsvd 00000001
|
| 372 |
|
|
UART_TD_TFC 00000001
|
| 373 |
|
|
UART_TD_WnR 00000001
|
| 374 |
|
|
WaitLp1 00000012
|
| 375 |
|
|
WaitLp2 0000001B
|
| 376 |
|
|
WaitLp3 0000001F
|
| 377 |
|
|
WaitLp4 00000042
|
| 378 |
|
|
Wr_UART_TF 0000003B
|
| 379 |
|
|
__16F59 00000001
|
| 380 |
|
|
|
| 381 |
|
|
|
| 382 |
|
|
MEMORY USAGE MAP ('X' = Used, '-' = Unused)
|
| 383 |
|
|
|
| 384 |
|
|
0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
|
| 385 |
|
|
0040 : XXXXX----------- ---------------- ---------------- ----------------
|
| 386 |
|
|
07C0 : ---------------- ---------------- ---------------- ---------------X
|
| 387 |
|
|
|
| 388 |
|
|
All other memory blocks unused.
|
| 389 |
|
|
|
| 390 |
|
|
Program Memory Words Used: 70
|
| 391 |
|
|
Program Memory Words Free: 1978
|
| 392 |
|
|
|
| 393 |
|
|
|
| 394 |
|
|
Errors : 0
|
| 395 |
|
|
Warnings : 0 reported, 0 suppressed
|
| 396 |
|
|
Messages : 1 reported, 0 suppressed
|
| 397 |
|
|
|
| 398 |
|
|
|
