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[/] [m16c5x/] [trunk/] [RTL/] [Sim/] [tb_P16C5x.v] - Blame information for rev 2

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///////////////////////////////////////////////////////////////////////////////
//
//  Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates
//
//  All rights reserved. The source code contained herein is publicly released
//  under the terms and conditions of the GNU Lesser Public License. No part of
//  this source code may be reproduced or transmitted in any form or by any
//  means, electronic or mechanical, including photocopying, recording, or any
//  information storage and retrieval system in violation of the license under
//  which the source code is released.
//
//  The source code contained herein is free; it may be redistributed and/or 
//  modified in accordance with the terms of the GNU Lesser General Public
//  License as published by the Free Software Foundation; either version 2.1 of
//  the GNU Lesser General Public License, or any later version.
//
//  The source code contained herein is freely released WITHOUT ANY WARRANTY;
//  without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
//  PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
//  more details.)
//
//  A copy of the GNU Lesser General Public License should have been received
//  along with the source code contained herein; if not, a copy can be obtained
//  by writing to:
//
//  Free Software Foundation, Inc.
//  51 Franklin Street, Fifth Floor
//  Boston, MA  02110-1301 USA
//
//  Further, no use of this source code is permitted in any form or means
//  without inclusion of this banner prominently in any derived works. 
//
//  Michael A. Morris
//  Huntsville, AL
//
///////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
///////////////////////////////////////////////////////////////////////////////
// Company:         M. A. Morris & Associates 
// Engineer:        Michael A. Morris
//
// Create Date:     11:48:46 02/18/2008
// Design Name:     PIC16C5x
// Module Name:     C:/ISEProjects/ISE10.1i/P16C5x/tb_PIC16C5x.v
// Project Name:    PIC16C5x
// Target Device:   Spartan-II  
// Tool versions:   ISEWebPACK 10.1i SP3  
//
// Description: Verilog Test Fixture created by ISE for module: PIC16C5x. Test
//              program used to verify the execution engine. Test program uses
//              all of the instructions in the PIC16C5x instructions. Program
//              memory address range is not explicitly tested.
//
// Dependencies:        P16C5x.v 
//
// Revision: 
//
//      0.01    08B17   MAM         File Created
//
//  1.00    13F15   MAM     Modified to support P16C5x implementation.
//
// Additional Comments: 
//
///////////////////////////////////////////////////////////////////////////////
 
module tb_P16C5x_v;
 
        // UUT Module Ports
        reg     POR;
 
        reg     Clk;
        reg     ClkEn;
 
        wire    [11:0] PC;
        reg     [11:0] ROM;
 
        reg     MCLR;
        reg     T0CKI;
        reg     WDTE;
 
        wire    WE_TRISA;
    wire    WE_TRISB;
    wire    WE_TRISC;
        wire    WE_PORTA;
    wire    WE_PORTB;
    wire    WE_PORTC;
    wire    RE_PORTA;
    wire    RE_PORTB;
    wire    RE_PORTC;
 
    wire    [7:0] IO_DO;
    reg     [7:0] IO_DI;
 
        // UUT Module Test Ports
 
    wire    Rst;
 
    wire    [5:0] OPTION;
 
    wire    [11:0] IR;
    wire    [ 9:0] dIR;
        wire    [11:0] ALU_Op;
        wire    [ 8:0] KI;
        wire    Err;
 
        wire    Skip;
 
        wire    [11:0] TOS;
        wire    [11:0] NOS;
 
        wire    [7:0] W;
 
        wire    [6:0] FA;
        wire    [7:0] DO;
        wire    [7:0] DI;
 
        wire    [7:0] TMR0;
        wire    [7:0] FSR;
        wire    [7:0] STATUS;
 
    wire    T0CKI_Pls;
 
    wire    WDTClr;
        wire    [9:0] WDT;
        wire    WDT_TC;
        wire    WDT_TO;
 
    wire    [7:0] PSCntr;
        wire    PSC_Pls;
 
        // Instantiate the Unit Under Test (UUT)
 
        P16C5x  #(
                .pWDT_Size(10)
            ) uut (
                .POR(POR),
                .Clk(Clk),
                .ClkEn(ClkEn),
 
                .MCLR(MCLR),
                .T0CKI(T0CKI),
 
                .WDTE(WDTE),
 
                .PC(PC),
                .ROM(ROM),
 
                .WE_TRISA(WE_TRISA),
                .WE_TRISB(WE_TRISB),
                .WE_TRISC(WE_TRISC),
                .WE_PORTA(WE_PORTA),
                .WE_PORTB(WE_PORTB),
                .WE_PORTC(WE_PORTC),
                .RE_PORTA(RE_PORTA),
                .RE_PORTB(RE_PORTB),
                .RE_PORTC(RE_PORTC),
                .IO_DO(IO_DO),
                .IO_DI(IO_DI),
 
                .Rst(Rst),
 
                .OPTION(OPTION),
 
                .IR(IR),
                .dIR(dIR),
                .ALU_Op(ALU_Op),
                .KI(KI),
                .Err(Err),
 
                .Skip(Skip),
 
                .TOS(TOS),
                .NOS(NOS),
                .W(W),
                .FA(FA),
                .DO(DO),
                .DI(DI),
                .TMR0(TMR0),
                .FSR(FSR),
                .STATUS(STATUS),
                .T0CKI_Pls(T0CKI_Pls),
                .WDTClr(WDTClr),
                .WDT(WDT),
                .WDT_TC(WDT_TC),
                .WDT_TO(WDT_TO),
                .PSCntr(PSCntr),
                .PSC_Pls(PSC_Pls)
            );
 
        initial begin
                // Initialize Inputs
                POR     = 1;
                Clk     = 1;
        ClkEn   = 1;
//        IR      = 0;
                IO_DI   = 0;
                MCLR    = 0;
                T0CKI   = 0;
                WDTE    = 1;
 
                // Wait 100 ns for global reset to finish
                #101;
 
        POR = 0;
//        ClkEn = 1;
 
        #899;
 
        end
 
    always #5 Clk = ~Clk;
 
    always @(posedge Clk)
    begin
        if(POR)
            #1 ClkEn <= 0;
        else
            #1 ClkEn <= ~ClkEn;
    end
 
    // Test Program ROM
 
//    always @(PC or POR)
    always @(posedge Clk or posedge POR)
    begin
        if(POR)
            ROM <= 12'b1010_0000_0000;                  // GOTO    0x000   ;; Reset Vector: Jump 0x000 (Start)
        else
            case(PC[11:0])
                12'h000 : ROM <= #1 12'b0111_0110_0011; // BTFSS   0x03,3  ;; Test PD (STATUS.3), if set, not SLEEP restart
                12'h001 : ROM <= #1 12'b1010_0011_0000; // GOTO    0x030   ;; SLEEP restart, continue test program
                12'h002 : ROM <= #1 12'b1100_0000_0111; // MOVLW   0x07    ;; load OPTION
                12'h003 : ROM <= #1 12'b0000_0000_0010; // OPTION
                12'h004 : ROM <= #1 12'b0000_0100_0000; // CLRW            ;; clear working register
                12'h005 : ROM <= #1 12'b0000_0000_0101; // TRISA           ;; load W into port control registers
                12'h006 : ROM <= #1 12'b0000_0000_0110; // TRISB
                12'h007 : ROM <= #1 12'b0000_0000_0111; // TRISC
                12'h008 : ROM <= #1 12'b1010_0000_1010; // GOTO    0x00A   ;; Test GOTO
                12'h009 : ROM <= #1 12'b1100_1111_1111; // MOVLW   0xFF    ;; instruction should be skipped
                12'h00A : ROM <= #1 12'b1001_0000_1101; // CALL    0x0D    ;; Test CALL
                12'h00B : ROM <= #1 12'b0000_0010_0010; // MOVWF   0x02    ;; Test Computed GOTO, Load PCL with W
                12'h00C : ROM <= #1 12'b0000_0000_0000; // NOP             ;; No Operation
                12'h00D : ROM <= #1 12'b1000_0000_1110; // RETLW   0x0E    ;; Test RETLW, return 0x0E in W
                12'h00E : ROM <= #1 12'b1100_0000_1001; // MOVLW   0x09    ;; starting RAM + 1
                12'h00F : ROM <= #1 12'b0000_0010_0100; // MOVWF   0x04    ;; indirect address register (FSR)
//
                12'h010 : ROM <= #1 12'b1100_0001_0111; // MOVLW   0x17    ;; internal RAM count - 1
                12'h011 : ROM <= #1 12'b0000_0010_1000; // MOVWF   0x08    ;; loop counter
                12'h012 : ROM <= #1 12'b0000_0100_0000; // CLRW            ;; zero working register
                12'h013 : ROM <= #1 12'b0000_0010_0000; // MOVWF   0x00    ;; clear RAM indirectly
                12'h014 : ROM <= #1 12'b0010_1010_0100; // INCF    0x04,1  ;; increment FSR
                12'h015 : ROM <= #1 12'b0010_1110_1000; // DECFSZ  0x08,1  ;; decrement loop counter
                12'h016 : ROM <= #1 12'b1010_0001_0011; // GOTO    0x013   ;; loop until loop counter == 0
                12'h017 : ROM <= #1 12'b1100_0000_1001; // MOVLW   0x09    ;; starting RAM + 1
                12'h018 : ROM <= #1 12'b0000_0010_0100; // MOVWF   0x04    ;; reload FSR
                12'h019 : ROM <= #1 12'b1100_1110_1001; // MOVLW   0xE9    ;; set loop counter to 256 - 23
                12'h01A : ROM <= #1 12'b0000_0010_1000; // MOVWF   0x08
                12'h01B : ROM <= #1 12'b0010_0000_0000; // MOVF    0x00,0  ;; read memory into W 
                12'h01C : ROM <= #1 12'b0011_1110_1000; // INCFSZ  0x08,1  ;; increment counter loop until 0
                12'h01D : ROM <= #1 12'b1010_0001_1011; // GOTO    0x01B   ;; loop    
                12'h01E : ROM <= #1 12'b0000_0000_0100; // CLRWDT          ;; clear WDT
                12'h01F : ROM <= #1 12'b0000_0110_1000; // CLRF    0x08    ;; Clear Memory Location 0x08
//
                12'h020 : ROM <= #1 12'b0010_0110_1000; // DECF    0x08,1  ;; Decrement Memory Location 0x08
                12'h021 : ROM <= #1 12'b0001_1100_1000; // ADDWF   0x08,0  ;; Add Memory Location 0x08 to W, Store in W
                12'h022 : ROM <= #1 12'b0000_1010_1000; // SUBWF   0x08,1  ;; Subtract Memory Location 0x08
                12'h023 : ROM <= #1 12'b0011_0110_1000; // RLF     0x08,1  ;; Rotate Memory Location 0x08
                12'h024 : ROM <= #1 12'b0011_0010_1000; // RRF     0x08,1  ;; Rotate Memory Location
                12'h025 : ROM <= #1 12'b1100_0110_1001; // MOVLW   0x69    ;; Load W with test pattern: W <= 0x69
                12'h026 : ROM <= #1 12'b0000_0010_1000; // MOVWF   0x08    ;; Initialize Memory with test pattern
                12'h027 : ROM <= #1 12'b0011_1010_1000; // SWAPF   0x08,1  ;; Test SWAPF: (0x08) <= 0x96 
                12'h028 : ROM <= #1 12'b0001_0010_1000; // IORWF   0x08,1  ;; Test IORWF: (0x08) <= 0x69 | 0x96 
                12'h029 : ROM <= #1 12'b0001_0110_1000; // ANDWF   0x08,1  ;; Test ANDWF: (0x08) <= 0x69 & 0xFF
                12'h02A : ROM <= #1 12'b0001_1010_1000; // XORWF   0x08,1  :: Test XORWF: (0x08) <= 0x69 ^ 0x69
                12'h02B : ROM <= #1 12'b0010_0110_1000; // COMF    0x08    ;; Test COMF:  (0x08) <= ~0x00  
                12'h02C : ROM <= #1 12'b1101_1001_0110; // IORLW   0x96    ;; Test IORLW:      W <= 0x69 | 0x96
                12'h02D : ROM <= #1 12'b1110_0110_1001; // ANDLW   0x69    ;; Test ANDLW:      W <= 0xFF & 0x69
                12'h02E : ROM <= #1 12'b1111_0110_1001; // XORLW   0x69    ;; Test XORLW:      W <= 0x69 ^ 0x69
                12'h02F : ROM <= #1 12'b0000_0000_0011; // SLEEP           ;; Stop Execution of test program: HALT
//
                12'h030 : ROM <= #1 12'b0000_0000_0100; // CLRWDT          ;; Detected SLEEP restart, Clr WDT to reset PD
                12'h031 : ROM <= #1 12'b0110_0110_0011; // BTFSC   0x03,3  ;; Check STATUS.3, skip if ~PD clear
                12'h032 : ROM <= #1 12'b1010_0011_0100; // GOTO    0x034   ;; ~PD is set, CLRWDT cleared PD
                12'h033 : ROM <= #1 12'b1010_0011_0011; // GOTO    0x033   ;; ERROR: hold here on error
                12'h034 : ROM <= #1 12'b1100_0001_0000; // MOVLW   0x10    ;; Load FSR with non-banked RAM address
                12'h035 : ROM <= #1 12'b0000_0010_0100; // MOVWF   0x04    ;; Initialize FSR for Bit Processor Tests
                12'h036 : ROM <= #1 12'b0000_0110_0000; // CLRF    0x00    ;; Clear non-banked RAM location using INDF
                12'h037 : ROM <= #1 12'b0101_0000_0011; // BSF     0x03,0  ;; Set   STATUS.0 (C) bit 
                12'h038 : ROM <= #1 12'b0100_0010_0011; // BCF     0x03,1  ;; Clear STATUS.1 (DC) bit
                12'h039 : ROM <= #1 12'b0100_0100_0011; // BCF     0x03,2  ;; Clear STATUS.2 (Z) bit
                12'h03A : ROM <= #1 12'b0010_0000_0011; // MOVF    0x03,0  ;; Load W with STATUS
                12'h03B : ROM <= #1 12'b0011_0000_0000; // RRF     0x00,0  ;; Rotate Right RAM location: C <= 0,      W <= 0x80
                12'h03C : ROM <= #1 12'b0011_0110_0000; // RLF     0x00,0  ;; Rotate Left  RAM location: C <= 0, (INDF) <= 0x00
                12'h03D : ROM <= #1 12'b0000_0010_0000; // MOVWF   0x00    ;; Write result back to RAM: (INDF) <= 0x80
                12'h03E : ROM <= #1 12'b0000_0010_0001; // MOVWF   0x01    ;; Write to TMR0, clear Prescaler
                12'h03F : ROM <= #1 12'b1010_0100_0000; // GOTO    0x040   ;; Restart Program
//
                12'h040 : ROM <= #1 12'b0000_0000_0100; // CLRWDT          ;; Detected SLEEP restart, Clr WDT to reset PD
                12'h041 : ROM <= #1 12'b1100_1010_1010; // MOVLW   0xAA    ;; Load W with 0xAA
                12'h042 : ROM <= #1 12'b0000_0010_0101; // MOVWF   0x05    ;; WE_PortA
                12'h043 : ROM <= #1 12'b0000_0010_0110; // MOVWF   0x06    ;; WE_PortB
                12'h044 : ROM <= #1 12'b0000_0010_0111; // MOVWF   0x07    ;; WE_PortC
                12'h045 : ROM <= #1 12'b0010_0000_0101; // MOVF    0x05,0  ;; RE_PortA
                12'h046 : ROM <= #1 12'b0010_0000_0110; // MOVF    0x06,0  ;; RE_PortB
                12'h047 : ROM <= #1 12'b0010_0000_0111; // MOVF    0x07,0  ;; RE_PortC
                12'h048 : ROM <= #1 12'b0010_0110_0101; // COMF    0x05    ;; Complement PortA
                12'h049 : ROM <= #1 12'b0010_0110_0110; // COMF    0x06    ;; Complement PortB
                12'h04A : ROM <= #1 12'b0010_0110_0111; // COMF    0x07    ;; Complement PortC
                12'h04B : ROM <= #1 12'b0000_0110_0101; // CLRF    0x05    ;; Clear PortA
                12'h04C : ROM <= #1 12'b0000_0110_0110; // CLRF    0x06    ;; Clear PortB
                12'h04D : ROM <= #1 12'b0000_0110_0111; // CLRF    0x07    ;; Clear PortC
                12'h04E : ROM <= #1 12'b0000_0100_0000; // CLRW            ;; zero working register
                12'h04F : ROM <= #1 12'b1010_0000_0000; // GOTO    0x000   ;; Restart Program
//
                default : ROM <= #1 12'b1010_0000_0000; // GOTO    0x000   ;; Reset Vector: Jump 0x000 (Start)
            endcase
    end
 
endmodule
 

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Subversion Repositories m16c5x

[/] [m16c5x/] [trunk/] [RTL/] [Sim/] [tb_P16C5x.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	MichaelA	`///////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates`
4			`//`
5			`// All rights reserved. The source code contained herein is publicly released`
6			`// under the terms and conditions of the GNU Lesser Public License. No part of`
7			`// this source code may be reproduced or transmitted in any form or by any`
8			`// means, electronic or mechanical, including photocopying, recording, or any`
9			`// information storage and retrieval system in violation of the license under`
10			`// which the source code is released.`
11			`//`
12			`// The source code contained herein is free; it may be redistributed and/or`
13			`// modified in accordance with the terms of the GNU Lesser General Public`
14			`// License as published by the Free Software Foundation; either version 2.1 of`
15			`// the GNU Lesser General Public License, or any later version.`
16			`//`
17			`// The source code contained herein is freely released WITHOUT ANY WARRANTY;`
18			`// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A`
19			`// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for`
20			`// more details.)`
21			`//`
22			`// A copy of the GNU Lesser General Public License should have been received`
23			`// along with the source code contained herein; if not, a copy can be obtained`
24			`// by writing to:`
25			`//`
26			`// Free Software Foundation, Inc.`
27			`// 51 Franklin Street, Fifth Floor`
28			`// Boston, MA 02110-1301 USA`
29			`//`
30			`// Further, no use of this source code is permitted in any form or means`
31			`// without inclusion of this banner prominently in any derived works.`
32			`//`
33			`// Michael A. Morris`
34			`// Huntsville, AL`
35			`//`
36			`///////////////////////////////////////////////////////////////////////////////`
37
38			`timescale 1ns / 1ps
39
40			`///////////////////////////////////////////////////////////////////////////////`
41			`// Company: M. A. Morris & Associates`
42			`// Engineer: Michael A. Morris`
43			`//`
44			`// Create Date: 11:48:46 02/18/2008`
45			`// Design Name: PIC16C5x`
46			`// Module Name: C:/ISEProjects/ISE10.1i/P16C5x/tb_PIC16C5x.v`
47			`// Project Name: PIC16C5x`
48			`// Target Device: Spartan-II`
49			`// Tool versions: ISEWebPACK 10.1i SP3`
50			`//`
51			`// Description: Verilog Test Fixture created by ISE for module: PIC16C5x. Test`
52			`// program used to verify the execution engine. Test program uses`
53			`// all of the instructions in the PIC16C5x instructions. Program`
54			`// memory address range is not explicitly tested.`
55			`//`
56			`// Dependencies: P16C5x.v`
57			`//`
58			`// Revision:`
59			`//`
60			`// 0.01 08B17 MAM File Created`
61			`//`
62			`// 1.00 13F15 MAM Modified to support P16C5x implementation.`
63			`//`
64			`// Additional Comments:`
65			`//`
66			`///////////////////////////////////////////////////////////////////////////////`
67
68			`module tb_P16C5x_v;`
69
70			`// UUT Module Ports`
71			`reg POR;`
72
73			`reg Clk;`
74			`reg ClkEn;`
75
76			`wire [11:0] PC;`
77			`reg [11:0] ROM;`
78
79			`reg MCLR;`
80			`reg T0CKI;`
81			`reg WDTE;`
82
83			`wire WE_TRISA;`
84			`wire WE_TRISB;`
85			`wire WE_TRISC;`
86			`wire WE_PORTA;`
87			`wire WE_PORTB;`
88			`wire WE_PORTC;`
89			`wire RE_PORTA;`
90			`wire RE_PORTB;`
91			`wire RE_PORTC;`
92
93			`wire [7:0] IO_DO;`
94			`reg [7:0] IO_DI;`
95
96			`// UUT Module Test Ports`
97
98			`wire Rst;`
99
100			`wire [5:0] OPTION;`
101
102			`wire [11:0] IR;`
103			`wire [ 9:0] dIR;`
104			`wire [11:0] ALU_Op;`
105			`wire [ 8:0] KI;`
106			`wire Err;`
107
108			`wire Skip;`
109
110			`wire [11:0] TOS;`
111			`wire [11:0] NOS;`
112
113			`wire [7:0] W;`
114
115			`wire [6:0] FA;`
116			`wire [7:0] DO;`
117			`wire [7:0] DI;`
118
119			`wire [7:0] TMR0;`
120			`wire [7:0] FSR;`
121			`wire [7:0] STATUS;`
122
123			`wire T0CKI_Pls;`
124
125			`wire WDTClr;`
126			`wire [9:0] WDT;`
127			`wire WDT_TC;`
128			`wire WDT_TO;`
129
130			`wire [7:0] PSCntr;`
131			`wire PSC_Pls;`
132
133			`// Instantiate the Unit Under Test (UUT)`
134
135			`P16C5x #(`
136			`.pWDT_Size(10)`
137			`) uut (`
138			`.POR(POR),`
139			`.Clk(Clk),`
140			`.ClkEn(ClkEn),`
141
142			`.MCLR(MCLR),`
143			`.T0CKI(T0CKI),`
144
145			`.WDTE(WDTE),`
146
147			`.PC(PC),`
148			`.ROM(ROM),`
149
150			`.WE_TRISA(WE_TRISA),`
151			`.WE_TRISB(WE_TRISB),`
152			`.WE_TRISC(WE_TRISC),`
153			`.WE_PORTA(WE_PORTA),`
154			`.WE_PORTB(WE_PORTB),`
155			`.WE_PORTC(WE_PORTC),`
156			`.RE_PORTA(RE_PORTA),`
157			`.RE_PORTB(RE_PORTB),`
158			`.RE_PORTC(RE_PORTC),`
159			`.IO_DO(IO_DO),`
160			`.IO_DI(IO_DI),`
161
162			`.Rst(Rst),`
163
164			`.OPTION(OPTION),`
165
166			`.IR(IR),`
167			`.dIR(dIR),`
168			`.ALU_Op(ALU_Op),`
169			`.KI(KI),`
170			`.Err(Err),`
171
172			`.Skip(Skip),`
173
174			`.TOS(TOS),`
175			`.NOS(NOS),`
176			`.W(W),`
177			`.FA(FA),`
178			`.DO(DO),`
179			`.DI(DI),`
180			`.TMR0(TMR0),`
181			`.FSR(FSR),`
182			`.STATUS(STATUS),`
183			`.T0CKI_Pls(T0CKI_Pls),`
184			`.WDTClr(WDTClr),`
185			`.WDT(WDT),`
186			`.WDT_TC(WDT_TC),`
187			`.WDT_TO(WDT_TO),`
188			`.PSCntr(PSCntr),`
189			`.PSC_Pls(PSC_Pls)`
190			`);`
191
192			`initial begin`
193			`// Initialize Inputs`
194			`POR = 1;`
195			`Clk = 1;`
196			`ClkEn = 1;`
197			`// IR = 0;`
198			`IO_DI = 0;`
199			`MCLR = 0;`
200			`T0CKI = 0;`
201			`WDTE = 1;`
202
203			`// Wait 100 ns for global reset to finish`
204			`#101;`
205
206			`POR = 0;`
207			`// ClkEn = 1;`
208
209			`#899;`
210
211			`end`
212
213			`always #5 Clk = ~Clk;`
214
215			`always @(posedge Clk)`
216			`begin`
217			`if(POR)`
218			`#1 ClkEn <= 0;`
219			`else`
220			`#1 ClkEn <= ~ClkEn;`
221			`end`
222
223			`// Test Program ROM`
224
225			`// always @(PC or POR)`
226			`always @(posedge Clk or posedge POR)`
227			`begin`
228			`if(POR)`
229			`ROM <= 12'b1010_0000_0000; // GOTO 0x000 ;; Reset Vector: Jump 0x000 (Start)`
230			`else`
231			`case(PC[11:0])`
232			`12'h000 : ROM <= #1 12'b0111_0110_0011; // BTFSS 0x03,3 ;; Test PD (STATUS.3), if set, not SLEEP restart`
233			`12'h001 : ROM <= #1 12'b1010_0011_0000; // GOTO 0x030 ;; SLEEP restart, continue test program`
234			`12'h002 : ROM <= #1 12'b1100_0000_0111; // MOVLW 0x07 ;; load OPTION`
235			`12'h003 : ROM <= #1 12'b0000_0000_0010; // OPTION`
236			`12'h004 : ROM <= #1 12'b0000_0100_0000; // CLRW ;; clear working register`
237			`12'h005 : ROM <= #1 12'b0000_0000_0101; // TRISA ;; load W into port control registers`
238			`12'h006 : ROM <= #1 12'b0000_0000_0110; // TRISB`
239			`12'h007 : ROM <= #1 12'b0000_0000_0111; // TRISC`
240			`12'h008 : ROM <= #1 12'b1010_0000_1010; // GOTO 0x00A ;; Test GOTO`
241			`12'h009 : ROM <= #1 12'b1100_1111_1111; // MOVLW 0xFF ;; instruction should be skipped`
242			`12'h00A : ROM <= #1 12'b1001_0000_1101; // CALL 0x0D ;; Test CALL`
243			`12'h00B : ROM <= #1 12'b0000_0010_0010; // MOVWF 0x02 ;; Test Computed GOTO, Load PCL with W`
244			`12'h00C : ROM <= #1 12'b0000_0000_0000; // NOP ;; No Operation`
245			`12'h00D : ROM <= #1 12'b1000_0000_1110; // RETLW 0x0E ;; Test RETLW, return 0x0E in W`
246			`12'h00E : ROM <= #1 12'b1100_0000_1001; // MOVLW 0x09 ;; starting RAM + 1`
247			`12'h00F : ROM <= #1 12'b0000_0010_0100; // MOVWF 0x04 ;; indirect address register (FSR)`
248			`//`
249			`12'h010 : ROM <= #1 12'b1100_0001_0111; // MOVLW 0x17 ;; internal RAM count - 1`
250			`12'h011 : ROM <= #1 12'b0000_0010_1000; // MOVWF 0x08 ;; loop counter`
251			`12'h012 : ROM <= #1 12'b0000_0100_0000; // CLRW ;; zero working register`
252			`12'h013 : ROM <= #1 12'b0000_0010_0000; // MOVWF 0x00 ;; clear RAM indirectly`
253			`12'h014 : ROM <= #1 12'b0010_1010_0100; // INCF 0x04,1 ;; increment FSR`
254			`12'h015 : ROM <= #1 12'b0010_1110_1000; // DECFSZ 0x08,1 ;; decrement loop counter`
255			`12'h016 : ROM <= #1 12'b1010_0001_0011; // GOTO 0x013 ;; loop until loop counter == 0`
256			`12'h017 : ROM <= #1 12'b1100_0000_1001; // MOVLW 0x09 ;; starting RAM + 1`
257			`12'h018 : ROM <= #1 12'b0000_0010_0100; // MOVWF 0x04 ;; reload FSR`
258			`12'h019 : ROM <= #1 12'b1100_1110_1001; // MOVLW 0xE9 ;; set loop counter to 256 - 23`
259			`12'h01A : ROM <= #1 12'b0000_0010_1000; // MOVWF 0x08`
260			`12'h01B : ROM <= #1 12'b0010_0000_0000; // MOVF 0x00,0 ;; read memory into W`
261			`12'h01C : ROM <= #1 12'b0011_1110_1000; // INCFSZ 0x08,1 ;; increment counter loop until 0`
262			`12'h01D : ROM <= #1 12'b1010_0001_1011; // GOTO 0x01B ;; loop`
263			`12'h01E : ROM <= #1 12'b0000_0000_0100; // CLRWDT ;; clear WDT`
264			`12'h01F : ROM <= #1 12'b0000_0110_1000; // CLRF 0x08 ;; Clear Memory Location 0x08`
265			`//`
266			`12'h020 : ROM <= #1 12'b0010_0110_1000; // DECF 0x08,1 ;; Decrement Memory Location 0x08`
267			`12'h021 : ROM <= #1 12'b0001_1100_1000; // ADDWF 0x08,0 ;; Add Memory Location 0x08 to W, Store in W`
268			`12'h022 : ROM <= #1 12'b0000_1010_1000; // SUBWF 0x08,1 ;; Subtract Memory Location 0x08`
269			`12'h023 : ROM <= #1 12'b0011_0110_1000; // RLF 0x08,1 ;; Rotate Memory Location 0x08`
270			`12'h024 : ROM <= #1 12'b0011_0010_1000; // RRF 0x08,1 ;; Rotate Memory Location`
271			`12'h025 : ROM <= #1 12'b1100_0110_1001; // MOVLW 0x69 ;; Load W with test pattern: W <= 0x69`
272			`12'h026 : ROM <= #1 12'b0000_0010_1000; // MOVWF 0x08 ;; Initialize Memory with test pattern`
273			`12'h027 : ROM <= #1 12'b0011_1010_1000; // SWAPF 0x08,1 ;; Test SWAPF: (0x08) <= 0x96`
274			`12'h028 : ROM <= #1 12'b0001_0010_1000; // IORWF 0x08,1 ;; Test IORWF: (0x08) <= 0x69 \| 0x96`
275			`12'h029 : ROM <= #1 12'b0001_0110_1000; // ANDWF 0x08,1 ;; Test ANDWF: (0x08) <= 0x69 & 0xFF`
276			`12'h02A : ROM <= #1 12'b0001_1010_1000; // XORWF 0x08,1 :: Test XORWF: (0x08) <= 0x69 ^ 0x69`
277			`12'h02B : ROM <= #1 12'b0010_0110_1000; // COMF 0x08 ;; Test COMF: (0x08) <= ~0x00`
278			`12'h02C : ROM <= #1 12'b1101_1001_0110; // IORLW 0x96 ;; Test IORLW: W <= 0x69 \| 0x96`
279			`12'h02D : ROM <= #1 12'b1110_0110_1001; // ANDLW 0x69 ;; Test ANDLW: W <= 0xFF & 0x69`
280			`12'h02E : ROM <= #1 12'b1111_0110_1001; // XORLW 0x69 ;; Test XORLW: W <= 0x69 ^ 0x69`
281			`12'h02F : ROM <= #1 12'b0000_0000_0011; // SLEEP ;; Stop Execution of test program: HALT`
282			`//`
283			`12'h030 : ROM <= #1 12'b0000_0000_0100; // CLRWDT ;; Detected SLEEP restart, Clr WDT to reset PD`
284			`12'h031 : ROM <= #1 12'b0110_0110_0011; // BTFSC 0x03,3 ;; Check STATUS.3, skip if ~PD clear`
285			`12'h032 : ROM <= #1 12'b1010_0011_0100; // GOTO 0x034 ;; ~PD is set, CLRWDT cleared PD`
286			`12'h033 : ROM <= #1 12'b1010_0011_0011; // GOTO 0x033 ;; ERROR: hold here on error`
287			`12'h034 : ROM <= #1 12'b1100_0001_0000; // MOVLW 0x10 ;; Load FSR with non-banked RAM address`
288			`12'h035 : ROM <= #1 12'b0000_0010_0100; // MOVWF 0x04 ;; Initialize FSR for Bit Processor Tests`
289			`12'h036 : ROM <= #1 12'b0000_0110_0000; // CLRF 0x00 ;; Clear non-banked RAM location using INDF`
290			`12'h037 : ROM <= #1 12'b0101_0000_0011; // BSF 0x03,0 ;; Set STATUS.0 (C) bit`
291			`12'h038 : ROM <= #1 12'b0100_0010_0011; // BCF 0x03,1 ;; Clear STATUS.1 (DC) bit`
292			`12'h039 : ROM <= #1 12'b0100_0100_0011; // BCF 0x03,2 ;; Clear STATUS.2 (Z) bit`
293			`12'h03A : ROM <= #1 12'b0010_0000_0011; // MOVF 0x03,0 ;; Load W with STATUS`
294			`12'h03B : ROM <= #1 12'b0011_0000_0000; // RRF 0x00,0 ;; Rotate Right RAM location: C <= 0, W <= 0x80`
295			`12'h03C : ROM <= #1 12'b0011_0110_0000; // RLF 0x00,0 ;; Rotate Left RAM location: C <= 0, (INDF) <= 0x00`
296			`12'h03D : ROM <= #1 12'b0000_0010_0000; // MOVWF 0x00 ;; Write result back to RAM: (INDF) <= 0x80`
297			`12'h03E : ROM <= #1 12'b0000_0010_0001; // MOVWF 0x01 ;; Write to TMR0, clear Prescaler`
298			`12'h03F : ROM <= #1 12'b1010_0100_0000; // GOTO 0x040 ;; Restart Program`
299			`//`
300			`12'h040 : ROM <= #1 12'b0000_0000_0100; // CLRWDT ;; Detected SLEEP restart, Clr WDT to reset PD`
301			`12'h041 : ROM <= #1 12'b1100_1010_1010; // MOVLW 0xAA ;; Load W with 0xAA`
302			`12'h042 : ROM <= #1 12'b0000_0010_0101; // MOVWF 0x05 ;; WE_PortA`
303			`12'h043 : ROM <= #1 12'b0000_0010_0110; // MOVWF 0x06 ;; WE_PortB`
304			`12'h044 : ROM <= #1 12'b0000_0010_0111; // MOVWF 0x07 ;; WE_PortC`
305			`12'h045 : ROM <= #1 12'b0010_0000_0101; // MOVF 0x05,0 ;; RE_PortA`
306			`12'h046 : ROM <= #1 12'b0010_0000_0110; // MOVF 0x06,0 ;; RE_PortB`
307			`12'h047 : ROM <= #1 12'b0010_0000_0111; // MOVF 0x07,0 ;; RE_PortC`
308			`12'h048 : ROM <= #1 12'b0010_0110_0101; // COMF 0x05 ;; Complement PortA`
309			`12'h049 : ROM <= #1 12'b0010_0110_0110; // COMF 0x06 ;; Complement PortB`
310			`12'h04A : ROM <= #1 12'b0010_0110_0111; // COMF 0x07 ;; Complement PortC`
311			`12'h04B : ROM <= #1 12'b0000_0110_0101; // CLRF 0x05 ;; Clear PortA`
312			`12'h04C : ROM <= #1 12'b0000_0110_0110; // CLRF 0x06 ;; Clear PortB`
313			`12'h04D : ROM <= #1 12'b0000_0110_0111; // CLRF 0x07 ;; Clear PortC`
314			`12'h04E : ROM <= #1 12'b0000_0100_0000; // CLRW ;; zero working register`
315			`12'h04F : ROM <= #1 12'b1010_0000_0000; // GOTO 0x000 ;; Restart Program`
316			`//`
317			`default : ROM <= #1 12'b1010_0000_0000; // GOTO 0x000 ;; Reset Vector: Jump 0x000 (Start)`
318			`endcase`
319			`end`
320
321			`endmodule`
322