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1 2 MichaelA
////////////////////////////////////////////////////////////////////////////////
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//
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//  Copyright 2007-2013 by Michael A. Morris, dba M. A. Morris & Associates
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//
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//  All rights reserved. The source code contained herein is publicly released
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//  under the terms and conditions of the GNU Lesser Public License. No part of
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//  this source code may be reproduced or transmitted in any form or by any
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//  means, electronic or mechanical, including photocopying, recording, or any
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//  information storage and retrieval system in violation of the license under
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//  which the source code is released.
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//
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//  The source code contained herein is free; it may be redistributed and/or
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//  modified in accordance with the terms of the GNU Lesser General Public
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//  License as published by the Free Software Foundation; either version 2.1 of
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//  the GNU Lesser General Public License, or any later version.
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//
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//  The source code contained herein is freely released WITHOUT ANY WARRANTY;
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//  without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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//  PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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//  more details.)
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//
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//  A copy of the GNU Lesser General Public License should have been received
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//  along with the source code contained herein; if not, a copy can be obtained
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//  by writing to:
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//
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//  Free Software Foundation, Inc.
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//  51 Franklin Street, Fifth Floor
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//  Boston, MA  02110-1301 USA
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//
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//  Further, no use of this source code is permitted in any form or means
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//  without inclusion of this banner prominently in any derived works.
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//
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//  Michael A. Morris
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//  Huntsville, AL
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:         M. A. Morris & Associates
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// Engineer:        Michael A. Morris
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// 
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// Create Date:     12:11:30 12/22/2007 
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// Design Name:     HAWK Interface FPGA, 4020-0420, U35
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// Module Name:     DPSFnmCE 
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// Project Name:    4020 HAWK ZAOM Upgrade
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// Target Devices:  XC2S150-5PQ208I
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// Tool versions:   ISE 8.2i 
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//
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// Description: This module implements a parameterized version of a distributed
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//              RAM synchronous FIFO. The address width, FIFO width and depth
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//              are all specified by parameters. Default parameters settings 
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//              describe a 16x16 FIFO with Full (FF), Empty (EF), and Half 
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//              Full (HF) flags. The module also outputs the count words in the
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//              FIFO.
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//
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// Dependencies:    None
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//
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// Revision History: 
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//
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//  0.01    07L22   MAM     File Created
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//
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//  0.10    08K05   MAM     Changed depth to a localparam based on addr
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//
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//  1.00    13G14   MAM     Converted to Verilog 2001 standard
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//
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// Additional Comments: 
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//
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////////////////////////////////////////////////////////////////////////////////
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module DPSFnmCE #(
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    parameter addr  = 4,                // Sets depth of the FIFO: 2**addr
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    parameter width = 16,               // Sets width of the FIFO
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    parameter init  = "DPSFnmRAM.coe"   // Initializes FIFO memory
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)(
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    input   Rst,
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    input   Clk,
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    input   WE,
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    input   RE,
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    input   [(width - 1):0] DI,
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    output  [(width - 1):0] DO,
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    output  FF,
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    output  EF,
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    output  HF,
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    output  [addr:0] Cnt
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);
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////////////////////////////////////////////////////////////////////////////////
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//
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//  Module Parameter List
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//
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localparam  depth = (2**addr);
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////////////////////////////////////////////////////////////////////////////////
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//
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//  Module Level Declarations
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//
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    reg     [(width - 1):0] RAM [(depth - 1):0];
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    reg     [ (addr - 1):0] A, DPRA;
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    reg     [ (addr - 1):0] WCnt;
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    reg     nEF, rFF;
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    wire    Wr, Rd, CE;
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////////////////////////////////////////////////////////////////////////////////
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//
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//  Implementation
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//
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//
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//  Combinatorial Control Signals
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//
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assign Wr = WE & ~FF;
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assign Rd = RE & ~EF;
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assign CE = Wr ^ Rd;
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//
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//  Write Address Counter
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//
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always @(posedge Clk)
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begin
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    if(Rst)
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        A <= #1 0;
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    else if(Wr)
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        A <= #1 A + 1;
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end
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//
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//  Read Address Counter
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//
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always @(posedge Clk)
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begin
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    if(Rst)
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       DPRA <= #1 0;
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    else if(Rd)
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        DPRA <= #1 DPRA + 1;
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end
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//
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//   Word Counter
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//
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always @(posedge Clk)
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begin
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    if(Rst)
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        WCnt <= #1 0;
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    else if(Wr & ~Rd)
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        WCnt <= #1 WCnt + 1;
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    else if(Rd & ~Wr)
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        WCnt <= #1 WCnt - 1;
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end
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//
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//  External Word Count
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//
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assign Cnt = {FF, WCnt};
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//
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//  Empty Flag Register (Active Low)
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//
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always @(posedge Clk)
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begin
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    if(Rst)
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        nEF <= #1 0;
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    else if(CE)
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        nEF <= #1 ~(RE & (Cnt == 1));
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end
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assign EF = ~nEF;
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//
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//  Full Flag Register
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//
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always @(posedge Clk)
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begin
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    if(Rst)
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        rFF <= #1 0;
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    else if(CE)
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        rFF <= #1 (WE & (&WCnt));
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end
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assign FF = rFF;
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//
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//  Half-Full Flag
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//
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assign HF = Cnt[addr] | Cnt[(addr - 1)];
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//
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//  Dual-Port Synchronous RAM
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//
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initial
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  $readmemh(init, RAM, 0, (depth - 1));
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always @(posedge Clk)
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begin
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    if(Wr)
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        RAM[A] <= #1 DI;    // Synchronous Write
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end
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assign DO = RAM[DPRA];      // Asynchronous Read
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endmodule
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