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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright 2013 by Michael A. Morris, dba M. A. Morris & Associates
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//
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// All rights reserved. The source code contained herein is publicly released
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// under the terms and conditions of the GNU Lesser Public License. No part of
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// this source code may be reproduced or transmitted in any form or by any
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// means, electronic or mechanical, including photocopying, recording, or any
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// information storage and retrieval system in violation of the license under
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// which the source code is released.
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//
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// The source code contained herein is free; it may be redistributed and/or
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// modified in accordance with the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either version 2.1 of
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// the GNU Lesser General Public License, or any later version.
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//
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// The source code contained herein is freely released WITHOUT ANY WARRANTY;
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// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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// more details.)
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//
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// A copy of the GNU Lesser General Public License should have been received
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// along with the source code contained herein; if not, a copy can be obtained
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// by writing to:
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//
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// Free Software Foundation, Inc.
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// 51 Franklin Street, Fifth Floor
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// Boston, MA 02110-1301 USA
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//
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// Further, no use of this source code is permitted in any form or means
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// without inclusion of this banner prominently in any derived works.
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//
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// Michael A. Morris
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// Huntsville, AL
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company: M. A. Morris & Associates
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// Engineer: Michael A. Morris
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//
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// Create Date: 20:13:40 07/06/2013
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// Design Name: M16C5x Microcontroller based on PIC16C5x-compatible core
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// Module Name: M16C5x_UART.v
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// Project Name: M16C5x
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// Target Devices: SRAM-based FPGAs
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// Tool versions: Xilinx ISE 10.1i SP3
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//
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// Description:
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//
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// This module implements a UART for use with the M16C5x soft-core processor.
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// The module is based on existing modules developed for use with the NXP ARM
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// LPC213x/LPC214x processor's Synchronous Serial Peripheral interface. A 16-
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// bit frame size is used. The SSPx_Slv module is an SSP-compatible serial
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// slave I/F that can be connected to an SPI Master interface. The SSPx_Slv
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// controls the synchronous serial interface transactions to/from the SSP_UART
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// which is attached. Additional modules can be attached to the SSPx_Slv, but
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// select logic would need to be incorporated to select the additional modules
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// based on the RA, register address, control field. The SSP_UART attached
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// requires 4 addresses, and RA has a range from 0 to 7, i.e. 3 bits.
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//
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// The UART and its SSP interface is optimized to transfer 4 control signals
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// and 12 data bits. Standard MSB first shifting is expected by the SSPx_Slv
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// module. This allows on the fly decoding of the 3 address bits and the WnR
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// write control signal.
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//
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// The 12-bit data format, more fully described in the headers of the SSPx_Slv
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// and SSP_UART modules, allows efficient control of the UART over a serial
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// link. On every 16-bit serial transfer, the UART provides status information
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// regarding the UART's transmitter and UART's receiver. This allows the pro-
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// grammer access to critical status information with a minimal number of
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// transfers. Transmit and Receive FIFOs are part of the implementation pro-
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// vided, and these elements provide buffering which further reduces the work-
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// load on the processor to which the SSP_UART is attached.
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//
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// Dependencies: SSPx_Slv.v
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// SSP_UART.v
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// re1ce.v
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// DPSFmnCE.v
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// UART_BRG.v
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// UART_TXSM.v
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// UART_RXSM.v
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// UART_RTO.v
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// UART_INT.v
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// redet.v
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//
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// Revision:
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//
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// 1.00 13G06 MAM File Created
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//
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// 1.00 13G14 MAM Improved parameterization. Added/pulled parameters
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// to allow all relevant options to be set through the
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// instantiation interface.
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//
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module M16C5x_UART #(
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// SSP_UART Default BRR Settings Parameters
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parameter pPS_Default = 4'h1, // see baud rate tables SSP_UART
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parameter pDiv_Default = 8'hEF, // see baud rate tables SSP_UART
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// SSP_UART Default Receive Time Out Character Delay Count
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parameter pRTOChrDlyCnt = 3,
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// SSP_UART FIFO Configuration Parameters
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parameter pTF_Depth = 0, // Tx FIFO Depth: 2**(TF_Depth + 4)
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parameter pRF_Depth = 3, // Rx FIFO Depth: 2**(RF_Depth + 4)
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parameter pTF_Init = "Src/UART_TF.coe", // Tx FIFO Memory Initialization
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parameter pRF_Init = "Src/UART_RF.coe" // Rx FIFO Memory Initialization
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)(
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input Rst, // System Reset
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input Clk_UART, // UART Clock - expected to be 48 MHz
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// SPI Mode 0/3 Interface
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input SSEL, // Slave Select
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input SCK, // Serial Shift Clock
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input MOSI, // Serial Data Input: Master Out/Slave In
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output MISO, // Serial Data Output: Master In/Slave Out
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// UART External Interface
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output TxD, // Transmit Data
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output RTS, // Request to Send
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input RxD, // Receive Data
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input CTS, // Clear to Send
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output DE, // Drive Enable for RS-485 Modes
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output IRQ // Interrupt Request
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);
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////////////////////////////////////////////////////////////////////////////////
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//
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// Declarations
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//
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wire [2:0] RA;
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wire WnR;
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wire En;
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wire EOC;
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wire [11:0] DI;
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wire [11:0] DO;
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wire TxD_232;
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wire TxD_485;
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////////////////////////////////////////////////////////////////////////////////
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//
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// Implementation
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//
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// Instatiate a 16-bit Synchronous Serial Peripheral Slave Interface Controller
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SSPx_Slv SSP_Slv (
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.Rst(Rst),
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.SSEL(SSEL),
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.SCK(SCK),
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.MOSI(MOSI),
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.MISO(MISO),
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.RA(RA),
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.WnR(WnR),
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.En(En),
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.EOC(EOC),
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.DI(DI),
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.DO(DO),
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.BC()
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);
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// Instantiate UART compatible with 16-bit SSP Slave Interface Controller
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SSP_UART #(
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.pPS_Default(pPS_Default),
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.pDiv_Default(pDiv_Default),
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.pRTOChrDlyCnt(pRTOChrDlyCnt),
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.pTF_Depth(pTF_Depth),
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.pRF_Depth(pRF_Depth),
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.pTF_Init(pTF_Init),
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.pRF_Init(pRF_Init)
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) UART (
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.Rst(Rst),
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.Clk(Clk_UART),
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.SSP_SSEL(SSEL),
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.SSP_SCK(SCK),
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.SSP_RA(RA),
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.SSP_WnR(WnR),
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.SSP_En(En),
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.SSP_EOC(EOC),
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.SSP_DI(DI),
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.SSP_DO(DO),
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.TxD_232(TxD_232),
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.RxD_232(RxD),
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.xRTS(RTS),
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.xCTS(CTS),
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.TxD_485(TxD_485),
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.RxD_485(RxD),
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.xDE(DE),
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.IRQ(IRQ),
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.TxIdle(),
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.RxIdle()
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);
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assign TxD = TxD_232 & TxD_485;
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endmodule
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