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////////////////////////////////////////////////////////////////////////////////
//
//  Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates
//
//  All rights reserved. The source code contained herein is publicly released
//  under the terms and conditions of the GNU Lesser Public License. No part of
//  this source code may be reproduced or transmitted in any form or by any
//  means, electronic or mechanical, including photocopying, recording, or any
//  information storage and retrieval system in violation of the license under
//  which the source code is released.
//
//  The source code contained herein is free; it may be redistributed and/or
//  modified in accordance with the terms of the GNU Lesser General Public
//  License as published by the Free Software Foundation; either version 2.1 of
//  the GNU Lesser General Public License, or any later version.
//
//  The source code contained herein is freely released WITHOUT ANY WARRANTY;
//  without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
//  PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
//  more details.)
//
//  A copy of the GNU Lesser General Public License should have been received
//  along with the source code contained herein; if not, a copy can be obtained
//  by writing to:
//
//  Free Software Foundation, Inc.
//  51 Franklin Street, Fifth Floor
//  Boston, MA  02110-1301 USA
//
//  Further, no use of this source code is permitted in any form or means
//  without inclusion of this banner prominently in any derived works.
//
//  Michael A. Morris
//  Huntsville, AL
//
////////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
///////////////////////////////////////////////////////////////////////////////
// Company:         M. A. Morris & Associates
// Engineer:        Michael A. Morris
//
// Create Date:     07:33 05/10/2008 
// Design Name:     Synchronous Serial Peripheral (SSP) Interface UART 
// Module Name:     ../VerilogCoponentsLib/SSP_UART/SSPx_Slv.v
// Project Name:    Verilog Components Library
// Target Devices:  XC3S50A-4VQG100I, XC3S20A-4VQG100I, XC3S700AN-4FFG484I
// Tool versions:   ISE 10.1i SP3 
//
// Description:
//
//  This module implements a full-duplex (Slave) SSP interface for 16-bit 
//  frames. In accordance to standard SPI practice, the module expects that
//  data is shifted into it MSB first. The first three bits are address bits,
//  the fourth bit is a command (WnR) bit which determines the operations to
//  be performed on the register, and the final twelve (12) bits are data bits.
//
// Dependencies:    None
//
// Revision History:
//
//  0.01    08E10   MAM     File Created
//
//  1.00    08E10   MAM     Initial Release
//
//  1.10    08G24   MAM     Modified the interface to operate with registered
//                          shift register data to eliminate transitions on
//                          MISO after risisng edge of SCK when input register
//                          written. Register RA[3:0] during fourth clock, and
//                          register DO[11:0] on falling edge of SCK after RA
//                          registered. This holds output data constant for the
//                          entire shift cycle.
//
//  1.11    11B01   MAM     Corrected #1 delay statement placement in register
//
//  2.00    11B06   MAM     Modified the interface to separate RA[3:1] and 
//                          RA[0] into RA[2:0] address port and a WnR command
//                          port. This makes the operation of the SSP/SPI I/F
//                          more clear.
//
//  2.10    13G06   MAM     Changed the asynchronous reset generated by ~SSEL.
//                          Previously, a number of internal circuits were 
//                          reset asynchronously on system reset, Rst, or ~SSEL.
//                          Added a FF, clocked on posedge SCK, that is asyn-
//                          chronously reset as before, but synchronously de-
//                          asserts on first rising edge of SCK. This signal,
//                          SSP_Rst, is used to asynchronously reset the same
//                          circuits as before: BC, EOC, and RDI. SPI Modes 0 or
//                          3 are still supported.
//
// Additional Comments: 
//
///////////////////////////////////////////////////////////////////////////////
 
module SSPx_Slv(
    input   Rst,            // System Reset
//
    input   SSEL,           // Slave Select
    input   SCK,            // Shift Clock
    input   MOSI,           // Master Out, Slave In: Serial Data In
    output  reg MISO,       // Master In, Slave Out: Serial Data Out
//
    output  reg [2:0] RA,   // SSP Register Address output
    output  reg WnR,        // SSP Command: 1 - Write, 0 - Read
    output  En,             // SSP Enable - asserted during field
    output  reg EOC,        // SSP End of Cycle - asserted on last bit of frame
    output  reg [11:0] DI,  // Input shift register output
    input   [11:0] DO,      // Output shift register input
//
    output  reg [3:0] BC    // Bit Count, 0 - MSB; 15 - LSB
);
 
///////////////////////////////////////////////////////////////////////////////    
//
//  Local Declarations
//
 
    reg     [15:1] RDI; // Serial Input Shift Register
    reg     [11:0] rDO; // output data register
 
    reg     SSP_Rst;
 
///////////////////////////////////////////////////////////////////////////////
//
//  Implementation
//
 
//  Module Reset - asynchronous because SCK not continuous
 
assign Rst_SSP = (Rst | ~SSEL);
 
always @(posedge SCK or posedge Rst_SSP)
begin
    if(Rst_SSP)
        SSP_Rst <= #1 ~0;
    else
        SSP_Rst <= #1  0;
end
 
//  Bit Counter, count from 0 to 15
//      Clock on negedge SCK to align MISO in bit cell
 
always @(negedge SCK or posedge SSP_Rst)
begin
    if(SSP_Rst)
        BC <= #1 4'd0;
    else
        BC <= #1 (BC + 1);
end
 
//  End-Of-Cycle, asserted during last bit of transfer (bit 15)
//      Clock on negedge SCK to center rising edge in bit cell
 
always @(negedge SCK or posedge SSP_Rst)
begin
    if(SSP_Rst)
        EOC <= #1 1'b0;
    else
        EOC <= #1 (BC == 14);
end
 
//  Generate SSP Enable, require four bits for internal addressing
 
assign En = BC[3] | BC[2];
 
//  Load MOSI into RDI using BC to select the active register
//      Use posedge SCK to sample in middle of bit cell
 
always @(posedge SCK or posedge SSP_Rst)
begin
    if(SSP_Rst)
        RDI <= #1 15'b0;
    else
        case(BC)
            4'b0000 : RDI[15] <= #1 MOSI;
            4'b0001 : RDI[14] <= #1 MOSI;
            4'b0010 : RDI[13] <= #1 MOSI;
            4'b0011 : RDI[12] <= #1 MOSI;
            4'b0100 : RDI[11] <= #1 MOSI;
            4'b0101 : RDI[10] <= #1 MOSI;
            4'b0110 : RDI[ 9] <= #1 MOSI;
            4'b0111 : RDI[ 8] <= #1 MOSI;
            4'b1000 : RDI[ 7] <= #1 MOSI;
            4'b1001 : RDI[ 6] <= #1 MOSI;
            4'b1010 : RDI[ 5] <= #1 MOSI;
            4'b1011 : RDI[ 4] <= #1 MOSI;
            4'b1100 : RDI[ 3] <= #1 MOSI;
            4'b1101 : RDI[ 2] <= #1 MOSI;
            4'b1110 : RDI[ 1] <= #1 MOSI;
            default : RDI <= #1 RDI;
        endcase
end
 
//  Assign RA, WnR, and DI bus from RDI and MOSI
 
always @(negedge SCK or posedge Rst)
begin
    if(Rst)
        RA <= #1 0;
    else if(BC == 2)
        RA <= #1 RDI[15:13];
end
 
always @(negedge SCK or posedge Rst)
begin
    if(Rst)
        WnR <= #1 0;
    else if(EOC)
        WnR <= #1 0;
    else if(BC == 3)
        WnR <= #1 RDI[12];
end
 
always @(*) DI <= {RDI[11:1], MOSI};
 
always @(negedge SCK or posedge Rst)
begin
    if(Rst)
        rDO <= #1 0;
    else if(BC == 3)
        rDO <= #1 DO;
end
 
// Generate MISO: multiplex MOSI and DO using En and BC
 
always @(*)
begin
    case(BC)
        4'b0000 :   MISO <= MOSI;
        4'b0001 :   MISO <= MOSI;
        4'b0010 :   MISO <= MOSI;
        4'b0011 :   MISO <= MOSI;
        4'b0100 :   MISO <= rDO[11];
        4'b0101 :   MISO <= rDO[10];
        4'b0110 :   MISO <= rDO[ 9];
        4'b0111 :   MISO <= rDO[ 8];
        4'b1000 :   MISO <= rDO[ 7];
        4'b1001 :   MISO <= rDO[ 6];
        4'b1010 :   MISO <= rDO[ 5];
        4'b1011 :   MISO <= rDO[ 4];
        4'b1100 :   MISO <= rDO[ 3];
        4'b1101 :   MISO <= rDO[ 2];
        4'b1110 :   MISO <= rDO[ 1];
        4'b1111 :   MISO <= rDO[ 0];
    endcase
end
 
endmodule

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Subversion Repositories m16c5x

[/] [m16c5x/] [trunk/] [RTL/] [Src/] [SSPx_Slv.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	MichaelA	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates`
4			`//`
5			`// All rights reserved. The source code contained herein is publicly released`
6			`// under the terms and conditions of the GNU Lesser Public License. No part of`
7			`// this source code may be reproduced or transmitted in any form or by any`
8			`// means, electronic or mechanical, including photocopying, recording, or any`
9			`// information storage and retrieval system in violation of the license under`
10			`// which the source code is released.`
11			`//`
12			`// The source code contained herein is free; it may be redistributed and/or`
13			`// modified in accordance with the terms of the GNU Lesser General Public`
14			`// License as published by the Free Software Foundation; either version 2.1 of`
15			`// the GNU Lesser General Public License, or any later version.`
16			`//`
17			`// The source code contained herein is freely released WITHOUT ANY WARRANTY;`
18			`// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A`
19			`// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for`
20			`// more details.)`
21			`//`
22			`// A copy of the GNU Lesser General Public License should have been received`
23			`// along with the source code contained herein; if not, a copy can be obtained`
24			`// by writing to:`
25			`//`
26			`// Free Software Foundation, Inc.`
27			`// 51 Franklin Street, Fifth Floor`
28			`// Boston, MA 02110-1301 USA`
29			`//`
30			`// Further, no use of this source code is permitted in any form or means`
31			`// without inclusion of this banner prominently in any derived works.`
32			`//`
33			`// Michael A. Morris`
34			`// Huntsville, AL`
35			`//`
36			`////////////////////////////////////////////////////////////////////////////////`
37
38			`timescale 1ns / 1ps
39
40			`///////////////////////////////////////////////////////////////////////////////`
41			`// Company: M. A. Morris & Associates`
42			`// Engineer: Michael A. Morris`
43			`//`
44			`// Create Date: 07:33 05/10/2008`
45			`// Design Name: Synchronous Serial Peripheral (SSP) Interface UART`
46			`// Module Name: ../VerilogCoponentsLib/SSP_UART/SSPx_Slv.v`
47			`// Project Name: Verilog Components Library`
48			`// Target Devices: XC3S50A-4VQG100I, XC3S20A-4VQG100I, XC3S700AN-4FFG484I`
49			`// Tool versions: ISE 10.1i SP3`
50			`//`
51			`// Description:`
52			`//`
53			`// This module implements a full-duplex (Slave) SSP interface for 16-bit`
54			`// frames. In accordance to standard SPI practice, the module expects that`
55			`// data is shifted into it MSB first. The first three bits are address bits,`
56			`// the fourth bit is a command (WnR) bit which determines the operations to`
57			`// be performed on the register, and the final twelve (12) bits are data bits.`
58			`//`
59			`// Dependencies: None`
60			`//`
61			`// Revision History:`
62			`//`
63			`// 0.01 08E10 MAM File Created`
64			`//`
65			`// 1.00 08E10 MAM Initial Release`
66			`//`
67			`// 1.10 08G24 MAM Modified the interface to operate with registered`
68			`// shift register data to eliminate transitions on`
69			`// MISO after risisng edge of SCK when input register`
70			`// written. Register RA[3:0] during fourth clock, and`
71			`// register DO[11:0] on falling edge of SCK after RA`
72			`// registered. This holds output data constant for the`
73			`// entire shift cycle.`
74			`//`
75			`// 1.11 11B01 MAM Corrected #1 delay statement placement in register`
76			`//`
77			`// 2.00 11B06 MAM Modified the interface to separate RA[3:1] and`
78			`// RA[0] into RA[2:0] address port and a WnR command`
79			`// port. This makes the operation of the SSP/SPI I/F`
80			`// more clear.`
81			`//`
82			`// 2.10 13G06 MAM Changed the asynchronous reset generated by ~SSEL.`
83			`// Previously, a number of internal circuits were`
84			`// reset asynchronously on system reset, Rst, or ~SSEL.`
85			`// Added a FF, clocked on posedge SCK, that is asyn-`
86			`// chronously reset as before, but synchronously de-`
87			`// asserts on first rising edge of SCK. This signal,`
88			`// SSP_Rst, is used to asynchronously reset the same`
89			`// circuits as before: BC, EOC, and RDI. SPI Modes 0 or`
90			`// 3 are still supported.`
91			`//`
92			`// Additional Comments:`
93			`//`
94			`///////////////////////////////////////////////////////////////////////////////`
95
96			`module SSPx_Slv(`
97			`input Rst, // System Reset`
98			`//`
99			`input SSEL, // Slave Select`
100			`input SCK, // Shift Clock`
101			`input MOSI, // Master Out, Slave In: Serial Data In`
102			`output reg MISO, // Master In, Slave Out: Serial Data Out`
103			`//`
104			`output reg [2:0] RA, // SSP Register Address output`
105			`output reg WnR, // SSP Command: 1 - Write, 0 - Read`
106			`output En, // SSP Enable - asserted during field`
107			`output reg EOC, // SSP End of Cycle - asserted on last bit of frame`
108			`output reg [11:0] DI, // Input shift register output`
109			`input [11:0] DO, // Output shift register input`
110			`//`
111			`output reg [3:0] BC // Bit Count, 0 - MSB; 15 - LSB`
112			`);`
113
114			`///////////////////////////////////////////////////////////////////////////////`
115			`//`
116			`// Local Declarations`
117			`//`
118
119			`reg [15:1] RDI; // Serial Input Shift Register`
120			`reg [11:0] rDO; // output data register`
121
122			`reg SSP_Rst;`
123
124			`///////////////////////////////////////////////////////////////////////////////`
125			`//`
126			`// Implementation`
127			`//`
128
129			`// Module Reset - asynchronous because SCK not continuous`
130
131			`assign Rst_SSP = (Rst \| ~SSEL);`
132
133			`always @(posedge SCK or posedge Rst_SSP)`
134			`begin`
135			`if(Rst_SSP)`
136			`SSP_Rst <= #1 ~0;`
137			`else`
138			`SSP_Rst <= #1 0;`
139			`end`
140
141			`// Bit Counter, count from 0 to 15`
142			`// Clock on negedge SCK to align MISO in bit cell`
143
144			`always @(negedge SCK or posedge SSP_Rst)`
145			`begin`
146			`if(SSP_Rst)`
147			`BC <= #1 4'd0;`
148			`else`
149			`BC <= #1 (BC + 1);`
150			`end`
151
152			`// End-Of-Cycle, asserted during last bit of transfer (bit 15)`
153			`// Clock on negedge SCK to center rising edge in bit cell`
154
155			`always @(negedge SCK or posedge SSP_Rst)`
156			`begin`
157			`if(SSP_Rst)`
158			`EOC <= #1 1'b0;`
159			`else`
160			`EOC <= #1 (BC == 14);`
161			`end`
162
163			`// Generate SSP Enable, require four bits for internal addressing`
164
165			`assign En = BC[3] \| BC[2];`
166
167			`// Load MOSI into RDI using BC to select the active register`
168			`// Use posedge SCK to sample in middle of bit cell`
169
170			`always @(posedge SCK or posedge SSP_Rst)`
171			`begin`
172			`if(SSP_Rst)`
173			`RDI <= #1 15'b0;`
174			`else`
175			`case(BC)`
176			`4'b0000 : RDI[15] <= #1 MOSI;`
177			`4'b0001 : RDI[14] <= #1 MOSI;`
178			`4'b0010 : RDI[13] <= #1 MOSI;`
179			`4'b0011 : RDI[12] <= #1 MOSI;`
180			`4'b0100 : RDI[11] <= #1 MOSI;`
181			`4'b0101 : RDI[10] <= #1 MOSI;`
182			`4'b0110 : RDI[ 9] <= #1 MOSI;`
183			`4'b0111 : RDI[ 8] <= #1 MOSI;`
184			`4'b1000 : RDI[ 7] <= #1 MOSI;`
185			`4'b1001 : RDI[ 6] <= #1 MOSI;`
186			`4'b1010 : RDI[ 5] <= #1 MOSI;`
187			`4'b1011 : RDI[ 4] <= #1 MOSI;`
188			`4'b1100 : RDI[ 3] <= #1 MOSI;`
189			`4'b1101 : RDI[ 2] <= #1 MOSI;`
190			`4'b1110 : RDI[ 1] <= #1 MOSI;`
191			`default : RDI <= #1 RDI;`
192			`endcase`
193			`end`
194
195			`// Assign RA, WnR, and DI bus from RDI and MOSI`
196
197			`always @(negedge SCK or posedge Rst)`
198			`begin`
199			`if(Rst)`
200			`RA <= #1 0;`
201			`else if(BC == 2)`
202			`RA <= #1 RDI[15:13];`
203			`end`
204
205			`always @(negedge SCK or posedge Rst)`
206			`begin`
207			`if(Rst)`
208			`WnR <= #1 0;`
209			`else if(EOC)`
210			`WnR <= #1 0;`
211			`else if(BC == 3)`
212			`WnR <= #1 RDI[12];`
213			`end`
214
215			`always @(*) DI <= {RDI[11:1], MOSI};`
216
217			`always @(negedge SCK or posedge Rst)`
218			`begin`
219			`if(Rst)`
220			`rDO <= #1 0;`
221			`else if(BC == 3)`
222			`rDO <= #1 DO;`
223			`end`
224
225			`// Generate MISO: multiplex MOSI and DO using En and BC`
226
227			`always @(*)`
228			`begin`
229			`case(BC)`
230			`4'b0000 : MISO <= MOSI;`
231			`4'b0001 : MISO <= MOSI;`
232			`4'b0010 : MISO <= MOSI;`
233			`4'b0011 : MISO <= MOSI;`
234			`4'b0100 : MISO <= rDO[11];`
235			`4'b0101 : MISO <= rDO[10];`
236			`4'b0110 : MISO <= rDO[ 9];`
237			`4'b0111 : MISO <= rDO[ 8];`
238			`4'b1000 : MISO <= rDO[ 7];`
239			`4'b1001 : MISO <= rDO[ 6];`
240			`4'b1010 : MISO <= rDO[ 5];`
241			`4'b1011 : MISO <= rDO[ 4];`
242			`4'b1100 : MISO <= rDO[ 3];`
243			`4'b1101 : MISO <= rDO[ 2];`
244			`4'b1110 : MISO <= rDO[ 1];`
245			`4'b1111 : MISO <= rDO[ 0];`
246			`endcase`
247			`end`
248
249			`endmodule`