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1 2 MichaelA
////////////////////////////////////////////////////////////////////////////////
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//
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//  Copyright 2006-2013 by Michael A. Morris, dba M. A. Morris & Associates
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//
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//  All rights reserved. The source code contained herein is publicly released
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//  under the terms and conditions of the GNU Lesser Public License. No part of
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//  this source code may be reproduced or transmitted in any form or by any
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//  means, electronic or mechanical, including photocopying, recording, or any
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//  information storage and retrieval system in violation of the license under
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//  which the source code is released.
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//
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//  The source code contained herein is free; it may be redistributed and/or
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//  modified in accordance with the terms of the GNU Lesser General Public
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//  License as published by the Free Software Foundation; either version 2.1 of
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//  the GNU Lesser General Public License, or any later version.
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//
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//  The source code contained herein is freely released WITHOUT ANY WARRANTY;
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//  without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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//  PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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//  more details.)
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//
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//  A copy of the GNU Lesser General Public License should have been received
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//  along with the source code contained herein; if not, a copy can be obtained
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//  by writing to:
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//
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//  Free Software Foundation, Inc.
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//  51 Franklin Street, Fifth Floor
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//  Boston, MA  02110-1301 USA
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//
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//  Further, no use of this source code is permitted in any form or means
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//  without inclusion of this banner prominently in any derived works.
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//
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//  Michael A. Morris
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//  Huntsville, AL
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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///////////////////////////////////////////////////////////////////////////////
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// Company:         Alpha Beta Technologies, Inc.
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// Engineer:        Michael A. Morris 
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// 
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// Create Date:     11:45:29 12/31/2006 
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// Design Name:     USB MBP HDL 
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// Module Name:     re1ce 
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// Project Name:    USBMBP_HDL
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// Target Devices:  XC2S15-5TQ144
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// Tool versions:   ISE Webpack 8.2i
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// Description:     Multi-stage synchronizer with rising edge detection
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//
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// Dependencies:    None
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//
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// Revision History:
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//
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//  0.01    06L31   MAM     File Created
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//
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//  1.00    13G06   MAM     Added initial values for the sync FFs
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//
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// Additional Comments: 
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//
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///////////////////////////////////////////////////////////////////////////////
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module re1ce(den, din, clk, rst, trg, pls);
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///////////////////////////////////////////////////////////////////////////////
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//
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//  Module Port Declarations
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//
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input   den;
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input   din;
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input   clk;
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input   rst;
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output  trg;
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output  pls;
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///////////////////////////////////////////////////////////////////////////////
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//
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//  Module Level Declarations
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//
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reg     QIn;
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reg     [2:0] QSync;
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wire    Rst_QIn;
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///////////////////////////////////////////////////////////////////////////////
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//
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//  Implementation
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//
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assign Rst_QIn = (rst | pls);
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always @(posedge din or posedge Rst_QIn) begin
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    if(Rst_QIn)
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        #1 QIn <= 1'b0;
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    else if(den)
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        #1 QIn <= den;
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end
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assign trg = QIn;
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always @(posedge clk or posedge rst) begin
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    if(rst)
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        #1 QSync <= 3'b0;
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    else
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        #1 QSync <= {QSync[0] & ~QSync[1], QSync[0], QIn};
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end
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assign pls = QSync[2];
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endmodule

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