Subversion Repositories m1_core

# Synthesis script for dc_shell (Tcl mode)

# Analyze

set search_path [concat [list /home/fabrizio/m1_core/hdl/rtl/m1_cpu] $search_path]

analyze -format verilog ~/m1_core/hdl/rtl/m1_cpu/m1_alu.v

analyze -format verilog ~/m1_core/hdl/rtl/m1_cpu/m1_cpu.v

# Elaborate

elaborate m1_cpu

link

uniquify

check_design

# Constraints

create_clock -name "sys_clock_i" -period 2.0 -waveform {0 1.0} [get_ports "sys_clock_i"]

set_dont_touch_network [get_clocks "sys_clock_i"]

set_input_delay 1.25 -max -rise -clock "sys_clock_i" [get_ports "sys_reset_i"]

set_input_delay 1.25 -max -fall -clock "sys_clock_i" [get_ports "sys_reset_i"]

set_output_delay 1.25 -clock sys_clock_i -max -rise [all_outputs]

set_output_delay 1.25 -clock sys_clock_i -max -fall [all_outputs]

set_wire_load_mode "enclosed"

# Compile

compile -map_effort low

write -format db -hierarchy -output m1_cpu.db

write -format verilog -hierarchy -output m1_cpu.v

# Report

report_area > report_area.txt

report_timing > report_timing.txt

report_constraint -all_violators > report_constraint.txt

quit