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[/] [m1_core/] [tags/] [first/] [hdl/] [rtl/] [m1_core/] [m1_core.v] - Blame information for rev 64

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/*
 * Simply RISC M1 Core Top-Level
 */
 
module m1_core (
    sys_clock_i, sys_reset_i, sys_irq_i
  );
 
  input sys_clock_i, sys_reset_i;
  input[31:0] sys_irq_i;
  wire[31:0] imem_addr, imem_data, dmem_addr, dmem_rdata, dmem_wdata;
  wire imem_read, imem_busy, dmem_read, dmem_write, dmem_busy;
  wire[3:0] dmem_sel;
 
  m1_cpu cpu_0(sys_clock_i, sys_reset_i, sys_irq_i,
    imem_addr, imem_data, imem_read, imem_busy,
    dmem_addr, dmem_rdata, dmem_wdata, dmem_read, dmem_write, dmem_busy , dmem_sel
  );
 
  m1_mmu mmu_0(sys_clock_i, sys_reset_i,
    imem_addr, imem_data, imem_read, imem_busy,
    dmem_addr, dmem_rdata, dmem_wdata, dmem_read, dmem_write, dmem_busy , dmem_sel
  );
 
endmodule

Line No.	Rev	Author	Line
1	2	fafa1971	`/*`
2			`* Simply RISC M1 Core Top-Level`
3			`*/`
4
5			`module m1_core (`
6			`sys_clock_i, sys_reset_i, sys_irq_i`
7			`);`
8
9			`input sys_clock_i, sys_reset_i;`
10			`input[31:0] sys_irq_i;`
11			`wire[31:0] imem_addr, imem_data, dmem_addr, dmem_rdata, dmem_wdata;`
12			`wire imem_read, imem_busy, dmem_read, dmem_write, dmem_busy;`
13			`wire[3:0] dmem_sel;`
14
15			`m1_cpu cpu_0(sys_clock_i, sys_reset_i, sys_irq_i,`
16			`imem_addr, imem_data, imem_read, imem_busy,`
17			`dmem_addr, dmem_rdata, dmem_wdata, dmem_read, dmem_write, dmem_busy , dmem_sel`
18			`);`
19
20			`m1_mmu mmu_0(sys_clock_i, sys_reset_i,`
21			`imem_addr, imem_data, imem_read, imem_busy,`
22			`dmem_addr, dmem_rdata, dmem_wdata, dmem_read, dmem_write, dmem_busy , dmem_sel`
23			`);`
24
25			`endmodule`

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[/] [m1_core/] [tags/] [first/] [hdl/] [rtl/] [m1_core/] [m1_core.v] - Blame information for rev 64