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fafa1971 |
/*
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* Simply RISC M1 ALU & Multiplier & Divider
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*
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* Three modules (alu, multiplier, divider) with Alternating Bit Protocol (ABP) interface.
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*/
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`include "m1_defs.h"
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// Combinational ALU with 32-bit operands
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module alu(a_i, b_i, func_i, signed_i, result_o, carry_o);
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// I/O Ports
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input[31:0] a_i, b_i; // Operands
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input[4:0] func_i; // Function to be performed
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input signed_i; // Operation is signed
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output[31:0] result_o; // Result
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output carry_o; // Carry bit
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// Registers
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reg[31:0] result_o; // Registered output of result
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// ALU Logic
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always @(a_i or b_i or func_i or signed_i) begin
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case(func_i)
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`ALU_OP_SLL: result_o = a_i << b_i;
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`ALU_OP_SRL: result_o = a_i >> b_i;
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`ALU_OP_SRA: result_o = {{32{a_i[31]}}, a_i } >> b_i;
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`ALU_OP_ADD: result_o = a_i + b_i;
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`ALU_OP_SUB: result_o = a_i - b_i;
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`ALU_OP_AND: result_o = a_i & b_i;
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`ALU_OP_OR: result_o = a_i | b_i;
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`ALU_OP_XOR: result_o = a_i ^ b_i;
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// `ALU_OP_NOR: result_o = a_i ~| b_i;
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`ALU_OP_SEQ: result_o = (a_i == b_i) ? 32'b1 : 32'b0;
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`ALU_OP_SNE: result_o = (a_i != b_i) ? 32'b1 : 32'b0;
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`ALU_OP_SLT: if(signed_i) result_o = ({~a_i[31],a_i[30:0]} < {~b_i[31],b_i[30:0]}) ? 32'b1 : 32'b0;
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else result_o = a_i < b_i;
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`ALU_OP_SLE: if ((a_i[31] == 1'b1) || (a_i == 32'b0)) result_o = 32'b1;
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else result_o = 32'b0;
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`ALU_OP_SGT: if ((a_i[31] == 1'b0) && (a_i != 32'b0)) result_o = 32'b1;
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else result_o = 32'b0;
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`ALU_OP_SGE: if(signed_i) result_o = ({~a_i[31],a_i[30:0]} >= {~b_i[31],b_i[30:0]}) ? 32'b1 : 32'b0;
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else result_o = a_i >= b_i;
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endcase
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end
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endmodule
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// 32-bit * 32-bit Integer Multiplier (this version is not optimized and always takes 32 cycles)
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module multiplier(sys_reset_i, sys_clock_i, a_i, b_i, signed_i, product_o, abp_req_i, abp_ack_o);
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// I/O ports
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input sys_reset_i; // System Reset
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input sys_clock_i; // System Clock
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input[31:0] a_i, b_i; // Operands of multiplication
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input signed_i; // If multiplication is signed
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output[63:0] product_o; // Product of multiplication
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input abp_req_i; // ABP Request
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output abp_ack_o; // ABP Acknowledgement
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// Registers
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reg[63:0] a_latched; // Latched 'a' input
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reg[31:0] b_latched; // Latched 'b' input
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reg[63:0] product_o; // Registered output of result
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reg[63:0] product_tmp; // Temporary result
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reg abp_ack_o; // Registered output of ABP Ack
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reg negative_output; // If output is negative
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reg[5:0] count; // Downward counter (32->0)
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reg abp_last; // Level of last ABP request
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// Sequential logic
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always @(posedge sys_clock_i) begin
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// Initialization
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if(sys_reset_i) begin
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product_o = 0;
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abp_ack_o = 0;
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negative_output = 0;
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count = 6'd0;
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abp_last = 0;
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// New request
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end else if(abp_req_i!=abp_last) begin
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abp_last = abp_req_i; // Latch level of ABP request
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count = 6'd32; // Start counter
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product_tmp = 0; // Initialize result
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a_latched = (!signed_i || !a_i[31]) ? { 32'd0, a_i } : { 32'd0, (~a_i+1'b1) };
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b_latched = (!signed_i || !b_i[31]) ? b_i : (~b_i + 1'b1);
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negative_output = signed_i && (a_i[31] ^ b_i[31]);
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product_o = (!negative_output) ? product_tmp : (~product_tmp+1); // Degugging only
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// Calculating
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end else if(count>0) begin
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count = count-1;
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if(b_latched[0]==1) product_tmp = product_tmp + a_latched;
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a_latched = a_latched << 1;
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b_latched = b_latched >> 1;
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product_o = (!negative_output) ? product_tmp : (~product_tmp + 1); // Debugging only
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// Return the result
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end else if(count==0) begin
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abp_ack_o = abp_req_i; // Return the result
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product_o = (!negative_output) ? product_tmp : (~product_tmp + 1);
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end
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end
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endmodule
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// 32-bit / 32-bit Integer Divider (this version is not optimized and always takes 32 cycles)
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module divider(sys_reset_i, sys_clock_i, a_i, b_i, signed_i, quotient_o, remainder_o, abp_req_i, abp_ack_o);
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// I/O ports
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input sys_reset_i; // System Reset
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input sys_clock_i; // System Clock
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input[31:0] a_i, b_i; // Operands of division
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input signed_i; // If division is signed
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output[31:0] quotient_o; // Quotient of division
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output[31:0] remainder_o; // Remainder of division
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input abp_req_i; // ABP Request
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output abp_ack_o; // ABP Acknowledgement
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// Registers
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reg[63:0] a_latched; // Latched 'a' input
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reg[63:0] b_latched; // Latched 'b' input
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reg[31:0] quotient_o; // Registered output of result
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reg[31:0] quotient_tmp; // Temporary result
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reg[31:0] remainder_o; // Registered output of result
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reg[31:0] remainder_tmp; // Temporary result
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reg abp_ack_o; // Registered output of ABP Ack
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reg negative_output; // If output is negative
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reg[5:0] count; // Downward counter (32->0)
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reg abp_last; // Level of last ABP request
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reg[63:0] diff; // Difference
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// Sequential logic
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always @(posedge sys_clock_i) begin
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// Initialization
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if(sys_reset_i) begin
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quotient_o = 0;
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remainder_o = 0;
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abp_ack_o = 0;
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negative_output = 0;
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count = 6'd0;
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abp_last = 0;
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// New request
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end else if(abp_req_i!=abp_last) begin
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abp_last = abp_req_i; // Latch level of ABP request
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count = 6'd32; // Start counter
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quotient_tmp = 0; // Initialize result
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remainder_tmp = 0; // Initialize result
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a_latched = (!signed_i || !a_i[31]) ? { 32'd0, a_i } : { 32'd0, (~a_i + 1'b1) };
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b_latched = (!signed_i || !b_i[31]) ? { 1'b0, b_i, 31'd0 } : { 1'b0, ~b_i + 1'b1, 31'd0 };
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negative_output = signed_i && (a_i[31] ^ b_i[31]);
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quotient_o = (!negative_output) ? quotient_tmp : (~quotient_tmp+1); // Debugging only
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remainder_o = (!negative_output) ? a_latched[31:0] : (~a_latched[31:0]+1); // Debugging only
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// Calculating
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end else if(count>0) begin
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count = count-1;
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diff = a_latched-b_latched;
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quotient_tmp = quotient_tmp << 1;
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if(!diff[63]) begin
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a_latched = diff;
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quotient_tmp[0] = 1;
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end
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b_latched = b_latched >> 1;
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quotient_o = (!negative_output) ? quotient_tmp : (~quotient_tmp+1); // Debugging only
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remainder_o = (!negative_output) ? a_latched[31:0] : (~a_latched[31:0]+1); // Debugging only
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// Return the result
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end else if(count==0) begin
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abp_ack_o = abp_req_i; // Return the result
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quotient_o = (!negative_output) ? quotient_tmp : (~quotient_tmp+1);
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remainder_o = (!negative_output) ? a_latched[31:0] : (~a_latched[31:0]+1);
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end
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end
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endmodule
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/*
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// Testbench
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module testbench;
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reg sys_clock_i, sys_reset_i;
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reg[31:0] a_i,b_i;
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wire[63:0] product_o;
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wire[31:0] quotient_o, remainder_o;
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reg signed_i,abp_req_i_mul,abp_req_i_div;
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wire abp_ack_o_mul,abp_ack_o_div;
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multiplier mul_0(sys_reset_i, sys_clock_i, a_i, b_i, signed_i, product_o, abp_req_i_mul, abp_ack_o_mul);
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divider div_0(sys_reset_i, sys_clock_i, a_i, b_i, signed_i, quotient_o, remainder_o, abp_req_i_div, abp_ack_o_div);
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initial begin
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$dumpfile("trace.vcd");
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$dumpvars();
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sys_clock_i = 0;
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sys_reset_i = 1;
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abp_req_i_mul = 0;
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abp_req_i_div = 0;
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#100
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sys_reset_i = 0;
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#100
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a_i = 17;
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b_i = 3;
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signed_i = 0;
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abp_req_i_mul = !abp_req_i_mul;
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#100
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$display("Try unsigned 17*3: Product is %d", product_o);
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a_i = 20;
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b_i = 4;
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signed_i = 1;
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abp_req_i_div = !abp_req_i_div;
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#100
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$display("Try signed 20/4: Quotient is %d and remainder is %d", quotient_o, remainder_o);
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a_i = -7;
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b_i = 3;
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signed_i = 1;
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abp_req_i_mul = !abp_req_i_mul;
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#100
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$display("Try signed -7*3: Product is %d", product_o);
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a_i = 17;
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b_i = 5;
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signed_i = 0;
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abp_req_i_div = !abp_req_i_div;
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#100
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$display("Try unsigned 17/5: Quotient is %d and remainder is %d", quotient_o, remainder_o);
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$finish();
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end
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always #1 sys_clock_i = !sys_clock_i;
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endmodule
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*/
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