Subversion Repositories m1_core

#@ #

#@ # Running dc_shell Version 2001.08 -- Aug 22, 2001

#@ # Date:   Tue Jan 15 21:02:25 2008

#@

source /usr/synopsys/synthesis/admin/setup/.synopsys_dc.setup

#@ #

#@ #

#@ #            ".synopsys_dc.setup" Initialization File for

#@ #

#@ #                Dc_Shell and Design_Analyzer

#@ #

#@ #    The variables in this file define the behavior of many parts

#@ #    of the Synopsys Synthesis Tools.  Upon installation, they should

#@ #    be reviewed and modified to fit your site's needs.  Each engineer

#@ #    can have a .synopsys file in his/her home directory or current

#@ #    directory to override variable settings in this file.

#@ #

#@ #    Each logical grouping of variables is commented as to their

#@ #    nature and effect on the Synthesis Commands.  Examples of

#@ #    variable groups are the Compile Variable Group, which affects

#@ #    the designs produced by the COMPILE command, and the Schematic

#@ #    Variable Group, which affects the output of the create_schematic

#@ #    command.

#@ #

#@ #    You can type "man _variables" in dc_shell or

#@ #    design_analyzer to get help about a group of variables.

#@ #    For instance, to get help about the "system" variable group,

#@ #    type "help system_variables".  You can also type

#@ #    "man ", to get help on the that variable's

#@ #    group.

#@ #

#@

#@ # System variables

#@ set sh_command_abbrev_mode       "Anywhere"

#@ set sh_continue_on_error         "true"

#@ set sh_enable_page_mode          "true"

#@ set sh_source_uses_search_path   "true"

#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {

#@  set sh_command_log_file          "./command.log"

#@ }

#@

#@

#@

#@ # Enable debug output on fatal

#@ if { $sh_arch == "sparc" || $sh_arch == "sparcOS5" ||      $sh_arch == "hp700" || $sh_arch == "hpux10"   ||      $sh_arch == "linux" } {

#@    setenv SYNOPSYS_TRACE ""

#@ }

#@

#@ #

#@ # Load the procedures which make up part of the user interface.

#@ #

#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {

#@   source $synopsys_root/auxx/syn/.dc_common_procs.tcl

#@   source $synopsys_root/auxx/syn/.dc_procs.tcl

#@   alias list_commands help

#@ }

#@ ##############################################################################

#@ #

#@ #

#@ # FILE:         auxx/syn/.dc_common_procs.tcl

#@ #

#@ # ABSTRACT:     These procedures are part of the PrimeTime and DC

#@ #               user interface.

#@ #               They are loaded by .synopsys_pt.setup and .synopsys_dc.setup.

#@ #

#@ ##############################################################################

#@ #

#@ #

#@

#@

#@ ##############################################################################

#@ #

#@ #

#@ #  PROCEDURE:   group_variable

#@ #

#@ #  ABSTRACT:    Add a variable to the specified variable group.

#@ #               This command is typically used by the system

#@ #               administrator only.

#@ #

#@ #               Below the proc is the command which creates the command

#@ #               help information and semantic data for the argument.

#@ #

#@ #  RETURNS:     1 if it is successful.

#@ #               error code if the variable does not exist.

#@ #               error code of the variable is already in the group.

#@ #

#@ #  SYNTAX:      group_variable group_name variable_name

#@ #

#@ ##############################################################################

#@ #

#@

#@

#@ proc group_variable { args } {

#@   global _Variable_Groups

#@

#@   parse_proc_arguments -args $args resarr

#@   set group $resarr(group)

#@   set var $resarr(variable_name)

#@

#@   if { ![info exists _Variable_Groups($group)] } {

#@    set _Variable_Groups($group) ""

#@   }

#@

#@   # Verify that var exists as a global variable

#@

#@   set cmd "uplevel #0 \{info exists $var\}"

#@   if { ![eval $cmd] } {

#@     return -code error "Variable '$var' is not defined."

#@   }

#@

#@   # Only add it if it's not already there

#@

#@   if { [lsearch $_Variable_Groups($group) $var] == -1 } {

#@     lappend _Variable_Groups($group) $var

#@   }

#@

#@   return 1

#@ }

#@

#@ define_proc_attributes group_variable     -info "Add a variable to a variable group"      -command_group "Builtins" -permanent -dont_abbrev     -define_args {

#@       {group "Variable group name" group}

#@       {variable_name "Variable name" variable_name}}

#@

#@ ##############################################################################

#@ #

#@ #

#@ #  PROCEDURE:   print_variable_group

#@ #

#@ #  ABSTRACT:    Shows variables and their values defined in the given group.

#@

#@ #

#@ #               Below the proc is the command which creates the command

#@ #               help information and semantic data for the argument.

#@ #

#@ #  RETURNS:     1 if it is successful.

#@ #               error code of the variable group does not exist.

#@ #

#@ #  SYNTAX:      print_variable_group group_name

#@ #

#@ ##############################################################################

#@ #

#@

#@ proc print_variable_group { args } {

#@   global _Variable_Groups

#@

#@   parse_proc_arguments -args $args resarr

#@   set group $resarr(group)

#@

#@   if { [string compare $group "all"] == 0 } {

#@     set cmd "uplevel #0 \{printvar\}"

#@     return [eval $cmd]

#@   }

#@

#@   if { ![info exists _Variable_Groups($group)] } {

#@     return -code error "Variable group '$group' does not exist."

#@   }

#@

#@   # Print out each global variable in the list. To be totally bulletproof,

#@   # test that each variable in the group is still defined.  If not, remove

#@   # it from the list.

#@

#@   foreach var [lsort $_Variable_Groups($group)] {

#@     set cmd "uplevel #0 \{info exists $var\}"

#@     if { ![eval $cmd] } {

#@       # Remove it

#@       set n [lsearch $_Variable_Groups($group) $var]

#@       set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n]

#@     } else {

#@       # Print it.

#@       set cmd "uplevel #0 \{set $var\}"

#@       set val [eval $cmd]

#@       echo [format "%-25s = \"%s\"" $var $val]

#@     }

#@   }

#@

#@   return 1

#@ }

#@

#@ define_proc_attributes print_variable_group     -info "Print the contents of a variable group"      -command_group "Builtins" -permanent      -define_args {{group "Variable group name" group}}

#@

#@

#@

#@ ##############################################################################

#@ #

#@ #

#@ #  PROCEDURE:   _Variable_Groups_Get_Groups

#@ #

#@ #  ABSTRACT:    Return a list of all variable groups. This command is hidden

#@ #               and is used by Design Vision.

#@ #

#@ #   RETURNS:    Tcl list of all variable groups including group all

#@ #

#@ #  SYNTAX:      _Variable_Groups_Get_Groups

#@ ##############################################################################

#@ #

#@

#@ proc _Variable_Groups_Get_Groups { } {

#@    global _Variable_Groups

#@

#@    set groups  [array names _Variable_Groups]

#@    append groups " all"

#@    return $groups

#@ }

#@ define_proc_attributes _Variable_Groups_Get_Groups -hidden

#@

#@

#@ ##############################################################################

#@ #

#@ #

#@ #  PROCEDURE:   _Variable_Groups_Get_Variables_Of_Group

#@ #

#@ #  ABSTRACT:    Return a list of all variables of a variable group.

#@ #               It also works for pseudo group all.

#@ #

#@ #   RETURNS:    Tcl list of all variables of a variable group including

#@ #               pseudo group all

#@ #

#@ #  SYNTAX:      _Variable_Groups_Get_Groups

#@ ##############################################################################

#@ #

#@

#@ proc _Variable_Groups_Get_Variables_Of_Group { group } {

#@   global _Variable_Groups

#@

#@   if { [string compare $group "all"] == 0 } {

#@     set itr [array startsearch _Variable_Groups]

#@     for {  } { [array anymore _Variable_Groups $itr]} { } {

#@       set index [array nextelement _Variable_Groups $itr]

#@       append vars $_Variable_Groups($index)

#@     }

#@     array donesearch _Variable_Groups $itr

#@     return $vars

#@   }

#@

#@   if { ![info exists _Variable_Groups($group)] } {

#@     return -code error "Variable group '$group' does not exist."

#@   }

#@

#@   # Test if all variables in the list of variables are still defined.

#@   # Remove not existing variables.

#@   foreach var [lsort $_Variable_Groups($group)] {

#@     set cmd "uplevel #0 \{info exists $var\}"

#@     if { ![eval $cmd] } {

#@       # Remove it

#@       set n [lsearch $_Variable_Groups($group) $var]

#@       set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n]

#@     }

#@   }

#@   return $_Variable_Groups($group)

#@ }

#@ define_proc_attributes _Variable_Groups_Get_Variables_Of_Group -hidden

#@

#@ # -- End source /usr/synopsys/synthesis/auxx/syn/.dc_common_procs.tcl

#@ ##############################################################################

#@ #

#@ #

#@ # FILE:         auxx/syn/.dc_procs.tcl

#@ #

#@ # ABSTRACT:     These procedures are part of the Design Compiler Tcl

#@ #               user interface.

#@ #               They are loaded by .synopsys_dc.setup.

#@ #

#@ ##############################################################################

#@ #

#@ #

#@

#@ ##############################################################################

#@ #

#@ #

#@ #  PROCEDURE:  read_verilog

#@ #

#@ #  ABSTRACT:   Emulate PT's read_verilog command in DC:

#@ #

#@ #  Usage:      read_verilog         #  Read one or more verilog files

#@ #                *[-hdl_compiler]       (Use HDL Compiler (ignored))

#@ #                file_names             (Files to read)

#@ #

#@ #  Modified: Bharat 11/17/99. Use uplevel to ensure that the command

#@ #            sees user/hidden variables from the top level. Star 92970.

#@ #

#@ ##############################################################################

#@ #

#@

#@ proc read_verilog { args } {

#@   parse_proc_arguments -args $args ra

#@

#@   set cmd [format {read_file -format verilog  [list %s]} $ra(file_names)]

#@   return [uplevel #0 $cmd]

#@ }

#@

#@ define_proc_attributes read_verilog     -info " Read one or more verilog files"     -permanent     -define_args {

#@       {file_names "Files to read" file_names list required}

#@    {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}}

#@ }

#@

#@

#@ ##############################################################################

#@ #

#@ #

#@ #  PROCEDURE: read_vhdl

#@ #

#@ #  ABSTRACT:  Emulate PT's read_vhdl command in DC:

#@ #

#@ #  Usage:     read_vhdl            #  Read one or more vhdl files

#@ #               file_names             (Files to read)

#@ #

#@ #

#@ ##############################################################################

#@ #

#@

#@ proc read_vhdl { args } {

#@   parse_proc_arguments -args $args ra

#@

#@   set cmd [format {read_file -format vhdl  [list %s]} $ra(file_names)]

#@   return [uplevel #0 $cmd]

#@ }

#@

#@ define_proc_attributes read_vhdl     -info " Read one or more vhdl files"     -permanent     -define_args {

#@       {file_names "Files to read" file_names list required}}

#@

#@ ##############################################################################

#@ #

#@ #

#@ #  PROCEDURE:   read_db

#@ #

#@ #  ABSTRACT:    Emulate PT's read_db command in DC:

#@ #

#@ #  Usage:

#@ #     read_db              #  Read one or more db files

#@ #       *[-netlist_only]       (Do not read any attributes from db (ignored))

#@ #       *[-library]            (File is a library DB (ignored))

#@ #      file_names             (Files to read)

#@ #

#@ #

#@ ##############################################################################

#@ #

#@

#@ proc read_db { args } {

#@   parse_proc_arguments -args $args ra

#@

#@   set cmd [format {read_file -format db  [list %s]} $ra(file_names)]

#@   return [uplevel #0 $cmd]

#@ }

#@

#@ define_proc_attributes read_db     -info " Read one or more db files"     -permanent     -define_args {

#@       {file_names "Files to read" file_names list required}

#@       {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}}

#@       {-library "File is a library DB (ignored)" "" boolean {hidden optional}}

#@      }

#@

#@ ##############################################################################

#@ #

#@ #

#@ #  PROCEDURE:   read_edif

#@ #

#@ #  ABSTRACT:    Emulate PT's read_edif command in DC:

#@ #

#@ #  Usage:

#@ #      read_edif            #  Read one or more edif files

#@ #        *[-complete_language]  (Use ptxr to read the file (ignored))

#@ #        file_names             (Files to read)

#@ #

#@ #

#@ ##############################################################################

#@ #

#@ proc read_edif { args } {

#@   parse_proc_arguments -args $args ra

#@

#@   set cmd [format {read_file -format edif  [list %s]} $ra(file_names)]

#@   return [uplevel #0 $cmd]

#@ }

#@

#@ define_proc_attributes read_edif     -info " Read one or more edif files"     -permanent     -define_args {

#@       {file_names "Files to read" file_names list required}

#@       {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}}

#@ }

#@

#@ # -- End source /usr/synopsys/synthesis/auxx/syn/.dc_procs.tcl

#@

#@ # Temporary fix for the LMC_HOME variable- set it to an empty string

#@

#@ if { [catch {getenv LMC_HOME } __err ] != 0 } {

#@   setenv LMC_HOME ""

#@ }

#@

#@

#@ #

#@ #

#@ #       Site-Specific Variables

#@ #

#@ #       These are the variables that are most commonly changed at a

#@ #       specific site, either upon installation of the Synopsys software,

#@ #       or by specific engineers in their local .synopsys files.

#@ #

#@ #

#@

#@ # from the System Variable Group

#@ set link_force_case  "check_reference"

#@ set link_library  { * umce13h210t3_tc_120V_25C.db }

#@ set physical_library ""

#@

#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/dw/sim_ver /usr/synopsys/libraries/umc/]

#@ set target_library umce13h210t3_tc_120V_25C.db

#@ set synthetic_library  ""

#@ set command_log_file  "./command.log"

#@ set designer  ""

#@ set company  ""

#@ set find_converts_name_lists  "false"

#@

#@ set symbol_library umce13h210t3.sdb

#@

#@ # from the Schematic Variable Group

#@

#@ # from the Plot Variable Group

#@ if { $sh_arch == "hp700" } {

#@   set plot_command "lp -d"

#@ } else {

#@   set plot_command "lpr -Plw"

#@ }

#@

#@ set view_command_log_file  "./view_command.log"

#@

#@ # from the View Variable group

#@ if { $sh_arch == "hp700" } {

#@    set text_print_command  "lp -d"

#@ } else {

#@    set text_print_command  "lpr -Plw"

#@ }

#@ #

#@ #       System Variable Group:

#@ #

#@ #       These variables are system-wide variables.

#@ #

#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid

#@ set auto_link_disable  "false"

#@ set auto_link_options  "-all"

#@ set uniquify_naming_style  "%s_%d"

#@ set verbose_messages  "true"

#@ set echo_include_commands  "true"

#@ set preserve_subshells  "hdl_shell_exec"

#@ set suppress_errors  {PWR-18 OPT-932 OPT-317}

#@ set change_names_update_inst_tree   "true"

#@ set change_names_dont_change_bus_members false

#@ set default_name_rules ""

#@

#@ #

#@ #       Compile Variable Group:

#@ #

#@ #       These variables affect the designs created by the COMPILE command.

#@ #

#@ set compile_assume_fully_decoded_three_state_busses   "false"

#@ set compile_automatic_clock_phase_inference    "strict"

#@ set compile_no_new_cells_at_top_level   "false"

#@ set compile_dont_touch_annotated_cell_during_inplace_opt   "false"

#@ set compile_update_annotated_delays_during_inplace_opt  "true"

#@ set compile_instance_name_prefix   "U"

#@ set compile_instance_name_suffix   ""

#@ set compile_negative_logic_methodology   "false"

#@ set compile_disable_hierarchical_inverter_opt   "false"

#@ set compile_use_fast_delay_mode   "true"

#@ set compile_use_low_timing_effort   "false"

#@ set compile_new_boolean_structure   "false"

#@ set compile_fix_cell_degradation   "false"

#@ set compile_preserve_subdesign_interfaces   "false"

#@ set compile_sequential_area_recovery   "false"

#@ set port_complement_naming_style   "%s_BAR"

#@ set compile_implementation_selection   "true"

#@ set compile_mux_no_boundary_optimization   "false"

#@ set compile_create_mux_op_hierarchy   "true"

#@ set compile_delete_unloaded_sequential_cells   "true"

#@ set reoptimize_design_changed_list_file_name   ""

#@ set compile_checkpoint_filename "./CHECKPOINT.db"

#@ set compile_checkpoint_cpu_interval 0.0

#@ set compile_checkpoint_phases "false"

#@ set compile_checkpoint_pre_delay_filename "./CHECKPOINT_PRE_DELAY.db"

#@ set compile_checkpoint_pre_drc1_filename "./CHECKPOINT_PRE_DRC1.db"

#@ set compile_checkpoint_pre_drc2_filename "./CHECKPOINT_PRE_DRC2.db"

#@ set compile_checkpoint_pre_area_filename "./CHECKPOINT_PRE_AREA.db"

#@ set compile_cpu_limit 0.0

#@ set compile_log_format "  %elap_time %area %wns %tns %drc %endpoint";

#@ set compile_top_all_paths   "false"

#@ set default_port_connection_class "universal"

#@ set compile_dw_simple_mode "false"

#@ set compile_simple_mode_block_effort "none"

#@ set compile_hold_reduce_cell_count "false"

#@ set compile_new_optimization "false"

#@

#@

#@ set ldd_return_val 0

#@ if { [string compare $dc_shell_mode "default"] == 0 } {

#@   set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh

#@   alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val "

#@

#@ }

#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {

#@   set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl

#@   alias list_duplicate_designs "source $ldd_script; set dc_shell_status $ldd_return_val "

#@ }

#@

#@

#@ set compile_log_format "  %elap_time %area %wns %tns %drc %endpoint";

#@

#@ set compile_top_all_paths "false"

#@ alias compile_inplace_changed_list_file_name                 reoptimize_design_changed_list_file_name

#@ #

#@ #  These variables affects compile, report_timing and report_constraints

#@ #  commands.

#@ #

#@ set enable_recovery_removal_arcs  "false"

#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net}

#@

#@ #

#@ #       Multibit Variable Group:

#@ #

#@ #       These variables affect the multibit mapping functionality

#@ #

#@

#@ set bus_multiple_separator_style  ","

#@

#@ #

#@ #       Estimator Variable Group:

#@ #

#@ #       These variables affect the designs created by the ESTIMATE command.

#@ #

#@ set estimate_resource_preference  "fast"

#@ alias est_resource_preference estimate_resource_preference

#@ set lbo_lfo_enable_at_pin_count   3

#@ set lbo_cells_in_regions   "false"

#@

#@ #     Synthetic Library Group:

#@ #

#@ #       These variable affect synthetic library processing.

#@ #

#@ set cache_dir_chmod_octal   "777"

#@ set cache_file_chmod_octal  "666"

#@ set cache_read   "~"

#@ set cache_read_info  "false"

#@ set cache_write  "~"

#@ set cache_write_info   "false"

#@ set dw_prefer_mc_inside "false"

#@ set mgi_scratch_directory "designware_generator"

#@ set synlib_disable_limited_licenses   "true"

#@ set synlib_dont_get_license  {}

#@ set synlib_evaluation_mode  "false"

#@ set synlib_library_list   {DW01 DW02 DW03 DW04 DW05 DW06 DW07 DW08}

#@ set synlib_model_map_effort  "medium"

#@ set synlib_optimize_non_cache_elements  "true"

#@ set synlib_prefer_ultra_license "false"

#@ set synlib_sequential_module   "default"

#@ set synlib_wait_for_design_license {}

#@

#@ #

#@ #       Insert_DFT Variable Group:

#@ #

#@ set test_default_client_order [list]

#@ set test_point_keep_hierarchy "false"

#@ set insert_dft_clean_up "true"

#@ set insert_test_design_naming_style  "%s_test_%d"

#@ # /*insert_test_scan_chain_only_one_clock = "false"

#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/

#@ set test_clock_port_naming_style  "test_c%s"

#@ set test_scan_clock_a_port_naming_style  "test_sca%s"

#@ set test_scan_clock_b_port_naming_style  "test_scb%s"

#@ set test_scan_clock_port_naming_style   "test_sc%s"

#@ set test_scan_enable_inverted_port_naming_style   "test_sei%s"

#@ set test_scan_enable_port_naming_style   "test_se%s"

#@ set test_scan_in_port_naming_style   "test_si%s%s"

#@ set test_scan_out_port_naming_style  "test_so%s%s"

#@ set test_non_scan_clock_port_naming_style  "test_nsc_%s"

#@ set test_default_min_fault_coverage  95

#@ set test_dedicated_subdesign_scan_outs  "true"

#@ set test_disable_find_best_scan_out  "false"

#@ set test_dont_fix_constraint_violations  "false"

#@ set test_isolate_hier_scan_out  0

#@ set test_mode_port_naming_style  "test_mode%s"

#@ set test_mode_port_inverted_naming_style  "test_mode_i%s"

#@ set compile_dont_use_dedicated_scanout 1

#@ set test_mux_constant_so "false"

#@

#@ #

#@ #        Analyze_Scan Variable Group:

#@ #

#@ #     These variables affect the designs created by the PREVIEW_SCAN command.

#@ #

#@ set test_preview_scan_shows_cell_types  "false"

#@ set test_scan_link_so_lockup_key "l"

#@ set test_scan_link_wire_key  "w"

#@ set test_scan_segment_key  "s"

#@ set test_scan_true_key  "t"

#@ set test_jump_over_bufs_invs "true"

#@

#@ #

#@ #        bsd Variable Group:

#@

#@ #        These variables affect the report generated by the check_bsd command

#@ #        and the BSDLout generated by the write_bsdl command.

#@ #

#@ set test_user_test_data_register_naming_style  "UTDR%d"

#@

#@ set test_user_defined_instruction_naming_style  "USER%d"

#@

#@ set test_bsdl_default_suffix_name  "bsdl"

#@

#@ set test_bsdl_max_line_length  80

#@

#@ set test_cc_ir_masked_bits 0

#@

#@ set test_cc_ir_value_of_masked_bits 0

#@

#@ set test_bsd_allow_tolerable_violations "false"

#@ set test_bsd_optimize_control_cell "false"

#@ set test_bsd_control_cell_drive_limit 0

#@ set test_bsd_manufacturer_id 0

#@ set test_bsd_part_number 0

#@ set test_bsd_version_number 0

#@

#@

#@ #

#@ #        TestManager Variable Group:

#@ #

#@ #        These variables affect the TestManager methodology.

#@ #

#@ set multi_pass_test_generation  "false"

#@

#@ #

#@ #        TestSim Variable Group:

#@ #

#@ #        These variables affect the TestSim behavior.

#@ #

#@ # set testsim_print_stats_file  "true"

#@

#@ #      Test DRC Variable Group:

#@ #

#@ #        These variables affect the check_test command.

#@ #

#@ set test_capture_clock_skew  "small_skew"

#@ set test_allow_clock_reconvergence  "true"

#@ set test_check_port_changes_in_capture  "true"

#@ set test_infer_slave_clock_pulse_after_capture "infer"

#@

#@ #

#@ #       Test Variable Group:

#@ #

#@ #       These variables affect the rtldrc, check_test, write_test_protocol

#@ #       and write_test command.

#@ #

#@ set test_default_delay  5.0

#@ set test_default_bidir_delay  55.0

#@ set test_default_strobe  95.0

#@ set test_default_strobe_width  0.0

#@ set test_default_period  100.0

#@ set test_default_scan_style  "multiplexed_flip_flop"

#@ set test_stil_netlist_format "db"

#@ set test_stil_multiclock_capture_procedures "false"

#@ set test_stil_max_line_length 72

#@ set test_write_four_cycle_stil_protocol "false"

#@ set test_protocol_add_cycle "true"

#@ set test_rtldrc_latch_check_style "default"

#@

#@ #

#@ #       JTAG variable group (associated with the insert_jtag command):

#@ #

#@ #       These variables are associated with JTAG synthesis.

#@ #

#@ set jtag_port_drive_limit  6

#@ set jtag_manufacturer_id  0

#@ set jtag_version_number  0

#@ set jtag_part_number  65535

#@ set jtag_test_data_in_port_naming_style  "jtag_tdi%s"

#@ set jtag_test_data_out_port_naming_style  "jtag_tdo%s"

#@ set jtag_test_mode_select_port_naming_style  "jtag_tms%s"

#@ set jtag_test_clock_port_naming_style  "jtag_tck%s"

#@ set jtag_test_reset_port_naming_style   "jtag_trst%s"

#@

#@

#@

#@ #

#@ #       Create_Test_Patterns Variable Group:

#@ #

#@ #       These variables affect the create_test_patterns command.

#@ #

#@ # From Peace on, the "atpg_test_asynchronous_pins" is obsolete

#@ # set atpg_test_asynchronous_pins  "true"

#@

#@ set atpg_bidirect_output_only  "false"

#@

#@

#@ #

#@ #       Write_Test Variable Group:

#@ #

#@ #       These variables affect output of the WRITE_TEST command.

#@ #

#@ set write_test_input_dont_care_value  "X"

#@ set write_test_vector_file_naming_style  "%s_%d.%s"

#@ set write_test_scan_check_file_naming_style   "%s_schk.%s"

#@ set write_test_pattern_set_naming_style  "TC_Syn_%d"

#@ set write_test_max_cycles  0

#@ set write_test_max_scan_patterns  0

#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */

#@ set write_test_formats   {synopsys tssi_ascii tds verilog vhdl wgl}

#@ set write_test_include_scan_cell_info  "true"

#@ set write_test_round_timing_values "true"

#@

#@ #

#@ #       Schematic and EDIF and Hdl Variable Groups:

#@ #

#@ #       These variables affect the schematics created by the

#@ #       create_schematic command, define the behavior of the

#@ #       DC system EDIF interface, and are for controlling hdl

#@ #       reading.

#@ #

#@ set bus_dimension_separator_style  {][}

#@ set bus_naming_style  {%s[%d]}

#@

#@

#@ #

#@ #       Schematic and EDIF Variable Groups:

#@ #

#@ #       These variables affect the schematics created by the

#@ #       create_schematic command and define the behavior of

#@ #       the DC system EDIF interface.

#@ #

#@ set bus_range_separator_style  ":"

#@

#@

#@ #

#@ # EDIF and Io Variable Groups:

#@ #

#@ # These variables define the behavior of the DC system EDIF interface and

#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc.

#@

#@ set bus_inference_descending_sort  "true"

#@ set bus_inference_style  ""

#@ set write_name_nets_same_as_ports  "false"

#@ #

#@ #       Schematic Variable Group:

#@ #

#@ #       These variables affect the schematics created by the

#@ #       create_schematic command.

#@ #

#@ set font_library  "1_25.font"

#@ set generic_symbol_library  "generic.sdb"

#@ set gen_max_ports_on_symbol_side  0

#@ set duplicate_ports   "false"

#@ set sheet_sizes  {A B C D E infinite mentor_maximum sge_maximum}

#@ set single_group_per_sheet  "false"

#@ set use_port_name_for_oscs  "true"

#@ set gen_bussing_exact_implicit  "false"

#@ set gen_cell_pin_name_separator  "/"

#@ set gen_max_compound_name_length  256

#@ set gen_show_created_symbols  "false"

#@ set gen_match_ripper_wire_widths  "false"

#@ set gen_show_created_busses  "false"

#@ set gen_dont_show_single_bit_busses  "false"

#@ set gen_single_osc_per_name  "false"

#@ set gen_create_netlist_busses  "true"

#@ # This setting will be overwritten to true below when using

#@ # Design Vision or Psyn Gui

#@ set sort_outputs  "false"

#@ if { ( [string compare $synopsys_program_name "design_vision"] == 0 ) ||

#@      ( [string compare $synopsys_program_name "psyn_gui"] == 0 ) } {

#@   set dv_enable_conservative_invalidate "true"

#@ }

#@ set gen_open_name_prefix  "Open"

#@ set gen_open_name_postfix  ""

#@ set default_schematic_options  "-size infinite"

#@ # This setting makes gen use the old way to annotate schematics for

#@ #   everything except sheets, which is fast enough.

#@ #

#@ set annotation_control  64

#@

#@ #

#@ #       Plot Variable Group:

#@ #

#@ #       These variables define the operating system and plotter

#@ #       interface to the Design Compiler.  These should be set at

#@ #       installation time, if needed, and then changed only if you

#@ #       start using a new type of plotter.

#@ #

#@ #       These four variables must be changed if you use a larger or

#@ #       smaller plotter or printer:

#@ #

#@ #       plotter_maxx, plotter_maxy, plotter_minx, plotter_miny

#@ #

#@ #       See the group of site-specific variables at the top of this

#@ #       file to set the name of your printer or plotter.

#@ #

#@ #

#@

#@ set plot_orientation  "best_fit"

#@ set plotter_maxx   584

#@ set plotter_maxy   764

#@ set plotter_minx   28

#@ set plotter_miny   28

#@ set plot_scale_factor   100

#@ set plot_box   "false"

#@

#@

#@ #

#@ #       Io Variable Group:

#@ #

#@ #       These variables define the behavior of the DC system

#@ #       interfaces, i.e. LSI, Mentor, TDL, SGE, etc.

#@ #

#@ set db2sge_output_directory  ""

#@ set db2sge_scale  "2"

#@ set db2sge_overwrite   "true"

#@ set db2sge_display_symbol_names  "false"

#@

#@

#@ set db2sge_display_pin_names  "false"

#@ set db2sge_display_instance_names   "false"

#@ set db2sge_use_bustaps   "false"

#@ set db2sge_use_compound_names   "true"

#@ set db2sge_bit_type   "std_logic"

#@ set db2sge_bit_vector_type   "std_logic_vector"

#@ set db2sge_one_name   "'1'"

#@ set db2sge_zero_name  "'0'"

#@ set db2sge_unknown_name  "'X'"

#@ set db2sge_target_xp  "false"

#@ set db2sge_tcf_package_file  "synopsys_tcf.vhd"

#@ set db2sge_use_lib_section  ""

#@ set db2sge_script  ""

#@ set db2sge_command  ""

#@ set equationout_and_sign  "*"

#@ set equationout_or_sign  "+"

#@ set equationout_postfix_negation  "true"

#@ set lsiin_net_name_prefix  "NET_"

#@ set lsiout_inverter_cell  ""

#@ set lsiout_upcase  "true"

#@ set mentor_bidirect_value  "INOUT"

#@ set mentor_do_path  ""

#@ set mentor_input_output_property_name  "PINTYPE"

#@ set mentor_input_value  "IN"

#@ set mentor_logic_one_value  "1SF"

#@ set mentor_logic_zero_one_property_name  "INIT"

#@ set mentor_logic_zero_value  "0SF"

#@ set mentor_output_value  "OUT"

#@ set mentor_primitive_property_name  "PRIMITIVE"

#@ set mentor_primitive_property_value  "MODULE"

#@ set mentor_reference_property_name  "COMP"

#@ set mentor_search_path   ""

#@ set mentor_write_symbols   "true"

#@ set pla_read_create_flip_flop   "false"

#@ set tdlout_upcase   "true"

#@ set xnfout_constraints_per_endpoint   "50"

#@ set xnfout_default_time_constraints   true

#@ set xnfout_clock_attribute_style   "CLK_ONLY"

#@ set xnfout_library_version  ""

#@ set xnfin_family   "4000"

#@ set xnfin_ignore_pins   "GTS GSR GR"

#@ set xnfin_dff_reset_pin_name             "RD"

#@ set xnfin_dff_set_pin_name               "SD"

#@ set xnfin_dff_clock_enable_pin_name      "CE"

#@ set xnfin_dff_data_pin_name              "D"

#@ set xnfin_dff_clock_pin_name             "C"

#@ set xnfin_dff_q_pin_name                 "Q"

#@

#@

#@ #

#@ #       EDIF Variable Group:

#@ #

#@ #       These variables define the behavior of the DC system

#@ #       EDIF interface.

#@ #

#@ set bus_extraction_style   {%s[%d:%d]}

#@ set edifin_autoconnect_offpageconnectors   "false"

#@ set edifin_autoconnect_ports   "false"

#@ set edifin_dc_script_flag   ""

#@ set edifin_delete_empty_cells   "true"

#@ set edifin_delete_ripper_cells   "true"

#@ set edifin_ground_net_name   ""

#@ set edifin_ground_net_property_name   ""

#@ set edifin_ground_net_property_value   ""

#@ set edifin_ground_port_name   ""

#@ set edifin_instance_property_name    ""

#@ set edifin_portinstance_disabled_property_name   ""

#@ set edifin_portinstance_disabled_property_value   ""

#@ set edifin_portinstance_property_name   ""

#@ set edifin_power_net_name  ""

#@ set edifin_power_net_property_name  ""

#@ set edifin_power_net_property_value  ""

#@ set edifin_power_port_name  ""

#@ set edifin_use_identifier_in_rename  "false"

#@ set edifin_view_identifier_property_name  ""

#@ set edifin_lib_logic_1_symbol  ""

#@ set edifin_lib_logic_0_symbol  ""

#@ set edifin_lib_in_port_symbol  ""

#@ set edifin_lib_out_port_symbol  ""

#@ set edifin_lib_inout_port_symbol  ""

#@ set edifin_lib_in_osc_symbol  ""

#@ set edifin_lib_out_osc_symbol  ""

#@ set edifin_lib_inout_osc_symbol  ""

#@ set edifin_lib_mentor_netcon_symbol  ""

#@ set edifin_lib_ripper_bits_property  ""

#@ set edifin_lib_ripper_bus_end  ""

#@ set edifin_lib_ripper_cell_name  ""

#@ set edifin_lib_ripper_view_name  ""

#@ set edifin_lib_route_grid  1024

#@ set edifin_lib_templates  {}

#@ set edifout_dc_script_flag  ""

#@ set edifout_design_name  "Synopsys_edif"

#@ set edifout_designs_library_name  "DESIGNS"

#@ set edifout_display_instance_names  "false"

#@ set edifout_display_net_names  "false"

#@ set edifout_external  "true"

#@ set edifout_external_graphic_view_name  "Graphic_representation"

#@ set edifout_external_netlist_view_name  "Netlist_representation"

#@ set edifout_external_schematic_view_name  "Schematic_representation"

#@ set edifout_ground_name  "logic_0"

#@ set edifout_ground_net_name  ""

#@ set edifout_ground_net_property_name  ""

#@ set edifout_ground_net_property_value  ""

#@ set edifout_ground_pin_name  "logic_0_pin"

#@ set edifout_ground_port_name  "GND"

#@ set edifout_instance_property_name   ""

#@ set edifout_instantiate_ports  "false"

#@ set edifout_library_graphic_view_name  "Graphic_representation"

#@ set edifout_library_netlist_view_name  "Netlist_representation"

#@ set edifout_library_schematic_view_name  "Schematic_representation"

#@ set edifout_merge_libraries  "false"

#@ set edifout_multidimension_arrays  "false"

#@ set edifout_name_oscs_different_from_ports  "false"

#@ set edifout_name_rippers_same_as_wires  "false"

#@ set edifout_netlist_only   "false"

#@ set edifout_no_array   "false"

#@ set edifout_numerical_array_members   "false"

#@ set edifout_pin_direction_in_value   ""

#@ set edifout_pin_direction_inout_value   ""

#@ set edifout_pin_direction_out_value   ""

#@ set edifout_pin_direction_property_name   ""

#@ set edifout_pin_name_property_name   ""

#@ set edifout_portinstance_disabled_property_name    ""

#@ set edifout_portinstance_disabled_property_value    ""

#@ set edifout_portinstance_property_name    ""

#@ set edifout_power_and_ground_representation   "cell"