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[/] [m1_core/] [tags/] [first/] [tools/] [src/] [.synopsys_dc.setup] - Blame information for rev 55

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set_local_link_library = { umce13h210t3_tc_120V_25C.db }
search_path = { /usr/design/techlibs/umc/design_compiler ../../../hdl/rtl/m1_cpu }
link_library = { umce13h210t3_tc_120V_25C.db }
target_library = { umce13h210t3_tc_120V_25C.db }
symbol_library = { umce13h210t3.sdb }
define_design_lib DEFAULT -path ./WORK_SYNTH
verilogout_write_components = "FALSE"
 

Line No.	Rev	Author	Line
1	2	fafa1971	`set_local_link_library = { umce13h210t3_tc_120V_25C.db }`
2			`search_path = { /usr/design/techlibs/umc/design_compiler ../../../hdl/rtl/m1_cpu }`
3			`link_library = { umce13h210t3_tc_120V_25C.db }`
4			`target_library = { umce13h210t3_tc_120V_25C.db }`
5			`symbol_library = { umce13h210t3.sdb }`
6			`define_design_lib DEFAULT -path ./WORK_SYNTH`
7			`verilogout_write_components = "FALSE"`
8

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[/] [m1_core/] [tags/] [first/] [tools/] [src/] [.synopsys_dc.setup] - Blame information for rev 55