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Simply RISC M1 Core ("Mistral") TODO List
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=========================================
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Implementation
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--------------
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Memory hierarchy requires at least a Wishbone interface
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and some sort of caches.
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Functional Verification
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-----------------------
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The simulation work has been performed by Simone Lunardo and Paolo Piscopo;
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the verification status for each SIMPLE instruction is as follows:
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- LOAD/STORE
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Common 32-bit LW/SW have been tested and they work.
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Other sizes are not working.
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Unaligned accesses are not implemented at all.
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- ALU I-TYPE, ALU R-TYPE, SHIFT, MULTIPLY-DIVIDE
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All tested and working.
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- JUMP/BRANCH
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Jump are working (J JAL JR JALR) including the delay slot.
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Equality branches (BEQ BNE) execute 2 delay slots rather than just 1.
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Disequality branches (BLEZ BGTZ BLTZ BGEZ) do not work.
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