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Simply RISC M1 Core ("Mistral") TODO List
=========================================
 
Implementation
--------------
At the moment the CPU has no exception nor external interrupt handling.
 
 
Functional Verification
-----------------------
Several simulations have been performed by Fabio Motta, Simone Lunardo and Paolo Piscopo.
 
 
Open issues
-----------
While Jump are working (J JAL JR JALR) including the delay slot,
equality branches (BEQ BNE) execute 2 delay slots rather than just 1
and disequality branches (BLEZ BGTZ BLTZ BGEZ) do not work yet.
 

Line No.	Rev	Author	Line
1	30	fafa1971	`Simply RISC M1 Core ("Mistral") TODO List`
2			`=========================================`
3
4			`Implementation`
5			`--------------`
6	52	fafa1971	`At the moment the CPU has no exception nor external interrupt handling.`
7	30	fafa1971
8
9	52	fafa1971	`Functional Verification`
10			`-----------------------`
11			`Several simulations have been performed by Fabio Motta, Simone Lunardo and Paolo Piscopo.`
12	30	fafa1971
13
14	52	fafa1971	`Open issues`
15			`-----------`
16			`While Jump are working (J JAL JR JALR) including the delay slot,`
17			`equality branches (BEQ BNE) execute 2 delay slots rather than just 1`
18			`and disequality branches (BLEZ BGTZ BLTZ BGEZ) do not work yet.`
19	30	fafa1971

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[/] [m1_core/] [trunk/] [doc/] [TODO.txt] - Blame information for rev 52