Subversion Repositories m1_core

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*                Copyright 2003 Micron Technology, Inc. All rights reserved.

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    // Timing parameters based on Speed Grade

                                          // SYMBOL UNITS DESCRIPTION

                                          // ------ ----- -----------

// `ifdef sg6T                               //              Timing Parameters for -6T (CL = 2.5)

    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time

    parameter tDQSQ            =    0.45; // tDQSS  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access

    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time

    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command

    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time

    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time

    parameter tRFC             =   120.0; // tRFC   ns    Refresh to Refresh Command interval time

    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time

    parameter tRP              =    15.0; // tRP    ns    Precharge command period

    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time

    parameter tWR              =    15.0; // tWR    ns    Write recovery time

    // Size Parameters based on Part Width

//`else `define x16

    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used

    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used

    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used

    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used

    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used

    parameter full_mem_bits    = 2+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used

    parameter part_mem_bits    = 10;                   // Set this parameter to control how many unique addresses are used

    parameter no_halt          =       0; // If set to 1, the model won't halt on command sequence/major errors

    parameter Debug            =       1; // Turn on debug message