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[/] [m1_core/] [trunk/] [hdl/] [behav/] [xilinx_unisim/] [BUFG.v] - Blame information for rev 54

Line No.	Rev	Author	Line
1	36	fafa1971	`// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/m1_core/hdl/behav/xilinx_unisim/BUFG.v,v 1.1 2008-11-07 13:12:06 fafa1971 Exp $`
2			`///////////////////////////////////////////////////////////////////////////////`
3			`// Copyright (c) 1995/2004 Xilinx, Inc.`
4			`// All Right Reserved.`
5			`///////////////////////////////////////////////////////////////////////////////`
6			`// ____ ____`
7			`// / /\/ /`
8			`// /___/ \ / Vendor : Xilinx`
9			`// \ \ \/ Version : 8.1i (I.13)`
10			`// \ \ Description : Xilinx Functional Simulation Library Component`
11			`// / / Global Clock Buffer`
12			`// /___/ /\ Filename : BUFG.v`
13			`// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004`
14			`// \___\/\___\`
15			`//`
16			`// Revision:`
17			`// 03/23/04 - Initial version.`
18			`// End Revision`
19
20			`timescale 100 ps / 10 ps
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22
23			`module BUFG (O, I);`
24
25			`output O;`
26
27			`input I;`
28
29			`buf B1 (O, I);`
30
31
32			`endmodule`
33