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fafa1971 |
/*
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* Simply RISC M1 Central Processing Unit
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*/
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`include "m1_defs.vh"
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module m1_cpu (
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// System
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input sys_clock_i, // System Clock
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input sys_reset_i, // System Reset
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input sys_irq_i, // Interrupt Request
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// ALU
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output[31:0] alu_a_o, // ALU Operand A
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output[31:0] alu_b_o, // ALU Operand B
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output[4:0] alu_func_o, // ALU Function
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output alu_signed_o, // ALU operation is Signed
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input[31:0] alu_result_i, // ALU Result
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input alu_carry_i, // ALU Carry
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// Multiplier
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output reg mul_req_o, // Multiplier Request
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output[31:0] mul_a_o, // Multiplier Operand A
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output[31:0] mul_b_o, // Multiplier Operand B
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output mul_signed_o, // Multiplication is Signed
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input mul_ack_i, // Multiplier Ack
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input[63:0] mul_product_i, // Multiplier Product
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// Divider
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output reg div_req_o, // Divider Request
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output[31:0] div_a_o, // Divider Operand A
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output[31:0] div_b_o, // Divider Operand B
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output div_signed_o, // Division is Signed
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input div_ack_i, // Divider Ack
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input[31:0] div_quotient_i, // Divider Quotient
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input[31:0] div_remainder_i, // Divider Remainder
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// Instruction Memory
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output imem_read_o, // I$ Read
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output[31:0] imem_addr_o, // I$ Address
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input imem_done_i, // I$ Done
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input[31:0] imem_data_i, // I$ Data
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// Data Memory
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output dmem_read_o, // D$ Read
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output dmem_write_o, // D$ Write
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output[3:0] dmem_sel_o, // D$ Byte selector
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output[31:0] dmem_addr_o, // D$ Address
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output[31:0] dmem_data_o, // D$ Write Data
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input dmem_done_i, // D$ Done
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input[31:0] dmem_data_i // D$ Read Data
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);
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/*
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* Registers
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*/
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// Register file
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reg[31:0] GPR[31:0]; // General Purpose Registers
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reg[31:0] PC; // Program Counter
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reg[31:0] HI, LO; // HI and LO registers (for multiplication/division)
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/*
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* Pipeline latches
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*/
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// Latch 1: IF/ID
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reg[31:0] if_id_opcode; // Instruction Register
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reg[31:0] if_id_addr, if_id_addrnext; // Addresses of the fetched opcode and of the next one
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// Latch 2: ID/EX
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reg[31:0] id_ex_opcode;
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reg[31:0] id_ex_addr, id_ex_addrnext;
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reg[31:0] id_ex_addrbranch, id_ex_addrjump, id_ex_addrjr; // Evaluated jump addresses
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reg[31:0] id_ex_alu_a, id_ex_alu_b; // ALU operands
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reg[4:0] id_ex_alu_func; // ALU operation code
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reg id_ex_alu_signed; // ALU operation is signed
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reg id_ex_branch, id_ex_jump, id_ex_jr, id_ex_linked; // Instruction is a jump
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reg id_ex_mult, id_ex_div; // Instruction is a multiplication/division
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reg id_ex_load, id_ex_store; // Instruction is a load/store
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reg[2:0] id_ex_size; // Load/store size (see defs.h)
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reg[31:0] id_ex_store_value; // Store value
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reg[4:0] id_ex_destreg; // Destination register (GPR number)
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reg id_ex_desthi, id_ex_destlo; // Destination register (HI/LO)
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// Latch 3: EX/MEM
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reg[31:0] ex_mem_opcode;
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reg[31:0] ex_mem_addr, ex_mem_addrnext;
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reg[31:0] ex_mem_addrbranch, ex_mem_addrjump, ex_mem_addrjr;
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reg[63:0] ex_mem_aluout; // ALU result
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reg ex_mem_branch, ex_mem_jump, ex_mem_jr, ex_mem_linked;
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reg ex_mem_mult, ex_mem_div;
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reg ex_mem_load,ex_mem_store;
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reg[31:0] ex_mem_store_value;
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reg[3:0] ex_mem_store_sel; // Byte Selector on Stores
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reg[4:0] ex_mem_destreg;
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reg ex_mem_desthi, ex_mem_destlo;
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// Latch 4: MEM/WB
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reg[31:0] mem_wb_opcode;
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reg[31:0] mem_wb_addr, mem_wb_addrnext;
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reg[63:0] mem_wb_value; // Write-back value
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reg[4:0] mem_wb_destreg;
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reg mem_wb_desthi, mem_wb_destlo;
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/*
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* Combinational logic
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*/
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// ALU
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assign alu_a_o = id_ex_alu_a;
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assign alu_b_o = id_ex_alu_b;
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assign alu_func_o = id_ex_alu_func;
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assign alu_signed_o = id_ex_alu_signed;
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// Multiplier
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assign mul_a_o = id_ex_alu_a;
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assign mul_b_o = id_ex_alu_b;
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assign mul_signed_o = id_ex_alu_signed;
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wire mul_ready = (mul_req_o==mul_ack_i); // Convert ABP ack to true/false format
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wire mul_busy = !mul_ready;
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// Divider
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assign div_a_o = id_ex_alu_a;
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assign div_b_o = id_ex_alu_b;
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assign div_signed_o = id_ex_alu_signed;
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wire div_ready = (div_req_o==div_ack_i); // Convert ABP ack to true/false format
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wire div_busy = !div_ready;
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// Incremented Program Counter
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wire[31:0] PCnext = PC + 4;
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// Instruction Memory
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assign imem_read_o = 1;
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assign imem_addr_o = PC;
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// Data Memory
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assign dmem_addr_o = ex_mem_aluout;
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assign dmem_read_o = ex_mem_load;
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assign dmem_write_o = ex_mem_store;
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assign dmem_data_o = ex_mem_store_value;
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assign dmem_sel_o = ex_mem_store_sel;
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// Decode fields from the Instruction Register
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wire[5:0] if_id_op = if_id_opcode[31:26]; // Operation code
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wire[4:0] if_id_rs = if_id_opcode[25:21]; // Source register
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wire[4:0] if_id_rt = if_id_opcode[20:16]; // Target register
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wire[4:0] if_id_rd = if_id_opcode[15:11]; // Destination register
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wire[31:0] if_id_imm_signext = {{16{if_id_opcode[15]}}, if_id_opcode[15:0]}; // Immediate field with sign-extension
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wire[31:0] if_id_imm_zeroext = {16'b0, if_id_opcode[15:0]}; // Immediate field with zero-extension
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wire[25:0] if_id_index = if_id_opcode[25:0]; // Index field
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wire[4:0] if_id_shamt = if_id_opcode[10:6]; // Shift amount
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wire[5:0] if_id_func = if_id_opcode[5:0]; // Function
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// True for still undecoded operations that read GPR[rs]
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wire if_id_reads_rs = (
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if_id_op==`OPCODE_BEQ || if_id_op==`OPCODE_BNE || if_id_op==`OPCODE_BLEZ || if_id_op==`OPCODE_BGTZ ||
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if_id_op==`OPCODE_ADDI || if_id_op==`OPCODE_ADDIU || if_id_op==`OPCODE_SLTI || if_id_op==`OPCODE_SLTIU ||
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if_id_op==`OPCODE_ANDI || if_id_op==`OPCODE_ORI || if_id_op==`OPCODE_XORI || if_id_op==`OPCODE_LB ||
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if_id_op==`OPCODE_LH || if_id_op==`OPCODE_LWL || if_id_op==`OPCODE_LW || if_id_op==`OPCODE_LBU ||
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if_id_op==`OPCODE_LHU || if_id_op==`OPCODE_LWR || if_id_op==`OPCODE_SB || if_id_op==`OPCODE_SH ||
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if_id_op==`OPCODE_SWL || if_id_op==`OPCODE_SW || if_id_op==`OPCODE_SWR || (
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if_id_op==`OPCODE_SPECIAL && (
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if_id_func==`FUNCTION_SLLV || if_id_func==`FUNCTION_SRLV || if_id_func==`FUNCTION_SRAV ||
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if_id_func==`FUNCTION_JR || if_id_func==`FUNCTION_JALR || if_id_func==`FUNCTION_MTHI ||
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if_id_func==`FUNCTION_MTLO || if_id_func==`FUNCTION_MULT || if_id_func==`FUNCTION_MULTU ||
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if_id_func==`FUNCTION_DIV || if_id_func==`FUNCTION_DIVU || if_id_func==`FUNCTION_ADD ||
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if_id_func==`FUNCTION_ADDU || if_id_func==`FUNCTION_SUB || if_id_func==`FUNCTION_SUBU ||
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if_id_func==`FUNCTION_AND || if_id_func==`FUNCTION_OR || if_id_func==`FUNCTION_XOR ||
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if_id_func==`FUNCTION_NOR || if_id_func==`FUNCTION_SLT || if_id_func==`FUNCTION_SLTU
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)
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) || (
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if_id_op==`OPCODE_BCOND && (
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if_id_rt==`BCOND_BLTZ || if_id_rt==`BCOND_BGEZ || if_id_rt==`BCOND_BLTZAL || if_id_rt==`BCOND_BGEZAL
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)
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)
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);
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// True for still undecoded operations that read GPR[rt]
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wire if_id_reads_rt = (
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if_id_op==`OPCODE_BEQ || if_id_op==`OPCODE_BNE || if_id_op==`OPCODE_SB || if_id_op==`OPCODE_SH ||
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if_id_op==`OPCODE_SWL || if_id_op==`OPCODE_SW || if_id_op==`OPCODE_SWR || (
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if_id_op==`OPCODE_SPECIAL && (
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if_id_func==`FUNCTION_SLL || if_id_func==`FUNCTION_SRL || if_id_func==`FUNCTION_SRA ||
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if_id_func==`FUNCTION_SLLV || if_id_func==`FUNCTION_SRLV || if_id_func==`FUNCTION_SRAV ||
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if_id_func==`FUNCTION_MULT || if_id_func==`FUNCTION_MULTU || if_id_func==`FUNCTION_DIV ||
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if_id_func==`FUNCTION_DIVU || if_id_func==`FUNCTION_ADD || if_id_func==`FUNCTION_ADDU ||
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if_id_func==`FUNCTION_SUB || if_id_func==`FUNCTION_SUBU || if_id_func==`FUNCTION_AND ||
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if_id_func==`FUNCTION_OR || if_id_func==`FUNCTION_XOR || if_id_func==`FUNCTION_NOR ||
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if_id_func==`FUNCTION_SLT || if_id_func==`FUNCTION_SLTU
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)
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)
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);
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// True for still undecoded operations that read the HI register
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wire if_id_reads_hi = (if_id_op==`OPCODE_SPECIAL && if_id_func==`FUNCTION_MFHI);
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// True for still undecoded operations that read the LO register
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wire if_id_reads_lo = (if_id_op==`OPCODE_SPECIAL && if_id_func==`FUNCTION_MFLO);
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// Finally detect a RAW hazard
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wire raw_detected = (
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(if_id_reads_rs && if_id_rs!=0 &&
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(if_id_rs==id_ex_destreg || if_id_rs==ex_mem_destreg || if_id_rs==mem_wb_destreg)) ||
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(if_id_reads_rt && if_id_rt!=0 &&
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(if_id_rt==id_ex_destreg || if_id_rt==ex_mem_destreg || if_id_rt==mem_wb_destreg)) ||
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(if_id_reads_hi && (id_ex_desthi || ex_mem_desthi || mem_wb_desthi)) ||
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(if_id_reads_lo && (id_ex_destlo || ex_mem_destlo || mem_wb_destlo))
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);
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// Stall signals for all the stages
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wire if_stall, id_stall, ex_stall, mem_stall, wb_stall;
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assign if_stall = id_stall || !imem_done_i;
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assign id_stall = ex_stall || raw_detected;
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assign ex_stall = mem_stall || mul_busy || div_busy;
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assign mem_stall = wb_stall || ( (dmem_read_o||dmem_write_o) && !dmem_done_i);
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assign wb_stall = 0;
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// Index for GPR initialization
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integer i;
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/*
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* Sequential logic
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*/
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always @ (posedge sys_clock_i) begin
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// Initialize all the registers
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if (sys_reset_i==1) begin
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// GPRs initialization
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for(i=0; i<=31; i=i+1) GPR[i] <= 32'h00000000;
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// System registers
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PC <= `BOOT_ADDRESS;
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HI <= 0;
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LO <= 0;
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// Initialize ABP requests to instantiated modules
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mul_req_o <= 0;
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div_req_o <= 0;
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// Latch 1: IF/ID
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if_id_opcode <= `NOP;
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if_id_addr <= `BOOT_ADDRESS;
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if_id_addrnext <= 0;
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// Latch 2: ID/EX
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id_ex_opcode <= 0;
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id_ex_addr <= 0;
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id_ex_addrnext <= 0;
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id_ex_addrjump <= 0;
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id_ex_addrbranch <= 0;
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id_ex_alu_a <= 0;
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id_ex_alu_b <= 0;
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id_ex_alu_func <= `ALU_OP_ADD;
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id_ex_alu_signed <= 0;
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id_ex_branch <= 0;
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id_ex_jump <= 0;
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id_ex_jr <=0;
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id_ex_linked <= 0;
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id_ex_mult <= 0;
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id_ex_div <= 0;
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id_ex_load <= 0;
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id_ex_store <= 0;
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id_ex_size <= 0;
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id_ex_store_value <= 0;
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id_ex_destreg <= 0;
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id_ex_desthi <= 0;
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id_ex_destlo <= 0;
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ex_mem_opcode <= 0;
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ex_mem_addr <= 0;
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ex_mem_addrnext <= 0;
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ex_mem_addrjump <= 0;
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ex_mem_addrbranch <= 0;
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ex_mem_aluout <= 0;
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ex_mem_branch <= 0;
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ex_mem_jump <= 0;
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ex_mem_jr <= 0;
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ex_mem_linked <= 0;
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ex_mem_mult <= 0;
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ex_mem_div <= 0;
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ex_mem_load <= 0;
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ex_mem_store <= 0;
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ex_mem_store_value <= 0;
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ex_mem_store_sel <= 0;
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ex_mem_destreg <= 0;
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|
|
ex_mem_desthi <= 0;
|
293 |
|
|
ex_mem_destlo <= 0;
|
294 |
|
|
|
295 |
|
|
// Latch 4: MEM/WB
|
296 |
|
|
mem_wb_opcode <= 0;
|
297 |
|
|
mem_wb_addr <= 0;
|
298 |
|
|
mem_wb_addrnext <= 0;
|
299 |
|
|
mem_wb_value <= 0;
|
300 |
|
|
mem_wb_destreg <= 0;
|
301 |
|
|
mem_wb_desthi <= 0;
|
302 |
|
|
mem_wb_destlo <= 0;
|
303 |
|
|
|
304 |
|
|
end else begin
|
305 |
|
|
|
306 |
|
|
$display("================> Time %t <================", $time);
|
307 |
|
|
|
308 |
|
|
/*
|
309 |
|
|
* Pipeline Stage 1: Instruction Fetch (IF)
|
310 |
|
|
*
|
311 |
|
|
* READ/WRITE:
|
312 |
|
|
* - read memory
|
313 |
|
|
* - write the IF/ID latch
|
314 |
|
|
* - write the PC register
|
315 |
|
|
*
|
316 |
|
|
* DESCRIPTION:
|
317 |
|
|
* This stage usually reads the next instruction from the PC address in memory and
|
318 |
|
|
* then updates the PC value by incrementing it by 4.
|
319 |
|
|
* When a hazard is detected this stage is idle.
|
320 |
|
|
*/
|
321 |
|
|
|
322 |
|
|
// A RAW hazard will stall the CPU
|
323 |
|
|
if(if_stall) begin
|
324 |
|
|
|
325 |
|
|
if(id_stall) begin
|
326 |
|
|
$display("INFO: CPU(%m)-IF: Fetching stalled and latch kept for following stalled pipeline stage");
|
327 |
|
|
end else begin
|
328 |
|
|
$display("INFO: CPU(%m)-IF: Fetching stalled and bubble inserted for following running pipeline stage");
|
329 |
|
|
if_id_opcode <= `BUBBLE;
|
330 |
|
|
end
|
331 |
|
|
|
332 |
|
|
end else begin
|
333 |
|
|
|
334 |
|
|
// Branch taken: insert a bubble and increment PC
|
335 |
|
|
if(ex_mem_branch==1 && ex_mem_aluout==32'h00000001) begin
|
336 |
|
|
|
337 |
|
|
$display("INFO: CPU(%m)-IF: Bubble inserted due branch taken in EX/MEM instruction @ADDR=%X w/OPCODE=%X having ALUout=%X", ex_mem_addr, ex_mem_opcode, ex_mem_aluout);
|
338 |
|
|
if_id_opcode <= `BUBBLE;
|
339 |
|
|
PC <= ex_mem_addrbranch;
|
340 |
|
|
|
341 |
|
|
//Jump to the required immediate address
|
342 |
|
|
end else if(id_ex_jump==1) begin
|
343 |
|
|
|
344 |
|
|
$display("INFO: CPU(%m)-IF: Bubble inserted due to jump in ID/EX instruction @ADDR=%X w/OPCODE=%X", id_ex_addr, id_ex_opcode);
|
345 |
|
|
if_id_opcode <= `BUBBLE;
|
346 |
|
|
PC <= id_ex_addrjump;
|
347 |
|
|
|
348 |
|
|
// Jump to the required address stored in GPR
|
349 |
|
|
end else if(id_ex_jr==1) begin
|
350 |
|
|
|
351 |
|
|
$display("INFO: CPU(%m)-IF: Bubble inserted due to jump register in ID/EX instruction @ADDR=%X w/OPCODE=%X", id_ex_addr, id_ex_opcode);
|
352 |
|
|
if_id_opcode <= `BUBBLE;
|
353 |
|
|
PC <= id_ex_addrjr;
|
354 |
|
|
|
355 |
|
|
// Normal execution
|
356 |
|
|
end else begin
|
357 |
|
|
|
358 |
|
|
$display("INFO: CPU(%m)-IF: Fetched from Program Counter @ADDR=%h getting OPCODE=%X", PC, imem_data_i);
|
359 |
|
|
if_id_opcode <= imem_data_i;
|
360 |
|
|
if_id_addr <= PC;
|
361 |
|
|
if_id_addrnext <= PCnext;
|
362 |
|
|
PC <= PCnext;
|
363 |
|
|
|
364 |
|
|
end
|
365 |
|
|
end
|
366 |
|
|
|
367 |
|
|
/*
|
368 |
|
|
* Pipeline Stage 2: Instruction Decode (ID)
|
369 |
|
|
*
|
370 |
|
|
* READ/WRITE:
|
371 |
|
|
* - read the IF/ID latch
|
372 |
|
|
* - read the register file
|
373 |
|
|
* - write the ID/EX latch
|
374 |
|
|
*
|
375 |
|
|
* DESCRIPTION:
|
376 |
|
|
* This stage decodes the instruction and puts the values for the ALU inputs
|
377 |
|
|
*/
|
378 |
|
|
|
379 |
|
|
if(id_stall) begin
|
380 |
|
|
|
381 |
|
|
if(ex_stall) begin
|
382 |
|
|
$display("INFO: CPU(%m)-ID: Decoding stalled and latch kept for following stalled pipeline stage");
|
383 |
|
|
end else begin
|
384 |
|
|
$display("INFO: CPU(%m)-ID: Decoding stalled and bubble inserted for following running pipeline stage");
|
385 |
|
|
id_ex_opcode <=`BUBBLE;
|
386 |
|
|
id_ex_alu_a <= 0;
|
387 |
|
|
id_ex_alu_b <= 0;
|
388 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
389 |
|
|
id_ex_alu_signed <= 0;
|
390 |
|
|
id_ex_addr <= if_id_addr;
|
391 |
|
|
id_ex_addrnext <= 0;
|
392 |
|
|
id_ex_addrjump <= 0;
|
393 |
|
|
id_ex_addrbranch <= 0;
|
394 |
|
|
id_ex_branch <= 0;
|
395 |
|
|
id_ex_jump <= 0;
|
396 |
|
|
id_ex_jr <= 0;
|
397 |
|
|
id_ex_linked <= 0;
|
398 |
|
|
id_ex_mult <= 0;
|
399 |
|
|
id_ex_div <= 0;
|
400 |
|
|
id_ex_load <= 0;
|
401 |
|
|
id_ex_store <= 0;
|
402 |
|
|
id_ex_destreg <= 0;
|
403 |
|
|
id_ex_desthi <= 0;
|
404 |
|
|
id_ex_destlo <= 0;
|
405 |
|
|
end
|
406 |
|
|
end else begin
|
407 |
|
|
id_ex_opcode <= if_id_opcode;
|
408 |
|
|
id_ex_addr <= if_id_addr;
|
409 |
|
|
id_ex_addrnext <= if_id_addrnext;
|
410 |
|
|
id_ex_addrbranch <= if_id_addrnext + {if_id_imm_signext[29:0], 2'b00};
|
411 |
|
|
id_ex_addrjump <= {if_id_addr[31:28], if_id_index, 2'b00};
|
412 |
|
|
id_ex_addrjr <= GPR[if_id_rs];
|
413 |
|
|
|
414 |
|
|
if(if_id_opcode==`BUBBLE) begin
|
415 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BUBBLE", if_id_addr, if_id_opcode);
|
416 |
|
|
id_ex_alu_a <= 0;
|
417 |
|
|
id_ex_alu_b <= 0;
|
418 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
419 |
|
|
id_ex_alu_signed <= 0;
|
420 |
|
|
id_ex_branch <= 0;
|
421 |
|
|
id_ex_jump <= 0;
|
422 |
|
|
id_ex_jr <= 0;
|
423 |
|
|
id_ex_linked <= 0;
|
424 |
|
|
id_ex_mult <= 0;
|
425 |
|
|
id_ex_div <= 0;
|
426 |
|
|
id_ex_load <= 0;
|
427 |
|
|
id_ex_store <= 0;
|
428 |
|
|
id_ex_size <= 0;
|
429 |
|
|
id_ex_store_value <= 0;
|
430 |
|
|
id_ex_destreg <= 0;
|
431 |
|
|
id_ex_desthi <= 0;
|
432 |
|
|
id_ex_destlo <= 0;
|
433 |
|
|
end else case(if_id_op)
|
434 |
|
|
`OPCODE_J:
|
435 |
|
|
begin
|
436 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as J %h", if_id_addr, if_id_opcode, if_id_index);
|
437 |
|
|
id_ex_alu_a <= 0;
|
438 |
|
|
id_ex_alu_b <= 0;
|
439 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
440 |
|
|
id_ex_alu_signed <= 0;
|
441 |
|
|
id_ex_branch <= 0;
|
442 |
|
|
id_ex_jump <= 1;
|
443 |
|
|
id_ex_jr <= 0;
|
444 |
|
|
id_ex_linked <= 0;
|
445 |
|
|
id_ex_mult <= 0;
|
446 |
|
|
id_ex_div <= 0;
|
447 |
|
|
id_ex_load <= 0;
|
448 |
|
|
id_ex_store <= 0;
|
449 |
|
|
id_ex_size <= 0;
|
450 |
|
|
id_ex_store_value <= 0;
|
451 |
|
|
id_ex_destreg <= 0;
|
452 |
|
|
id_ex_desthi <= 0;
|
453 |
|
|
id_ex_destlo <= 0;
|
454 |
|
|
end
|
455 |
|
|
`OPCODE_JAL:
|
456 |
|
|
begin
|
457 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as JAL %h", if_id_addr, if_id_opcode, if_id_index);
|
458 |
|
|
id_ex_alu_a <= if_id_addrnext;
|
459 |
|
|
id_ex_alu_b <= 4;
|
460 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
461 |
|
|
id_ex_alu_signed <= 0;
|
462 |
|
|
id_ex_branch <= 0;
|
463 |
|
|
id_ex_jump <= 1;
|
464 |
|
|
id_ex_jr <= 0;
|
465 |
|
|
id_ex_linked <= 1;
|
466 |
|
|
id_ex_mult <= 0;
|
467 |
|
|
id_ex_div <= 0;
|
468 |
|
|
id_ex_load <= 0;
|
469 |
|
|
id_ex_store <= 0;
|
470 |
|
|
id_ex_size <= 0;
|
471 |
|
|
id_ex_store_value <= 0;
|
472 |
|
|
id_ex_destreg <= 31;
|
473 |
|
|
id_ex_desthi <= 0;
|
474 |
|
|
id_ex_destlo <= 0;
|
475 |
|
|
end
|
476 |
|
|
`OPCODE_BEQ:
|
477 |
|
|
begin
|
478 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BEQ r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_rt, if_id_imm_signext);
|
479 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
480 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
481 |
|
|
id_ex_alu_func <= `ALU_OP_SEQ;
|
482 |
|
|
id_ex_alu_signed <= 0;
|
483 |
|
|
id_ex_branch <= 1;
|
484 |
|
|
id_ex_jump <= 0;
|
485 |
|
|
id_ex_jr <= 0;
|
486 |
|
|
id_ex_linked <= 0;
|
487 |
|
|
id_ex_mult <= 0;
|
488 |
|
|
id_ex_div <= 0;
|
489 |
|
|
id_ex_load <= 0;
|
490 |
|
|
id_ex_store <= 0;
|
491 |
|
|
id_ex_size <= 0;
|
492 |
|
|
id_ex_store_value <= 0;
|
493 |
|
|
id_ex_destreg <= 0;
|
494 |
|
|
id_ex_desthi <= 0;
|
495 |
|
|
id_ex_destlo <= 0;
|
496 |
|
|
end
|
497 |
|
|
`OPCODE_BNE:
|
498 |
|
|
begin
|
499 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BNE r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_rt, if_id_imm_signext);
|
500 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
501 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
502 |
|
|
id_ex_alu_func <= `ALU_OP_SNE;
|
503 |
|
|
id_ex_alu_signed <= 0;
|
504 |
|
|
id_ex_branch <= 1;
|
505 |
|
|
id_ex_jump <= 0;
|
506 |
|
|
id_ex_jr <= 0;
|
507 |
|
|
id_ex_linked <= 0;
|
508 |
|
|
id_ex_mult <= 0;
|
509 |
|
|
id_ex_div <= 0;
|
510 |
|
|
id_ex_load <= 0;
|
511 |
|
|
id_ex_store <= 0;
|
512 |
|
|
id_ex_size <= 0;
|
513 |
|
|
id_ex_store_value <= 0;
|
514 |
|
|
id_ex_destreg <= 0;
|
515 |
|
|
id_ex_desthi <= 0;
|
516 |
|
|
id_ex_destlo <= 0;
|
517 |
|
|
end
|
518 |
|
|
`OPCODE_BLEZ:
|
519 |
|
|
begin
|
520 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BLEZ r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
|
521 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
522 |
|
|
id_ex_alu_b <= 0;
|
523 |
|
|
id_ex_alu_func <= `ALU_OP_SLE;
|
524 |
|
|
id_ex_alu_signed <= 0;
|
525 |
|
|
id_ex_branch <= 1;
|
526 |
|
|
id_ex_jump <= 0;
|
527 |
|
|
id_ex_jr <= 0;
|
528 |
|
|
id_ex_linked <= 0;
|
529 |
|
|
id_ex_mult <= 0;
|
530 |
|
|
id_ex_div <= 0;
|
531 |
|
|
id_ex_load <= 0;
|
532 |
|
|
id_ex_store <= 0;
|
533 |
|
|
id_ex_size <= 0;
|
534 |
|
|
id_ex_store_value <= 0;
|
535 |
|
|
id_ex_destreg <= 0;
|
536 |
|
|
id_ex_desthi <= 0;
|
537 |
|
|
id_ex_destlo <= 0;
|
538 |
|
|
end
|
539 |
|
|
`OPCODE_BGTZ:
|
540 |
|
|
begin
|
541 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BGTZ r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
|
542 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
543 |
|
|
id_ex_alu_b <= 0;
|
544 |
|
|
id_ex_alu_func <= `ALU_OP_SGT;
|
545 |
|
|
id_ex_alu_signed <= 0;
|
546 |
|
|
id_ex_branch <= 1;
|
547 |
|
|
id_ex_jump <= 0;
|
548 |
|
|
id_ex_jr <= 0;
|
549 |
|
|
id_ex_linked <= 0;
|
550 |
|
|
id_ex_mult <= 0;
|
551 |
|
|
id_ex_div <= 0;
|
552 |
|
|
id_ex_load <= 0;
|
553 |
|
|
id_ex_store <= 0;
|
554 |
|
|
id_ex_size <= 0;
|
555 |
|
|
id_ex_store_value <= 0;
|
556 |
|
|
id_ex_destreg <= 0;
|
557 |
|
|
id_ex_desthi <= 0;
|
558 |
|
|
id_ex_destlo <= 0;
|
559 |
|
|
end
|
560 |
|
|
`OPCODE_ADDI:
|
561 |
|
|
begin
|
562 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ADDI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);
|
563 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
564 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
565 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
566 |
|
|
id_ex_alu_signed <= 1;
|
567 |
|
|
id_ex_branch <= 0;
|
568 |
|
|
id_ex_jump <= 0;
|
569 |
|
|
id_ex_jr <= 0;
|
570 |
|
|
id_ex_linked <= 0;
|
571 |
|
|
id_ex_mult <= 0;
|
572 |
|
|
id_ex_div <= 0;
|
573 |
|
|
id_ex_load <= 0;
|
574 |
|
|
id_ex_store <= 0;
|
575 |
|
|
id_ex_size <= 0;
|
576 |
|
|
id_ex_store_value <= 0;
|
577 |
|
|
id_ex_destreg <= if_id_rt;
|
578 |
|
|
id_ex_desthi <= 0;
|
579 |
|
|
id_ex_destlo <= 0;
|
580 |
|
|
end
|
581 |
|
|
`OPCODE_ADDIU:
|
582 |
|
|
begin
|
583 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ADDIU r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);
|
584 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
585 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
586 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
587 |
|
|
id_ex_alu_signed <= 0;
|
588 |
|
|
id_ex_branch <= 0;
|
589 |
|
|
id_ex_jump <= 0;
|
590 |
|
|
id_ex_jr <= 0;
|
591 |
|
|
id_ex_linked <= 0;
|
592 |
|
|
id_ex_mult <= 0;
|
593 |
|
|
id_ex_div <= 0;
|
594 |
|
|
id_ex_load <= 0;
|
595 |
|
|
id_ex_store <= 0;
|
596 |
|
|
id_ex_size <= 0;
|
597 |
|
|
id_ex_store_value <= 0;
|
598 |
|
|
id_ex_destreg <= if_id_rt;
|
599 |
|
|
id_ex_desthi <= 0;
|
600 |
|
|
id_ex_destlo <= 0;
|
601 |
|
|
end
|
602 |
|
|
`OPCODE_SLTI:
|
603 |
|
|
begin
|
604 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLTI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);
|
605 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
606 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
607 |
|
|
id_ex_alu_func <= `ALU_OP_SLT;
|
608 |
|
|
id_ex_alu_signed <= 1;
|
609 |
|
|
id_ex_branch <= 0;
|
610 |
|
|
id_ex_jump <= 0;
|
611 |
|
|
id_ex_jr <= 0;
|
612 |
|
|
id_ex_linked <= 0;
|
613 |
|
|
id_ex_mult <= 0;
|
614 |
|
|
id_ex_div <= 0;
|
615 |
|
|
id_ex_load <= 0;
|
616 |
|
|
id_ex_store <= 0;
|
617 |
|
|
id_ex_size <= 0;
|
618 |
|
|
id_ex_store_value <= 0;
|
619 |
|
|
id_ex_destreg <= if_id_rt;
|
620 |
|
|
id_ex_desthi <= 0;
|
621 |
|
|
id_ex_destlo <= 0;
|
622 |
|
|
end
|
623 |
|
|
`OPCODE_SLTIU:
|
624 |
|
|
begin
|
625 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLTIU r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);
|
626 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
627 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
628 |
|
|
id_ex_alu_func <= `ALU_OP_SLT;
|
629 |
|
|
id_ex_alu_signed <= 0;
|
630 |
|
|
id_ex_branch <= 0;
|
631 |
|
|
id_ex_jump <= 0;
|
632 |
|
|
id_ex_jr <= 0;
|
633 |
|
|
id_ex_linked <= 0;
|
634 |
|
|
id_ex_mult <= 0;
|
635 |
|
|
id_ex_div <= 0;
|
636 |
|
|
id_ex_load <= 0;
|
637 |
|
|
id_ex_store <= 0;
|
638 |
|
|
id_ex_size <= 0;
|
639 |
|
|
id_ex_store_value <= 0;
|
640 |
|
|
id_ex_destreg <= if_id_rt;
|
641 |
|
|
id_ex_desthi <= 0;
|
642 |
|
|
id_ex_destlo <= 0;
|
643 |
|
|
end
|
644 |
|
|
`OPCODE_ANDI:
|
645 |
|
|
begin
|
646 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ANDI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_zeroext);
|
647 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
648 |
|
|
id_ex_alu_b <= if_id_imm_zeroext;
|
649 |
|
|
id_ex_alu_func <= `ALU_OP_AND;
|
650 |
|
|
id_ex_alu_signed <= 0;
|
651 |
|
|
id_ex_branch <= 0;
|
652 |
|
|
id_ex_jump <= 0;
|
653 |
|
|
id_ex_jr <= 0;
|
654 |
|
|
id_ex_linked <= 0;
|
655 |
|
|
id_ex_mult <= 0;
|
656 |
|
|
id_ex_div <= 0;
|
657 |
|
|
id_ex_load <= 0;
|
658 |
|
|
id_ex_store <= 0;
|
659 |
|
|
id_ex_size <= 0;
|
660 |
|
|
id_ex_store_value <= 0;
|
661 |
|
|
id_ex_destreg <= if_id_rt;
|
662 |
|
|
id_ex_desthi <= 0;
|
663 |
|
|
id_ex_destlo <= 0;
|
664 |
|
|
end
|
665 |
|
|
`OPCODE_ORI:
|
666 |
|
|
begin
|
667 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ORI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_zeroext);
|
668 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
669 |
|
|
id_ex_alu_b <= if_id_imm_zeroext;
|
670 |
|
|
id_ex_alu_func <= `ALU_OP_OR;
|
671 |
|
|
id_ex_alu_signed <= 0;
|
672 |
|
|
id_ex_branch <= 0;
|
673 |
|
|
id_ex_jump <= 0;
|
674 |
|
|
id_ex_jr <= 0;
|
675 |
|
|
id_ex_linked <= 0;
|
676 |
|
|
id_ex_mult <= 0;
|
677 |
|
|
id_ex_div <= 0;
|
678 |
|
|
id_ex_load <= 0;
|
679 |
|
|
id_ex_store <= 0;
|
680 |
|
|
id_ex_size <= 0;
|
681 |
|
|
id_ex_store_value <= 0;
|
682 |
|
|
id_ex_destreg <= if_id_rt;
|
683 |
|
|
id_ex_desthi <= 0;
|
684 |
|
|
id_ex_destlo <= 0;
|
685 |
|
|
end
|
686 |
|
|
`OPCODE_XORI:
|
687 |
|
|
begin
|
688 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as XORI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_zeroext);
|
689 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
690 |
|
|
id_ex_alu_b <= if_id_imm_zeroext;
|
691 |
|
|
id_ex_alu_func <= `ALU_OP_XOR;
|
692 |
|
|
id_ex_alu_signed <= 0;
|
693 |
|
|
id_ex_branch <= 0;
|
694 |
|
|
id_ex_jump <= 0;
|
695 |
|
|
id_ex_jr <= 0;
|
696 |
|
|
id_ex_linked <= 0;
|
697 |
|
|
id_ex_mult <= 0;
|
698 |
|
|
id_ex_div <= 0;
|
699 |
|
|
id_ex_load <= 0;
|
700 |
|
|
id_ex_store <= 0;
|
701 |
|
|
id_ex_size <= 0;
|
702 |
|
|
id_ex_store_value <= 0;
|
703 |
|
|
id_ex_destreg <= if_id_rt;
|
704 |
|
|
id_ex_desthi <= 0;
|
705 |
|
|
id_ex_destlo <= 0;
|
706 |
|
|
end
|
707 |
|
|
`OPCODE_LUI:
|
708 |
|
|
begin
|
709 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LUI r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_zeroext);
|
710 |
|
|
id_ex_alu_a <= if_id_imm_zeroext;
|
711 |
|
|
id_ex_alu_b <= 16;
|
712 |
|
|
id_ex_alu_func <= `ALU_OP_SLL;
|
713 |
|
|
id_ex_alu_signed <= 0;
|
714 |
|
|
id_ex_branch <= 0;
|
715 |
|
|
id_ex_jump <= 0;
|
716 |
|
|
id_ex_jr <= 0;
|
717 |
|
|
id_ex_linked <= 0;
|
718 |
|
|
id_ex_mult <= 0;
|
719 |
|
|
id_ex_div <= 0;
|
720 |
|
|
id_ex_load <= 0;
|
721 |
|
|
id_ex_store <= 0;
|
722 |
|
|
id_ex_size <= 0;
|
723 |
|
|
id_ex_store_value <= 0;
|
724 |
|
|
id_ex_destreg <= if_id_rt;
|
725 |
|
|
id_ex_desthi <= 0;
|
726 |
|
|
id_ex_destlo <= 0;
|
727 |
|
|
end
|
728 |
|
|
`OPCODE_COP0:
|
729 |
|
|
begin
|
730 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as COP0", if_id_addr, if_id_opcode);
|
731 |
|
|
end
|
732 |
|
|
`OPCODE_COP1:
|
733 |
|
|
begin
|
734 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as COP1", if_id_addr, if_id_opcode);
|
735 |
|
|
end
|
736 |
|
|
`OPCODE_COP2:
|
737 |
|
|
begin
|
738 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as COP2", if_id_addr, if_id_opcode);
|
739 |
|
|
end
|
740 |
|
|
`OPCODE_COP3:
|
741 |
|
|
begin
|
742 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as COP3", if_id_addr, if_id_opcode);
|
743 |
|
|
end
|
744 |
|
|
`OPCODE_LB:
|
745 |
|
|
begin
|
746 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LB r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
747 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
748 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
749 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
750 |
|
|
id_ex_alu_signed <= 1;
|
751 |
|
|
id_ex_branch <= 0;
|
752 |
|
|
id_ex_jump <= 0;
|
753 |
|
|
id_ex_jr <= 0;
|
754 |
|
|
id_ex_linked <= 0;
|
755 |
|
|
id_ex_mult <= 0;
|
756 |
|
|
id_ex_div <= 0;
|
757 |
|
|
id_ex_load <= 1;
|
758 |
|
|
id_ex_store <= 0;
|
759 |
|
|
id_ex_size <= `SIZE_BYTE;
|
760 |
|
|
id_ex_store_value <= 0;
|
761 |
|
|
id_ex_destreg <= if_id_rt;
|
762 |
|
|
id_ex_desthi <= 0;
|
763 |
|
|
id_ex_destlo <= 0;
|
764 |
|
|
end
|
765 |
|
|
`OPCODE_LH:
|
766 |
|
|
begin
|
767 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LH r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
768 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
769 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
770 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
771 |
|
|
id_ex_alu_signed <= 1;
|
772 |
|
|
id_ex_branch <= 0;
|
773 |
|
|
id_ex_jump <= 0;
|
774 |
|
|
id_ex_jr <= 0;
|
775 |
|
|
id_ex_linked <= 0;
|
776 |
|
|
id_ex_mult <= 0;
|
777 |
|
|
id_ex_div <= 0;
|
778 |
|
|
id_ex_load <= 1;
|
779 |
|
|
id_ex_store <= 0;
|
780 |
|
|
id_ex_size <= `SIZE_HALF;
|
781 |
|
|
id_ex_store_value <= 0;
|
782 |
|
|
id_ex_destreg <= if_id_rt;
|
783 |
|
|
id_ex_desthi <= 0;
|
784 |
|
|
id_ex_destlo <= 0;
|
785 |
|
|
end
|
786 |
|
|
`OPCODE_LWL:
|
787 |
|
|
begin
|
788 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LWL r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
789 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
790 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
791 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
792 |
|
|
id_ex_alu_signed <= 1;
|
793 |
|
|
id_ex_branch <= 0;
|
794 |
|
|
id_ex_jump <= 0;
|
795 |
|
|
id_ex_jr <= 0;
|
796 |
|
|
id_ex_linked <= 0;
|
797 |
|
|
id_ex_mult <= 0;
|
798 |
|
|
id_ex_div <= 0;
|
799 |
|
|
id_ex_load <= 1;
|
800 |
|
|
id_ex_store <= 0;
|
801 |
|
|
id_ex_size <= `SIZE_LEFT;
|
802 |
|
|
id_ex_store_value <= 0;
|
803 |
|
|
id_ex_destreg <= if_id_rt;
|
804 |
|
|
id_ex_desthi <= 0;
|
805 |
|
|
id_ex_destlo <= 0;
|
806 |
|
|
end
|
807 |
|
|
`OPCODE_LW:
|
808 |
|
|
begin
|
809 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LW r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
810 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
811 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
812 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
813 |
|
|
id_ex_alu_signed <= 1;
|
814 |
|
|
id_ex_branch <= 0;
|
815 |
|
|
id_ex_jump <= 0;
|
816 |
|
|
id_ex_jr <= 0;
|
817 |
|
|
id_ex_linked <= 0;
|
818 |
|
|
id_ex_mult <= 0;
|
819 |
|
|
id_ex_div <= 0;
|
820 |
|
|
id_ex_load <= 1;
|
821 |
|
|
id_ex_store <= 0;
|
822 |
|
|
id_ex_size <= `SIZE_WORD;
|
823 |
|
|
id_ex_store_value <= 0;
|
824 |
|
|
id_ex_destreg <= if_id_rt;
|
825 |
|
|
id_ex_desthi <= 0;
|
826 |
|
|
id_ex_destlo <= 0;
|
827 |
|
|
end
|
828 |
|
|
`OPCODE_LBU:
|
829 |
|
|
begin
|
830 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LBU r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
831 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
832 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
833 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
834 |
|
|
id_ex_alu_signed <= 0;
|
835 |
|
|
id_ex_branch <= 0;
|
836 |
|
|
id_ex_jump <= 0;
|
837 |
|
|
id_ex_jr <= 0;
|
838 |
|
|
id_ex_linked <= 0;
|
839 |
|
|
id_ex_mult <= 0;
|
840 |
|
|
id_ex_div <= 0;
|
841 |
|
|
id_ex_load <= 1;
|
842 |
|
|
id_ex_store <= 0;
|
843 |
|
|
id_ex_size <= `SIZE_BYTE;
|
844 |
|
|
id_ex_store_value <= 0;
|
845 |
|
|
id_ex_destreg <= if_id_rt;
|
846 |
|
|
id_ex_desthi <= 0;
|
847 |
|
|
id_ex_destlo <= 0;
|
848 |
|
|
end
|
849 |
|
|
`OPCODE_LHU:
|
850 |
|
|
begin
|
851 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LHU r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
852 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
853 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
854 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
855 |
|
|
id_ex_alu_signed <= 0;
|
856 |
|
|
id_ex_branch <= 0;
|
857 |
|
|
id_ex_jump <= 0;
|
858 |
|
|
id_ex_jr <= 0;
|
859 |
|
|
id_ex_linked <= 0;
|
860 |
|
|
id_ex_mult <= 0;
|
861 |
|
|
id_ex_div <= 0;
|
862 |
|
|
id_ex_load <= 1;
|
863 |
|
|
id_ex_store <= 0;
|
864 |
|
|
id_ex_size <= `SIZE_HALF;
|
865 |
|
|
id_ex_store_value <= 0;
|
866 |
|
|
id_ex_destreg <= if_id_rt;
|
867 |
|
|
id_ex_desthi <= 0;
|
868 |
|
|
id_ex_destlo <= 0;
|
869 |
|
|
end
|
870 |
|
|
`OPCODE_LWR:
|
871 |
|
|
begin
|
872 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LWR r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
873 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
874 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
875 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
876 |
|
|
id_ex_alu_signed <= 1;
|
877 |
|
|
id_ex_branch <= 0;
|
878 |
|
|
id_ex_jump <= 0;
|
879 |
|
|
id_ex_jr <= 0;
|
880 |
|
|
id_ex_linked <= 0;
|
881 |
|
|
id_ex_mult <= 0;
|
882 |
|
|
id_ex_div <= 0;
|
883 |
|
|
id_ex_load <= 1;
|
884 |
|
|
id_ex_store <= 0;
|
885 |
|
|
id_ex_size <= `SIZE_RIGHT;
|
886 |
|
|
id_ex_store_value <= 0;
|
887 |
|
|
id_ex_destreg <= if_id_rt;
|
888 |
|
|
id_ex_desthi <= 0;
|
889 |
|
|
id_ex_destlo <= 0;
|
890 |
|
|
end
|
891 |
|
|
`OPCODE_SB:
|
892 |
|
|
begin
|
893 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SB r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
894 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
895 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
896 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
897 |
|
|
id_ex_alu_signed <= 1;
|
898 |
|
|
id_ex_branch <= 0;
|
899 |
|
|
id_ex_jump <= 0;
|
900 |
|
|
id_ex_jr <= 0;
|
901 |
|
|
id_ex_linked <= 0;
|
902 |
|
|
id_ex_mult <= 0;
|
903 |
|
|
id_ex_div <= 0;
|
904 |
|
|
id_ex_load <= 0;
|
905 |
|
|
id_ex_store <= 1;
|
906 |
|
|
id_ex_size <= `SIZE_BYTE;
|
907 |
|
|
id_ex_store_value <= GPR[if_id_rt];
|
908 |
|
|
id_ex_destreg <= 0;
|
909 |
|
|
id_ex_desthi <= 0;
|
910 |
|
|
id_ex_destlo <= 0;
|
911 |
|
|
end
|
912 |
|
|
`OPCODE_SH:
|
913 |
|
|
begin
|
914 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SH r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
915 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
916 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
917 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
918 |
|
|
id_ex_alu_signed <= 1;
|
919 |
|
|
id_ex_branch <= 0;
|
920 |
|
|
id_ex_jump <= 0;
|
921 |
|
|
id_ex_jr <= 0;
|
922 |
|
|
id_ex_linked <= 0;
|
923 |
|
|
id_ex_mult <= 0;
|
924 |
|
|
id_ex_div <= 0;
|
925 |
|
|
id_ex_load <= 0;
|
926 |
|
|
id_ex_store <= 1;
|
927 |
|
|
id_ex_size <= `SIZE_HALF;
|
928 |
|
|
id_ex_store_value <= GPR[if_id_rt];
|
929 |
|
|
id_ex_destreg <= 0;
|
930 |
|
|
id_ex_desthi <= 0;
|
931 |
|
|
id_ex_destlo <= 0;
|
932 |
|
|
end
|
933 |
|
|
`OPCODE_SWL:
|
934 |
|
|
begin
|
935 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SWL r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
936 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
937 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
938 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
939 |
|
|
id_ex_alu_signed <= 1;
|
940 |
|
|
id_ex_branch <= 0;
|
941 |
|
|
id_ex_jump <= 0;
|
942 |
|
|
id_ex_jr <= 0;
|
943 |
|
|
id_ex_linked <= 0;
|
944 |
|
|
id_ex_mult <= 0;
|
945 |
|
|
id_ex_div <= 0;
|
946 |
|
|
id_ex_load <= 0;
|
947 |
|
|
id_ex_store <= 1;
|
948 |
|
|
id_ex_size <= `SIZE_LEFT;
|
949 |
|
|
id_ex_store_value <= GPR[if_id_rt];
|
950 |
|
|
id_ex_destreg <= 0;
|
951 |
|
|
id_ex_desthi <= 0;
|
952 |
|
|
id_ex_destlo <= 0;
|
953 |
|
|
end
|
954 |
|
|
`OPCODE_SW:
|
955 |
|
|
begin
|
956 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SW r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
957 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
958 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
959 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
960 |
|
|
id_ex_alu_signed <= 1;
|
961 |
|
|
id_ex_branch <= 0;
|
962 |
|
|
id_ex_jump <= 0;
|
963 |
|
|
id_ex_jr <= 0;
|
964 |
|
|
id_ex_linked <= 0;
|
965 |
|
|
id_ex_mult <= 0;
|
966 |
|
|
id_ex_div <= 0;
|
967 |
|
|
id_ex_load <= 0;
|
968 |
|
|
id_ex_store <= 1;
|
969 |
|
|
id_ex_size <= `SIZE_WORD;
|
970 |
|
|
id_ex_store_value <= GPR[if_id_rt];
|
971 |
|
|
id_ex_destreg <= 0;
|
972 |
|
|
id_ex_desthi <= 0;
|
973 |
|
|
id_ex_destlo <= 0;
|
974 |
|
|
end
|
975 |
|
|
`OPCODE_SWR:
|
976 |
|
|
begin
|
977 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SWR r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
|
978 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
979 |
|
|
id_ex_alu_b <= if_id_imm_signext;
|
980 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
981 |
|
|
id_ex_alu_signed <= 1;
|
982 |
|
|
id_ex_branch <= 0;
|
983 |
|
|
id_ex_jump <= 0;
|
984 |
|
|
id_ex_jr <= 0;
|
985 |
|
|
id_ex_linked <= 0;
|
986 |
|
|
id_ex_mult <= 0;
|
987 |
|
|
id_ex_div <= 0;
|
988 |
|
|
id_ex_load <= 0;
|
989 |
|
|
id_ex_store <= 1;
|
990 |
|
|
id_ex_size <= `SIZE_RIGHT;
|
991 |
|
|
id_ex_store_value <= GPR[if_id_rt];
|
992 |
|
|
id_ex_destreg <= 0;
|
993 |
|
|
id_ex_desthi <= 0;
|
994 |
|
|
id_ex_destlo <= 0;
|
995 |
|
|
end
|
996 |
|
|
`OPCODE_LWC1:
|
997 |
|
|
begin
|
998 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LWC1", if_id_addr, if_id_opcode);
|
999 |
|
|
end
|
1000 |
|
|
`OPCODE_LWC2:
|
1001 |
|
|
begin
|
1002 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LWC2", if_id_addr, if_id_opcode);
|
1003 |
|
|
end
|
1004 |
|
|
`OPCODE_LWC3:
|
1005 |
|
|
begin
|
1006 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LWC3", if_id_addr, if_id_opcode);
|
1007 |
|
|
end
|
1008 |
|
|
`OPCODE_SWC1:
|
1009 |
|
|
begin
|
1010 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SWC1", if_id_addr, if_id_opcode);
|
1011 |
|
|
end
|
1012 |
|
|
`OPCODE_SWC2:
|
1013 |
|
|
begin
|
1014 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SWC2", if_id_addr, if_id_opcode);
|
1015 |
|
|
end
|
1016 |
|
|
`OPCODE_SWC3:
|
1017 |
|
|
begin
|
1018 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SWC3", if_id_addr, if_id_opcode);
|
1019 |
|
|
end
|
1020 |
|
|
`OPCODE_SPECIAL:
|
1021 |
|
|
case(if_id_func)
|
1022 |
|
|
`FUNCTION_SLL:
|
1023 |
|
|
begin
|
1024 |
|
|
if(if_id_opcode==`NOP) $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as NOP", if_id_addr, if_id_opcode);
|
1025 |
|
|
else $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLL r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_shamt);
|
1026 |
|
|
id_ex_alu_a <= GPR[if_id_rt];
|
1027 |
|
|
id_ex_alu_b <= if_id_shamt;
|
1028 |
|
|
id_ex_alu_func <= `ALU_OP_SLL;
|
1029 |
|
|
id_ex_alu_signed <= 0;
|
1030 |
|
|
id_ex_branch <= 0;
|
1031 |
|
|
id_ex_jump <= 0;
|
1032 |
|
|
id_ex_jr <= 0;
|
1033 |
|
|
id_ex_linked <= 0;
|
1034 |
|
|
id_ex_mult <= 0;
|
1035 |
|
|
id_ex_div <= 0;
|
1036 |
|
|
id_ex_load <= 0;
|
1037 |
|
|
id_ex_store <= 0;
|
1038 |
|
|
id_ex_size <= 0;
|
1039 |
|
|
id_ex_store_value <= 0;
|
1040 |
|
|
id_ex_destreg <= if_id_rd;
|
1041 |
|
|
id_ex_desthi <= 0;
|
1042 |
|
|
id_ex_destlo <= 0;
|
1043 |
|
|
end
|
1044 |
|
|
`FUNCTION_SRL:
|
1045 |
|
|
begin
|
1046 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SRL r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_shamt);
|
1047 |
|
|
id_ex_alu_a <= GPR[if_id_rt];
|
1048 |
|
|
id_ex_alu_b <= if_id_shamt;
|
1049 |
|
|
id_ex_alu_func <= `ALU_OP_SRL;
|
1050 |
|
|
id_ex_alu_signed <= 0;
|
1051 |
|
|
id_ex_branch <= 0;
|
1052 |
|
|
id_ex_jump <= 0;
|
1053 |
|
|
id_ex_jr <= 0;
|
1054 |
|
|
id_ex_linked <= 0;
|
1055 |
|
|
id_ex_mult <= 0;
|
1056 |
|
|
id_ex_div <= 0;
|
1057 |
|
|
id_ex_load <= 0;
|
1058 |
|
|
id_ex_store <= 0;
|
1059 |
|
|
id_ex_size <= 0;
|
1060 |
|
|
id_ex_store_value <= 0;
|
1061 |
|
|
id_ex_destreg <= if_id_rd;
|
1062 |
|
|
id_ex_desthi <= 0;
|
1063 |
|
|
id_ex_destlo <= 0;
|
1064 |
|
|
end
|
1065 |
|
|
`FUNCTION_SRA:
|
1066 |
|
|
begin
|
1067 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SRA r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_shamt);
|
1068 |
|
|
id_ex_alu_a <= GPR[if_id_rt];
|
1069 |
|
|
id_ex_alu_b <= if_id_shamt;
|
1070 |
|
|
id_ex_alu_func <= `ALU_OP_SRA;
|
1071 |
|
|
id_ex_alu_signed <= 1; // does nothing??
|
1072 |
|
|
id_ex_branch <= 0;
|
1073 |
|
|
id_ex_jump <= 0;
|
1074 |
|
|
id_ex_jr <= 0;
|
1075 |
|
|
id_ex_linked <= 0;
|
1076 |
|
|
id_ex_mult <= 0;
|
1077 |
|
|
id_ex_div <= 0;
|
1078 |
|
|
id_ex_load <= 0;
|
1079 |
|
|
id_ex_store <= 0;
|
1080 |
|
|
id_ex_size <= 0;
|
1081 |
|
|
id_ex_store_value <= 0;
|
1082 |
|
|
id_ex_destreg <= if_id_rd;
|
1083 |
|
|
id_ex_desthi <= 0;
|
1084 |
|
|
id_ex_destlo <= 0;
|
1085 |
|
|
end
|
1086 |
|
|
`FUNCTION_SLLV:
|
1087 |
|
|
begin
|
1088 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLLV r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_rs);
|
1089 |
|
|
id_ex_alu_a <= GPR[if_id_rt];
|
1090 |
|
|
id_ex_alu_b <= GPR[if_id_rs];
|
1091 |
|
|
id_ex_alu_func <= `ALU_OP_SLL;
|
1092 |
|
|
id_ex_alu_signed <= 0;
|
1093 |
|
|
id_ex_branch <= 0;
|
1094 |
|
|
id_ex_jump <= 0;
|
1095 |
|
|
id_ex_jr <= 0;
|
1096 |
|
|
id_ex_linked <= 0;
|
1097 |
|
|
id_ex_mult <= 0;
|
1098 |
|
|
id_ex_div <= 0;
|
1099 |
|
|
id_ex_load <= 0;
|
1100 |
|
|
id_ex_store <= 0;
|
1101 |
|
|
id_ex_size <= 0;
|
1102 |
|
|
id_ex_store_value <= 0;
|
1103 |
|
|
id_ex_destreg <= if_id_rd;
|
1104 |
|
|
id_ex_desthi <= 0;
|
1105 |
|
|
id_ex_destlo <= 0;
|
1106 |
|
|
end
|
1107 |
|
|
`FUNCTION_SRLV:
|
1108 |
|
|
begin
|
1109 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SRLV r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_rs);
|
1110 |
|
|
id_ex_alu_a <= GPR[if_id_rt];
|
1111 |
|
|
id_ex_alu_b <= GPR[if_id_rs];
|
1112 |
|
|
id_ex_alu_func <= `ALU_OP_SRL;
|
1113 |
|
|
id_ex_alu_signed <= 0;
|
1114 |
|
|
id_ex_branch <= 0;
|
1115 |
|
|
id_ex_jump <= 0;
|
1116 |
|
|
id_ex_jr <= 0;
|
1117 |
|
|
id_ex_linked <= 0;
|
1118 |
|
|
id_ex_mult <= 0;
|
1119 |
|
|
id_ex_div <= 0;
|
1120 |
|
|
id_ex_load <= 0;
|
1121 |
|
|
id_ex_store <= 0;
|
1122 |
|
|
id_ex_size <= 0;
|
1123 |
|
|
id_ex_store_value <= 0;
|
1124 |
|
|
id_ex_destreg <= if_id_rd;
|
1125 |
|
|
id_ex_desthi <= 0;
|
1126 |
|
|
id_ex_destlo <= 0;
|
1127 |
|
|
end
|
1128 |
|
|
`FUNCTION_SRAV:
|
1129 |
|
|
begin
|
1130 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SRAV r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_rs);
|
1131 |
|
|
id_ex_alu_a <= GPR[if_id_rt];
|
1132 |
|
|
id_ex_alu_b <= GPR[if_id_rs];
|
1133 |
|
|
id_ex_alu_func <= `ALU_OP_SRA;
|
1134 |
|
|
id_ex_alu_signed <= 1;
|
1135 |
|
|
id_ex_branch <= 0;
|
1136 |
|
|
id_ex_jump <= 0;
|
1137 |
|
|
id_ex_jr <= 0;
|
1138 |
|
|
id_ex_linked <= 0;
|
1139 |
|
|
id_ex_mult <= 0;
|
1140 |
|
|
id_ex_div <= 0;
|
1141 |
|
|
id_ex_load <= 0;
|
1142 |
|
|
id_ex_store <= 0;
|
1143 |
|
|
id_ex_size <= 0;
|
1144 |
|
|
id_ex_store_value <= 0;
|
1145 |
|
|
id_ex_destreg <= if_id_rd;
|
1146 |
|
|
id_ex_desthi <= 0;
|
1147 |
|
|
id_ex_destlo <= 0;
|
1148 |
|
|
end
|
1149 |
|
|
`FUNCTION_JR:
|
1150 |
|
|
begin
|
1151 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as JR r%d", if_id_addr, if_id_opcode, if_id_rs);
|
1152 |
|
|
id_ex_alu_a <= 0;
|
1153 |
|
|
id_ex_alu_b <= 0;
|
1154 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
1155 |
|
|
id_ex_alu_signed <= 0;
|
1156 |
|
|
id_ex_branch <= 0;
|
1157 |
|
|
id_ex_jump <= 0;
|
1158 |
|
|
id_ex_jr <= 1;
|
1159 |
|
|
id_ex_linked <= 0;
|
1160 |
|
|
id_ex_mult <= 0;
|
1161 |
|
|
id_ex_div <= 0;
|
1162 |
|
|
id_ex_load <= 0;
|
1163 |
|
|
id_ex_store <= 0;
|
1164 |
|
|
id_ex_size <= 0;
|
1165 |
|
|
id_ex_store_value <= 0;
|
1166 |
|
|
id_ex_destreg <= 0;
|
1167 |
|
|
id_ex_desthi <= 0;
|
1168 |
|
|
id_ex_destlo <= 0;
|
1169 |
|
|
end
|
1170 |
|
|
`FUNCTION_JALR:
|
1171 |
|
|
begin
|
1172 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as JALR [r%d,] r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs);
|
1173 |
|
|
id_ex_alu_a <= if_id_addrnext;
|
1174 |
|
|
id_ex_alu_b <= 4;
|
1175 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
1176 |
|
|
id_ex_alu_signed <= 0;
|
1177 |
|
|
id_ex_branch <= 0;
|
1178 |
|
|
id_ex_jump <= 0;
|
1179 |
|
|
id_ex_jr <= 1;
|
1180 |
|
|
id_ex_linked <= 1;
|
1181 |
|
|
id_ex_mult <= 0;
|
1182 |
|
|
id_ex_div <= 0;
|
1183 |
|
|
id_ex_load <= 0;
|
1184 |
|
|
id_ex_store <= 0;
|
1185 |
|
|
id_ex_size <= 0;
|
1186 |
|
|
id_ex_store_value <= 0;
|
1187 |
|
|
id_ex_destreg <= if_id_rd;
|
1188 |
|
|
id_ex_desthi <= 0;
|
1189 |
|
|
id_ex_destlo <= 0;
|
1190 |
|
|
end
|
1191 |
|
|
`FUNCTION_SYSCALL:
|
1192 |
|
|
begin
|
1193 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SYSCALL", if_id_addr, if_id_opcode);
|
1194 |
|
|
// id_ex_alu_a <= 0;
|
1195 |
|
|
// id_ex_alu_b <= 0;
|
1196 |
|
|
// id_ex_alu_func <= `ALU_OP_ADD;
|
1197 |
|
|
// id_ex_alu_signed <= 0;
|
1198 |
|
|
// id_ex_branch <= 0;
|
1199 |
|
|
// id_ex_jump <= 0;
|
1200 |
|
|
// id_ex_jr <= 0;
|
1201 |
|
|
// id_ex_linked <= 0;
|
1202 |
|
|
// id_ex_mult <= 0;
|
1203 |
|
|
// id_ex_div <= 0;
|
1204 |
|
|
// id_ex_load <= 0;
|
1205 |
|
|
// id_ex_store <= 0;
|
1206 |
|
|
// id_ex_size <= 0;
|
1207 |
|
|
// id_ex_store_value <= 0;
|
1208 |
|
|
// id_ex_destreg <= 0;
|
1209 |
|
|
// id_ex_desthi <= 0;
|
1210 |
|
|
// id_ex_destlo <= 0;
|
1211 |
|
|
end
|
1212 |
|
|
`FUNCTION_BREAK:
|
1213 |
|
|
begin
|
1214 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BREAK", if_id_addr, if_id_opcode);
|
1215 |
|
|
// id_ex_alu_a <= 0;
|
1216 |
|
|
// id_ex_alu_b <= 0;
|
1217 |
|
|
// id_ex_alu_func <= `ALU_OP_ADD;
|
1218 |
|
|
// id_ex_alu_signed <= 0;
|
1219 |
|
|
// id_ex_branch <= 0;
|
1220 |
|
|
// id_ex_jump <= 0;
|
1221 |
|
|
// id_ex_jr <= 0;
|
1222 |
|
|
// id_ex_linked <= 0;
|
1223 |
|
|
// id_ex_mult <= 0;
|
1224 |
|
|
// id_ex_div <= 0;
|
1225 |
|
|
// id_ex_load <= 0;
|
1226 |
|
|
// id_ex_store <= 0;
|
1227 |
|
|
// id_ex_size <= 0;
|
1228 |
|
|
// id_ex_store_value <= 0;
|
1229 |
|
|
// id_ex_destreg <= 0;
|
1230 |
|
|
// id_ex_desthi <= 0;
|
1231 |
|
|
// id_ex_destlo <= 0;
|
1232 |
|
|
end
|
1233 |
|
|
`FUNCTION_MFHI:
|
1234 |
|
|
begin
|
1235 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MFHI r%d", if_id_addr, if_id_opcode, if_id_rd);
|
1236 |
|
|
id_ex_alu_a <= HI;
|
1237 |
|
|
id_ex_alu_b <= 0;
|
1238 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
1239 |
|
|
id_ex_alu_signed <= 0;
|
1240 |
|
|
id_ex_branch <= 0;
|
1241 |
|
|
id_ex_jump <= 0;
|
1242 |
|
|
id_ex_jr <= 0;
|
1243 |
|
|
id_ex_linked <= 0;
|
1244 |
|
|
id_ex_mult <= 0;
|
1245 |
|
|
id_ex_div <= 0;
|
1246 |
|
|
id_ex_load <= 0;
|
1247 |
|
|
id_ex_store <= 0;
|
1248 |
|
|
id_ex_size <= 0;
|
1249 |
|
|
id_ex_store_value <= 0;
|
1250 |
|
|
id_ex_destreg <= if_id_rd;
|
1251 |
|
|
id_ex_desthi <= 0;
|
1252 |
|
|
id_ex_destlo <= 0;
|
1253 |
|
|
end
|
1254 |
|
|
`FUNCTION_MTHI:
|
1255 |
|
|
begin
|
1256 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MTHI r%d", if_id_addr, if_id_opcode, if_id_rs);
|
1257 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1258 |
|
|
id_ex_alu_b <= 0;
|
1259 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
1260 |
|
|
id_ex_alu_signed <= 0;
|
1261 |
|
|
id_ex_branch <= 0;
|
1262 |
|
|
id_ex_jump <= 0;
|
1263 |
|
|
id_ex_jr <= 0;
|
1264 |
|
|
id_ex_linked <= 0;
|
1265 |
|
|
id_ex_mult <= 0;
|
1266 |
|
|
id_ex_div <= 0;
|
1267 |
|
|
id_ex_load <= 0;
|
1268 |
|
|
id_ex_store <= 0;
|
1269 |
|
|
id_ex_size <= 0;
|
1270 |
|
|
id_ex_store_value <= 0;
|
1271 |
|
|
id_ex_destreg <= 0;
|
1272 |
|
|
id_ex_desthi <= 1;
|
1273 |
|
|
id_ex_destlo <= 0;
|
1274 |
|
|
end
|
1275 |
|
|
`FUNCTION_MFLO:
|
1276 |
|
|
begin
|
1277 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MFLO r%d", if_id_addr, if_id_opcode, if_id_rd);
|
1278 |
|
|
id_ex_alu_a <= LO;
|
1279 |
|
|
id_ex_alu_b <= 0;
|
1280 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
1281 |
|
|
id_ex_alu_signed <= 0;
|
1282 |
|
|
id_ex_branch <= 0;
|
1283 |
|
|
id_ex_jump <= 0;
|
1284 |
|
|
id_ex_jr <= 0;
|
1285 |
|
|
id_ex_linked <= 0;
|
1286 |
|
|
id_ex_mult <= 0;
|
1287 |
|
|
id_ex_div <= 0;
|
1288 |
|
|
id_ex_load <= 0;
|
1289 |
|
|
id_ex_store <= 0;
|
1290 |
|
|
id_ex_size <= 0;
|
1291 |
|
|
id_ex_store_value <= 0;
|
1292 |
|
|
id_ex_destreg <= if_id_rd;
|
1293 |
|
|
id_ex_desthi <= 0;
|
1294 |
|
|
id_ex_destlo <= 0;
|
1295 |
|
|
end
|
1296 |
|
|
`FUNCTION_MTLO:
|
1297 |
|
|
begin
|
1298 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MTLO r%d", if_id_addr, if_id_opcode, if_id_rs);
|
1299 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1300 |
|
|
id_ex_alu_b <= 0;
|
1301 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
1302 |
|
|
id_ex_alu_signed <= 0;
|
1303 |
|
|
id_ex_branch <= 0;
|
1304 |
|
|
id_ex_jump <= 0;
|
1305 |
|
|
id_ex_linked <= 0;
|
1306 |
|
|
id_ex_mult <= 0;
|
1307 |
|
|
id_ex_div <= 0;
|
1308 |
|
|
id_ex_load <= 0;
|
1309 |
|
|
id_ex_store <= 0;
|
1310 |
|
|
id_ex_size <= 0;
|
1311 |
|
|
id_ex_store_value <= 0;
|
1312 |
|
|
id_ex_destreg <= 0;
|
1313 |
|
|
id_ex_desthi <= 0;
|
1314 |
|
|
id_ex_destlo <= 1;
|
1315 |
|
|
end
|
1316 |
|
|
`FUNCTION_MULT:
|
1317 |
|
|
begin
|
1318 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MULT r%d, r%d", if_id_addr, if_id_opcode, if_id_rs, if_id_rt);
|
1319 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1320 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1321 |
|
|
id_ex_alu_func <= `ALU_OP_MULT;
|
1322 |
|
|
id_ex_alu_signed <= 1;
|
1323 |
|
|
id_ex_branch <= 0;
|
1324 |
|
|
id_ex_jump <= 0;
|
1325 |
|
|
id_ex_jr <= 0;
|
1326 |
|
|
id_ex_linked <= 0;
|
1327 |
|
|
id_ex_mult <= 1;
|
1328 |
|
|
id_ex_div <= 0;
|
1329 |
|
|
id_ex_load <= 0;
|
1330 |
|
|
id_ex_store <= 0;
|
1331 |
|
|
id_ex_size <= 0;
|
1332 |
|
|
id_ex_store_value <= 0;
|
1333 |
|
|
id_ex_destreg <= 0;
|
1334 |
|
|
id_ex_desthi <= 1;
|
1335 |
|
|
id_ex_destlo <= 1;
|
1336 |
|
|
mul_req_o <= !mul_req_o; // Toggle the ABP request
|
1337 |
|
|
end
|
1338 |
|
|
`FUNCTION_MULTU:
|
1339 |
|
|
begin
|
1340 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MULTU r%d, r%d", if_id_addr, if_id_opcode, if_id_rs, if_id_rt);
|
1341 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1342 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1343 |
|
|
id_ex_alu_func <= `ALU_OP_MULT;
|
1344 |
|
|
id_ex_alu_signed <= 0;
|
1345 |
|
|
id_ex_branch <= 0;
|
1346 |
|
|
id_ex_jump <= 0;
|
1347 |
|
|
id_ex_jr <= 0;
|
1348 |
|
|
id_ex_linked <= 0;
|
1349 |
|
|
id_ex_mult <= 1;
|
1350 |
|
|
id_ex_div <= 0;
|
1351 |
|
|
id_ex_load <= 0;
|
1352 |
|
|
id_ex_store <= 0;
|
1353 |
|
|
id_ex_size <= 0;
|
1354 |
|
|
id_ex_store_value <= 0;
|
1355 |
|
|
id_ex_destreg <= 0;
|
1356 |
|
|
id_ex_desthi <= 1;
|
1357 |
|
|
id_ex_destlo <= 1;
|
1358 |
|
|
mul_req_o <= !mul_req_o; // Toggle the ABP request
|
1359 |
|
|
end
|
1360 |
|
|
`FUNCTION_DIV:
|
1361 |
|
|
begin
|
1362 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as DIV r%d, r%d", if_id_addr, if_id_opcode, if_id_rs, if_id_rt);
|
1363 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1364 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1365 |
|
|
id_ex_alu_func <= `ALU_OP_DIV;
|
1366 |
|
|
id_ex_alu_signed <= 1;
|
1367 |
|
|
id_ex_branch <= 0;
|
1368 |
|
|
id_ex_jump <= 0;
|
1369 |
|
|
id_ex_jr <= 0;
|
1370 |
|
|
id_ex_linked <= 0;
|
1371 |
|
|
id_ex_mult <= 0;
|
1372 |
|
|
id_ex_div <= 1;
|
1373 |
|
|
id_ex_load <= 0;
|
1374 |
|
|
id_ex_store <= 0;
|
1375 |
|
|
id_ex_size <= 0;
|
1376 |
|
|
id_ex_store_value <= 0;
|
1377 |
|
|
id_ex_destreg <= 0;
|
1378 |
|
|
id_ex_desthi <= 1;
|
1379 |
|
|
id_ex_destlo <= 1;
|
1380 |
|
|
div_req_o <= !div_req_o; // Toggle the ABP request
|
1381 |
|
|
end
|
1382 |
|
|
`FUNCTION_DIVU:
|
1383 |
|
|
begin
|
1384 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as DIVU r%d, r%d", if_id_addr, if_id_opcode, if_id_rs, if_id_rt);
|
1385 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1386 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1387 |
|
|
id_ex_alu_func <= `ALU_OP_DIV;
|
1388 |
|
|
id_ex_alu_signed <= 0;
|
1389 |
|
|
id_ex_branch <= 0;
|
1390 |
|
|
id_ex_jump <= 0;
|
1391 |
|
|
id_ex_jr <= 0;
|
1392 |
|
|
id_ex_linked <= 0;
|
1393 |
|
|
id_ex_mult <= 0;
|
1394 |
|
|
id_ex_div <= 1;
|
1395 |
|
|
id_ex_load <= 0;
|
1396 |
|
|
id_ex_store <= 0;
|
1397 |
|
|
id_ex_size <= 0;
|
1398 |
|
|
id_ex_store_value <= 0;
|
1399 |
|
|
id_ex_destreg <= 0;
|
1400 |
|
|
id_ex_desthi <= 1;
|
1401 |
|
|
id_ex_destlo <= 1;
|
1402 |
|
|
div_req_o <= !div_req_o; // Toggle the ABP request
|
1403 |
|
|
end
|
1404 |
|
|
`FUNCTION_ADD:
|
1405 |
|
|
begin
|
1406 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ADD r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
|
1407 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1408 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1409 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
1410 |
|
|
id_ex_alu_signed <= 1;
|
1411 |
|
|
id_ex_branch <= 0;
|
1412 |
|
|
id_ex_jump <= 0;
|
1413 |
|
|
id_ex_jr <= 0;
|
1414 |
|
|
id_ex_linked <= 0;
|
1415 |
|
|
id_ex_mult <= 0;
|
1416 |
|
|
id_ex_div <= 0;
|
1417 |
|
|
id_ex_load <= 0;
|
1418 |
|
|
id_ex_store <= 0;
|
1419 |
|
|
id_ex_size <= 0;
|
1420 |
|
|
id_ex_store_value <= 0;
|
1421 |
|
|
id_ex_destreg <= if_id_rd;
|
1422 |
|
|
id_ex_desthi <= 0;
|
1423 |
|
|
id_ex_destlo <= 0;
|
1424 |
|
|
end
|
1425 |
|
|
`FUNCTION_ADDU:
|
1426 |
|
|
begin
|
1427 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ADDU r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
|
1428 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1429 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1430 |
|
|
id_ex_alu_func <= `ALU_OP_ADD;
|
1431 |
|
|
id_ex_alu_signed <= 0;
|
1432 |
|
|
id_ex_branch <= 0;
|
1433 |
|
|
id_ex_jump <= 0;
|
1434 |
|
|
id_ex_jr <= 0;
|
1435 |
|
|
id_ex_linked <= 0;
|
1436 |
|
|
id_ex_mult <= 0;
|
1437 |
|
|
id_ex_div <= 0;
|
1438 |
|
|
id_ex_load <= 0;
|
1439 |
|
|
id_ex_store <= 0;
|
1440 |
|
|
id_ex_size <= 0;
|
1441 |
|
|
id_ex_store_value <= 0;
|
1442 |
|
|
id_ex_destreg <= if_id_rd;
|
1443 |
|
|
id_ex_desthi <= 0;
|
1444 |
|
|
id_ex_destlo <= 0;
|
1445 |
|
|
end
|
1446 |
|
|
`FUNCTION_SUB:
|
1447 |
|
|
begin
|
1448 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SUB r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
|
1449 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1450 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1451 |
|
|
id_ex_alu_func <= `ALU_OP_SUB;
|
1452 |
|
|
id_ex_alu_signed <= 1;
|
1453 |
|
|
id_ex_branch <= 0;
|
1454 |
|
|
id_ex_jump <= 0;
|
1455 |
|
|
id_ex_jr <= 0;
|
1456 |
|
|
id_ex_linked <= 0;
|
1457 |
|
|
id_ex_mult <= 0;
|
1458 |
|
|
id_ex_div <= 0;
|
1459 |
|
|
id_ex_load <= 0;
|
1460 |
|
|
id_ex_store <= 0;
|
1461 |
|
|
id_ex_size <= 0;
|
1462 |
|
|
id_ex_store_value <= 0;
|
1463 |
|
|
id_ex_destreg <= if_id_rd;
|
1464 |
|
|
id_ex_desthi <= 0;
|
1465 |
|
|
id_ex_destlo <= 0;
|
1466 |
|
|
end
|
1467 |
|
|
`FUNCTION_SUBU:
|
1468 |
|
|
begin
|
1469 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SUBU r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
|
1470 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1471 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1472 |
|
|
id_ex_alu_func <= `ALU_OP_SUB;
|
1473 |
|
|
id_ex_alu_signed <= 0;
|
1474 |
|
|
id_ex_branch <= 0;
|
1475 |
|
|
id_ex_jump <= 0;
|
1476 |
|
|
id_ex_jr <= 0;
|
1477 |
|
|
id_ex_linked <= 0;
|
1478 |
|
|
id_ex_mult <= 0;
|
1479 |
|
|
id_ex_div <= 0;
|
1480 |
|
|
id_ex_load <= 0;
|
1481 |
|
|
id_ex_store <= 0;
|
1482 |
|
|
id_ex_size <= 0;
|
1483 |
|
|
id_ex_store_value <= 0;
|
1484 |
|
|
id_ex_destreg <= if_id_rd;
|
1485 |
|
|
id_ex_desthi <= 0;
|
1486 |
|
|
id_ex_destlo <= 0;
|
1487 |
|
|
end
|
1488 |
|
|
`FUNCTION_AND:
|
1489 |
|
|
begin
|
1490 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as AND r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
|
1491 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1492 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1493 |
|
|
id_ex_alu_func <= `ALU_OP_AND;
|
1494 |
|
|
id_ex_alu_signed <= 0;
|
1495 |
|
|
id_ex_branch <= 0;
|
1496 |
|
|
id_ex_jump <= 0;
|
1497 |
|
|
id_ex_jr <= 0;
|
1498 |
|
|
id_ex_linked <= 0;
|
1499 |
|
|
id_ex_mult <= 0;
|
1500 |
|
|
id_ex_div <= 0;
|
1501 |
|
|
id_ex_load <= 0;
|
1502 |
|
|
id_ex_store <= 0;
|
1503 |
|
|
id_ex_size <= 0;
|
1504 |
|
|
id_ex_store_value <= 0;
|
1505 |
|
|
id_ex_destreg <= if_id_rd;
|
1506 |
|
|
id_ex_desthi <= 0;
|
1507 |
|
|
id_ex_destlo <= 0;
|
1508 |
|
|
end
|
1509 |
|
|
`FUNCTION_OR:
|
1510 |
|
|
begin
|
1511 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as OR r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
|
1512 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1513 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1514 |
|
|
id_ex_alu_func <= `ALU_OP_OR;
|
1515 |
|
|
id_ex_alu_signed <= 0;
|
1516 |
|
|
id_ex_branch <= 0;
|
1517 |
|
|
id_ex_jump <= 0;
|
1518 |
|
|
id_ex_jr <= 0;
|
1519 |
|
|
id_ex_linked <= 0;
|
1520 |
|
|
id_ex_mult <= 0;
|
1521 |
|
|
id_ex_div <= 0;
|
1522 |
|
|
id_ex_load <= 0;
|
1523 |
|
|
id_ex_store <= 0;
|
1524 |
|
|
id_ex_size <= 0;
|
1525 |
|
|
id_ex_store_value <= 0;
|
1526 |
|
|
id_ex_destreg <= if_id_rd;
|
1527 |
|
|
id_ex_desthi <= 0;
|
1528 |
|
|
id_ex_destlo <= 0;
|
1529 |
|
|
end
|
1530 |
|
|
`FUNCTION_XOR:
|
1531 |
|
|
begin
|
1532 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as XOR r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
|
1533 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1534 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1535 |
|
|
id_ex_alu_func <= `ALU_OP_XOR;
|
1536 |
|
|
id_ex_alu_signed <= 0;
|
1537 |
|
|
id_ex_branch <= 0;
|
1538 |
|
|
id_ex_jump <= 0;
|
1539 |
|
|
id_ex_jr <= 0;
|
1540 |
|
|
id_ex_linked <= 0;
|
1541 |
|
|
id_ex_mult <= 0;
|
1542 |
|
|
id_ex_div <= 0;
|
1543 |
|
|
id_ex_load <= 0;
|
1544 |
|
|
id_ex_store <= 0;
|
1545 |
|
|
id_ex_size <= 0;
|
1546 |
|
|
id_ex_store_value <= 0;
|
1547 |
|
|
id_ex_destreg <= if_id_rd;
|
1548 |
|
|
id_ex_desthi <= 0;
|
1549 |
|
|
id_ex_destlo <= 0;
|
1550 |
|
|
end
|
1551 |
|
|
`FUNCTION_NOR:
|
1552 |
|
|
begin
|
1553 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as NOR r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
|
1554 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1555 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1556 |
|
|
id_ex_alu_func <= `ALU_OP_NOR;
|
1557 |
|
|
id_ex_alu_signed <= 0;
|
1558 |
|
|
id_ex_branch <= 0;
|
1559 |
|
|
id_ex_jump <= 0;
|
1560 |
|
|
id_ex_jr <= 0;
|
1561 |
|
|
id_ex_linked <= 0;
|
1562 |
|
|
id_ex_mult <= 0;
|
1563 |
|
|
id_ex_div <= 0;
|
1564 |
|
|
id_ex_load <= 0;
|
1565 |
|
|
id_ex_store <= 0;
|
1566 |
|
|
id_ex_size <= 0;
|
1567 |
|
|
id_ex_store_value <= 0;
|
1568 |
|
|
id_ex_destreg <= if_id_rd;
|
1569 |
|
|
id_ex_desthi <= 0;
|
1570 |
|
|
id_ex_destlo <= 0;
|
1571 |
|
|
end
|
1572 |
|
|
`FUNCTION_SLT:
|
1573 |
|
|
begin
|
1574 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLT r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
|
1575 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1576 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1577 |
|
|
id_ex_alu_func <= `ALU_OP_SLT;
|
1578 |
|
|
id_ex_alu_signed <= 1;
|
1579 |
|
|
id_ex_branch <= 0;
|
1580 |
|
|
id_ex_jump <= 0;
|
1581 |
|
|
id_ex_jr <= 0;
|
1582 |
|
|
id_ex_linked <= 0;
|
1583 |
|
|
id_ex_mult <= 0;
|
1584 |
|
|
id_ex_div <= 0;
|
1585 |
|
|
id_ex_load <= 0;
|
1586 |
|
|
id_ex_store <= 0;
|
1587 |
|
|
id_ex_size <= 0;
|
1588 |
|
|
id_ex_store_value <= 0;
|
1589 |
|
|
id_ex_destreg <= if_id_rd;
|
1590 |
|
|
id_ex_desthi <= 0;
|
1591 |
|
|
id_ex_destlo <= 0;
|
1592 |
|
|
end
|
1593 |
|
|
`FUNCTION_SLTU:
|
1594 |
|
|
begin
|
1595 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLTU r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
|
1596 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1597 |
|
|
id_ex_alu_b <= GPR[if_id_rt];
|
1598 |
|
|
id_ex_alu_func <= `ALU_OP_SLT;
|
1599 |
|
|
id_ex_alu_signed <= 0;
|
1600 |
|
|
id_ex_branch <= 0;
|
1601 |
|
|
id_ex_jump <= 0;
|
1602 |
|
|
id_ex_jr <= 0;
|
1603 |
|
|
id_ex_linked <= 0;
|
1604 |
|
|
id_ex_mult <= 0;
|
1605 |
|
|
id_ex_div <= 0;
|
1606 |
|
|
id_ex_load <= 0;
|
1607 |
|
|
id_ex_store <= 0;
|
1608 |
|
|
id_ex_size <= 0;
|
1609 |
|
|
id_ex_store_value <= 0;
|
1610 |
|
|
id_ex_destreg <= if_id_rd;
|
1611 |
|
|
id_ex_desthi <= 0;
|
1612 |
|
|
id_ex_destlo <= 0;
|
1613 |
|
|
end
|
1614 |
|
|
endcase
|
1615 |
|
|
`OPCODE_BCOND:
|
1616 |
|
|
case(if_id_rt)
|
1617 |
|
|
`BCOND_BLTZ:
|
1618 |
|
|
begin
|
1619 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BLTZ r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
|
1620 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1621 |
|
|
id_ex_alu_b <= 0;
|
1622 |
|
|
id_ex_alu_func <= `ALU_OP_SLT;
|
1623 |
|
|
id_ex_alu_signed <= 1;
|
1624 |
|
|
id_ex_branch <= 1;
|
1625 |
|
|
id_ex_jump <= 0;
|
1626 |
|
|
id_ex_jr <= 0;
|
1627 |
|
|
id_ex_linked <= 0;
|
1628 |
|
|
id_ex_mult <= 0;
|
1629 |
|
|
id_ex_div <= 0;
|
1630 |
|
|
id_ex_load <= 0;
|
1631 |
|
|
id_ex_store <= 0;
|
1632 |
|
|
id_ex_size <= 0;
|
1633 |
|
|
id_ex_store_value <= 0;
|
1634 |
|
|
id_ex_destreg <= if_id_rd;
|
1635 |
|
|
id_ex_desthi <= 0;
|
1636 |
|
|
id_ex_destlo <= 0;
|
1637 |
|
|
end
|
1638 |
|
|
`BCOND_BGEZ:
|
1639 |
|
|
begin
|
1640 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BGEZ r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
|
1641 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1642 |
|
|
id_ex_alu_b <= 0;
|
1643 |
|
|
id_ex_alu_func <= `ALU_OP_SGE;
|
1644 |
|
|
id_ex_alu_signed <= 1;
|
1645 |
|
|
id_ex_branch <= 1;
|
1646 |
|
|
id_ex_jump <= 0;
|
1647 |
|
|
id_ex_jr <= 0;
|
1648 |
|
|
id_ex_linked <= 0;
|
1649 |
|
|
id_ex_mult <= 0;
|
1650 |
|
|
id_ex_div <= 0;
|
1651 |
|
|
id_ex_load <= 0;
|
1652 |
|
|
id_ex_store <= 0;
|
1653 |
|
|
id_ex_size <= 0;
|
1654 |
|
|
id_ex_store_value <= 0;
|
1655 |
|
|
id_ex_destreg <= if_id_rd;
|
1656 |
|
|
id_ex_desthi <= 0;
|
1657 |
|
|
id_ex_destlo <= 0;
|
1658 |
|
|
end
|
1659 |
|
|
`BCOND_BLTZAL:
|
1660 |
|
|
begin
|
1661 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BLTZAL r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
|
1662 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1663 |
|
|
id_ex_alu_b <= 0;
|
1664 |
|
|
id_ex_alu_func <= `ALU_OP_SLT;
|
1665 |
|
|
id_ex_alu_signed <= 1;
|
1666 |
|
|
id_ex_branch <= 1;
|
1667 |
|
|
id_ex_jump <= 0;
|
1668 |
|
|
id_ex_jr <= 0;
|
1669 |
|
|
id_ex_linked <= 1;
|
1670 |
|
|
id_ex_mult <= 0;
|
1671 |
|
|
id_ex_div <= 0;
|
1672 |
|
|
id_ex_load <= 0;
|
1673 |
|
|
id_ex_store <= 0;
|
1674 |
|
|
id_ex_size <= 0;
|
1675 |
|
|
id_ex_store_value <= 0;
|
1676 |
|
|
id_ex_destreg <= 31;
|
1677 |
|
|
id_ex_desthi <= 0;
|
1678 |
|
|
id_ex_destlo <= 0;
|
1679 |
|
|
end
|
1680 |
|
|
`BCOND_BGEZAL:
|
1681 |
|
|
begin
|
1682 |
|
|
$display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BGEZAL r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
|
1683 |
|
|
id_ex_alu_a <= GPR[if_id_rs];
|
1684 |
|
|
id_ex_alu_b <= 0;
|
1685 |
|
|
id_ex_alu_func <=`ALU_OP_SGE;
|
1686 |
|
|
id_ex_alu_signed <= 1;
|
1687 |
|
|
id_ex_branch <= 1;
|
1688 |
|
|
id_ex_jump <= 0;
|
1689 |
|
|
id_ex_jr <= 0;
|
1690 |
|
|
id_ex_linked <= 1;
|
1691 |
|
|
id_ex_mult <= 0;
|
1692 |
|
|
id_ex_div <= 0;
|
1693 |
|
|
id_ex_load <= 0;
|
1694 |
|
|
id_ex_store <= 0;
|
1695 |
|
|
id_ex_size <= 0;
|
1696 |
|
|
id_ex_store_value <= 0;
|
1697 |
|
|
id_ex_destreg <= 31;
|
1698 |
|
|
id_ex_desthi <= 0;
|
1699 |
|
|
id_ex_destlo <= 0;
|
1700 |
|
|
end
|
1701 |
|
|
endcase
|
1702 |
|
|
|
1703 |
|
|
endcase
|
1704 |
|
|
|
1705 |
|
|
end
|
1706 |
|
|
|
1707 |
|
|
/*
|
1708 |
|
|
* Pipeline Stage 3: Execute (EX)
|
1709 |
|
|
*
|
1710 |
|
|
* READ/WRITE:
|
1711 |
|
|
* - read the ID/EX latch
|
1712 |
|
|
* - write the EX/MEM latch
|
1713 |
|
|
*
|
1714 |
|
|
* DESCRIPTION:
|
1715 |
|
|
* This stage takes the result from the ALU and put it in the proper latch.
|
1716 |
|
|
* Please note that assignments to ALU inputs are done outside since they're wires.
|
1717 |
|
|
*/
|
1718 |
|
|
|
1719 |
|
|
if(ex_stall) begin
|
1720 |
|
|
|
1721 |
|
|
if(mem_stall) begin
|
1722 |
|
|
$display("INFO: CPU(%m)-EX: Execution stalled and latch kept for following stalled pipeline stage");
|
1723 |
|
|
end else begin
|
1724 |
|
|
$display("INFO: CPU(%m)-EX: Execution stalled and bubble inserted for following running pipeline stage");
|
1725 |
|
|
ex_mem_opcode <= `BUBBLE;
|
1726 |
|
|
ex_mem_addr <= id_ex_addr;
|
1727 |
|
|
ex_mem_addrnext <= 0;
|
1728 |
|
|
ex_mem_destreg <= 0;
|
1729 |
|
|
ex_mem_desthi <= 0;
|
1730 |
|
|
ex_mem_destlo <= 0;
|
1731 |
|
|
end
|
1732 |
|
|
|
1733 |
|
|
end else begin
|
1734 |
|
|
|
1735 |
|
|
// If not stalled propagate values to next latches
|
1736 |
|
|
ex_mem_opcode <= id_ex_opcode;
|
1737 |
|
|
ex_mem_addr <= id_ex_addr;
|
1738 |
|
|
ex_mem_addrnext <= id_ex_addrnext;
|
1739 |
|
|
ex_mem_addrjump <= id_ex_addrjump;
|
1740 |
|
|
ex_mem_addrbranch <= id_ex_addrbranch;
|
1741 |
|
|
ex_mem_branch <= id_ex_branch;
|
1742 |
|
|
ex_mem_jump <= id_ex_jump;
|
1743 |
|
|
ex_mem_jr <= id_ex_jr;
|
1744 |
|
|
ex_mem_linked <= id_ex_linked;
|
1745 |
|
|
ex_mem_mult <= id_ex_mult;
|
1746 |
|
|
ex_mem_div <= id_ex_div;
|
1747 |
|
|
ex_mem_load <= id_ex_load;
|
1748 |
|
|
ex_mem_store <= id_ex_store;
|
1749 |
|
|
ex_mem_destreg <= id_ex_destreg;
|
1750 |
|
|
ex_mem_desthi <= id_ex_desthi;
|
1751 |
|
|
ex_mem_destlo <= id_ex_destlo;
|
1752 |
|
|
|
1753 |
|
|
// Choose the output from ALU, Multiplier or Divider
|
1754 |
|
|
if(id_ex_mult) ex_mem_aluout <= mul_product_i;
|
1755 |
|
|
else if(id_ex_div) ex_mem_aluout <= { div_remainder_i, div_quotient_i };
|
1756 |
|
|
else ex_mem_aluout <= alu_result_i;
|
1757 |
|
|
|
1758 |
|
|
if(id_ex_store) begin
|
1759 |
|
|
|
1760 |
|
|
$display("INFO: CPU(%m)-EX: Execution of Store instruction @ADDR=%X w/OPCODE=%X started to STORE_ADDR=%X w/STORE_DATA=%X", id_ex_addr, id_ex_opcode, alu_result_i, id_ex_store_value);
|
1761 |
|
|
case(id_ex_size)
|
1762 |
|
|
`SIZE_WORD: begin
|
1763 |
|
|
ex_mem_store_value <= id_ex_store_value;
|
1764 |
|
|
ex_mem_store_sel <= 4'b1111;
|
1765 |
|
|
end
|
1766 |
|
|
`SIZE_HALF: begin
|
1767 |
|
|
if(alu_result_i[1]==0) begin
|
1768 |
|
|
ex_mem_store_value <= {{16'b0},id_ex_store_value[15:0]};
|
1769 |
|
|
ex_mem_store_sel <= 4'b0011;
|
1770 |
|
|
end else begin
|
1771 |
|
|
ex_mem_store_value <= {id_ex_store_value[15:0],{16'b0}};
|
1772 |
|
|
ex_mem_store_sel <= 4'b1100;
|
1773 |
|
|
end
|
1774 |
|
|
end
|
1775 |
|
|
`SIZE_BYTE: begin
|
1776 |
|
|
case(alu_result_i[1:0])
|
1777 |
|
|
2'b00: begin
|
1778 |
|
|
ex_mem_store_value <= {{24'b0},id_ex_store_value[7:0]};
|
1779 |
|
|
ex_mem_store_sel <= 4'b0001;
|
1780 |
|
|
end
|
1781 |
|
|
2'b01: begin
|
1782 |
|
|
ex_mem_store_value <= {{16'b0},id_ex_store_value[7:0],{8'b0}};
|
1783 |
|
|
ex_mem_store_sel <= 4'b0010;
|
1784 |
|
|
end
|
1785 |
|
|
2'b10: begin
|
1786 |
|
|
ex_mem_store_value <= {{8'b0},id_ex_store_value[7:0],{16'b0}};
|
1787 |
|
|
ex_mem_store_sel <= 4'b0100;
|
1788 |
|
|
end
|
1789 |
|
|
2'b11: begin
|
1790 |
|
|
ex_mem_store_value <= {id_ex_store_value[7:0],{24'b0}};
|
1791 |
|
|
ex_mem_store_sel <= 4'b1000;
|
1792 |
|
|
end
|
1793 |
|
|
endcase
|
1794 |
|
|
end
|
1795 |
|
|
endcase
|
1796 |
|
|
|
1797 |
|
|
end else begin
|
1798 |
|
|
|
1799 |
|
|
// Not a store
|
1800 |
|
|
$display("INFO: CPU(%m)-EX: Execution of instruction @ADDR=%X w/OPCODE=%X gave ALU result %X", id_ex_addr, id_ex_opcode, alu_result_i);
|
1801 |
|
|
|
1802 |
|
|
end
|
1803 |
|
|
|
1804 |
|
|
end
|
1805 |
|
|
|
1806 |
|
|
/*
|
1807 |
|
|
* Pipeline Stage 4: Memory access (MEM)
|
1808 |
|
|
*
|
1809 |
|
|
* READ/WRITE:
|
1810 |
|
|
* - read the EX/MEM latch
|
1811 |
|
|
* - read or write memory
|
1812 |
|
|
* - write the MEM/WB latch
|
1813 |
|
|
*
|
1814 |
|
|
* DESCRIPTION:
|
1815 |
|
|
* This stage perform accesses to memory to read/write the data during
|
1816 |
|
|
* the load/store operations.
|
1817 |
|
|
*/
|
1818 |
|
|
|
1819 |
|
|
if(mem_stall) begin
|
1820 |
|
|
|
1821 |
|
|
$display("INFO: CPU(%m)-MEM: Memory stalled");
|
1822 |
|
|
|
1823 |
|
|
end else begin
|
1824 |
|
|
|
1825 |
|
|
mem_wb_opcode <= ex_mem_opcode;
|
1826 |
|
|
mem_wb_addr <= ex_mem_addr;
|
1827 |
|
|
mem_wb_addrnext <= ex_mem_addrnext;
|
1828 |
|
|
mem_wb_destreg <= ex_mem_destreg;
|
1829 |
|
|
mem_wb_desthi <= ex_mem_desthi;
|
1830 |
|
|
mem_wb_destlo <= ex_mem_destlo;
|
1831 |
|
|
|
1832 |
|
|
if(ex_mem_load) begin
|
1833 |
|
|
|
1834 |
|
|
$display("INFO: CPU(%m)-MEM: Loading value %X", dmem_data_i);
|
1835 |
|
|
mem_wb_value[63:32] <= 32'b0;
|
1836 |
|
|
mem_wb_value[31:0] <= dmem_data_i;
|
1837 |
|
|
|
1838 |
|
|
end else if (ex_mem_desthi && ex_mem_destlo) begin
|
1839 |
|
|
|
1840 |
|
|
$display("INFO: CPU(%m)-MEM: Propagating value %X", ex_mem_aluout);
|
1841 |
|
|
mem_wb_value[31:0] <= ex_mem_aluout[31:0];
|
1842 |
|
|
mem_wb_value[63:32] <= ex_mem_aluout[63:32];
|
1843 |
|
|
|
1844 |
|
|
end else if (ex_mem_desthi) begin
|
1845 |
|
|
|
1846 |
|
|
$display("INFO: CPU(%m)-MEM: Propagating value %X", ex_mem_aluout);
|
1847 |
|
|
mem_wb_value[63:32] <= ex_mem_aluout[31:0];
|
1848 |
|
|
mem_wb_value[31:0] <= 32'b0;
|
1849 |
|
|
|
1850 |
|
|
end else begin
|
1851 |
|
|
|
1852 |
|
|
$display("INFO: CPU(%m)-MEM: Propagating value %X", ex_mem_aluout);
|
1853 |
|
|
mem_wb_value[31:0] <= ex_mem_aluout[31:0];
|
1854 |
|
|
mem_wb_value[63:32] <= 32'b0;
|
1855 |
|
|
|
1856 |
|
|
end
|
1857 |
|
|
|
1858 |
|
|
end
|
1859 |
|
|
|
1860 |
|
|
/*
|
1861 |
|
|
* Pipeline Stage 5: Write Back (WB)
|
1862 |
|
|
*
|
1863 |
|
|
* READ/WRITE:
|
1864 |
|
|
* - read the MEM/WB latch
|
1865 |
|
|
* - write the register file
|
1866 |
|
|
*
|
1867 |
|
|
* DESCRIPTION:
|
1868 |
|
|
* This stage writes back the result into the proper register (GPR, HI, LO).
|
1869 |
|
|
*/
|
1870 |
|
|
|
1871 |
|
|
if(wb_stall) begin
|
1872 |
|
|
|
1873 |
|
|
$display("INFO: CPU(%m)-WB: Write-Back stalled");
|
1874 |
|
|
|
1875 |
|
|
end else begin
|
1876 |
|
|
|
1877 |
|
|
// GPRs
|
1878 |
|
|
if(mem_wb_destreg!=0) begin
|
1879 |
|
|
$display("INFO: CPU(%m)-WB: Writing Back GPR[%d]=%X", mem_wb_destreg, mem_wb_value[31:0]);
|
1880 |
|
|
GPR[mem_wb_destreg] <= mem_wb_value[31:0];
|
1881 |
|
|
end
|
1882 |
|
|
|
1883 |
|
|
// HI
|
1884 |
|
|
if(mem_wb_desthi) begin
|
1885 |
|
|
$display("INFO: CPU(%m)-WB: Writing Back HI=%X", mem_wb_value[63:32]);
|
1886 |
|
|
HI <= mem_wb_value[63:32];
|
1887 |
|
|
end
|
1888 |
|
|
|
1889 |
|
|
// LO
|
1890 |
|
|
if(mem_wb_destlo) begin
|
1891 |
|
|
$display("INFO: CPU(%m)-WB: Writing Back LO=%X", mem_wb_value[31:0]);
|
1892 |
|
|
LO <= mem_wb_value[31:0];
|
1893 |
|
|
end
|
1894 |
|
|
|
1895 |
|
|
// Idle
|
1896 |
|
|
if(mem_wb_destreg==0 & mem_wb_desthi==0 & mem_wb_destlo==0)
|
1897 |
|
|
$display("INFO: CPU(%m)-WB: Write-Back has nothing to do");
|
1898 |
|
|
|
1899 |
|
|
end
|
1900 |
|
|
|
1901 |
|
|
// Display register file at each raising edge
|
1902 |
|
|
$display("INFO: CPU(%m)-Regs: R00=%X R01=%X R02=%X R03=%X R04=%X R05=%X R06=%X R07=%X",
|
1903 |
|
|
GPR[0], GPR[1], GPR[2], GPR[3], GPR[4], GPR[5], GPR[6], GPR[7]);
|
1904 |
|
|
$display("INFO: CPU(%m)-Regs: R08=%X R09=%X R10=%X R11=%X R12=%X R13=%X R14=%X R15=%X",
|
1905 |
|
|
GPR[8], GPR[9], GPR[10], GPR[11], GPR[12], GPR[13], GPR[14], GPR[15]);
|
1906 |
|
|
$display("INFO: CPU(%m)-Regs: R16=%X R17=%X R18=%X R19=%X R20=%X R21=%X R22=%X R23=%X",
|
1907 |
|
|
GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[23]);
|
1908 |
|
|
$display("INFO: CPU(%m)-Regs: R24=%X R25=%X R26=%X R27=%X R28=%X R29=%X R30=%X R31=%X",
|
1909 |
|
|
GPR[24], GPR[25], GPR[26], GPR[27], GPR[28], GPR[29], GPR[30], GPR[31]);
|
1910 |
|
|
$display("INFO: CPU(%m)-Regs: PC=%X HI=%X LO=%X",
|
1911 |
|
|
PC, HI, LO);
|
1912 |
|
|
|
1913 |
|
|
end
|
1914 |
|
|
end
|
1915 |
|
|
|
1916 |
|
|
endmodule
|
1917 |
|
|
|