Subversion Repositories m1_core

/*

 * Simply RISC M1 Central Processing Unit

 */

`include "m1_defs.vh"

module m1_cpu (

    // System

    input sys_clock_i,                            // System Clock

    input sys_reset_i,                            // System Reset

    input sys_irq_i,                              // Interrupt Request

    // ALU

    output[31:0] alu_a_o,                         // ALU Operand A

    output[31:0] alu_b_o,                         // ALU Operand B

    output[4:0] alu_func_o,                       // ALU Function

    output alu_signed_o,                          // ALU operation is Signed

    input[32:0] alu_result_i,                     // ALU Result with Carry

    // Multiplier

    output reg mul_req_o,                         // Multiplier Request

    output[31:0] mul_a_o,                         // Multiplier Operand A

    output[31:0] mul_b_o,                         // Multiplier Operand B

    output mul_signed_o,                          // Multiplication is Signed

    input mul_ack_i,                              // Multiplier Ack

    input[63:0] mul_product_i,                    // Multiplier Product

    // Divider

    output reg div_req_o,                         // Divider Request

    output[31:0] div_a_o,                         // Divider Operand A

    output[31:0] div_b_o,                         // Divider Operand B

    output div_signed_o,                          // Division is Signed

    input div_ack_i,                              // Divider Ack

    input[31:0] div_quotient_i,                   // Divider Quotient

    input[31:0] div_remainder_i,                  // Divider Remainder

    // Instruction Memory

    output imem_read_o,                           // I$ Read

    output[31:0] imem_addr_o,                     // I$ Address

    input imem_done_i,                            // I$ Done

    input[31:0] imem_data_i,                      // I$ Data

    // Data Memory

    output dmem_read_o,                           // D$ Read

    output dmem_write_o,                          // D$ Write

    output[3:0] dmem_sel_o,                       // D$ Byte selector

    output[31:0] dmem_addr_o,                     // D$ Address

    output[31:0] dmem_data_o,                     // D$ Write Data

    input dmem_done_i,                            // D$ Done

    input[31:0] dmem_data_i                       // D$ Read Data

  );

  /*

   * Registers

   */

  // Register file

  reg[31:0] GPR[31:0];                            // General Purpose Registers

  reg[31:0] PC;                                   // Program Counter

  reg[31:0] HI, LO;                               // HI and LO registers (for multiplication/division)

  reg[31:0] SysCon[0:31];                         // System Control registers

  /*

   * Pipeline latches

   */

  // Latch 1: IF/ID

  reg[31:0] if_id_opcode;                                            // Instruction Register

  reg[31:0] if_id_addr, if_id_addrnext;                              // Addresses of the fetched opcode and of the next one

  // Latch 2: ID/EX

  reg[31:0] id_ex_opcode;

  reg[31:0] id_ex_addr, id_ex_addrnext;

  reg[31:0] id_ex_addrbranch, id_ex_addrjump, id_ex_addrjr;          // Evaluated jump addresses

  reg[31:0] id_ex_alu_a, id_ex_alu_b;                                // ALU operands

  reg[4:0] id_ex_alu_func;                                           // ALU operation code

  reg id_ex_alu_signed;                                              // ALU operation is signed

  reg id_ex_branch, id_ex_jump, id_ex_jr, id_ex_linked;              // Instruction is a jump

  reg id_ex_mult, id_ex_div;                                         // Instruction is a multiplication/division

  reg id_ex_load, id_ex_store;                                       // Instruction is a load/store

  reg[2:0] id_ex_size;                                               // Load/store size (see defs.h)

  reg[31:0] id_ex_store_value;                                       // Store value

  reg[4:0] id_ex_destreg;                                            // Destination register (GPR number)

  reg id_ex_desthi, id_ex_destlo;                                    // Destination register (HI/LO)

  reg[4:0] id_ex_destsyscon;                                         // Destination register (System Control)

  // Latch 3: EX/MEM

  reg[31:0] ex_mem_opcode;

  reg[31:0] ex_mem_addr, ex_mem_addrnext;

  reg[31:0] ex_mem_addrbranch, ex_mem_addrjump, ex_mem_addrjr;

  reg[63:0] ex_mem_aluout;                                           // ALU result

  reg ex_mem_carry;                                                  // ALU carry

  reg ex_mem_branch, ex_mem_jump, ex_mem_jr, ex_mem_linked;

  reg ex_mem_mult, ex_mem_div;

  reg ex_mem_load, ex_mem_store;

  reg[2:0] ex_mem_size;

  reg[31:0] ex_mem_store_value;

  reg[3:0] ex_mem_store_sel;                                         // Byte Selector on Stores

  reg[4:0] ex_mem_destreg;

  reg ex_mem_desthi, ex_mem_destlo;

  reg[4:0] ex_mem_destsyscon;

  // Latch 4: MEM/WB

  reg[31:0] mem_wb_opcode;

  reg[31:0] mem_wb_addr, mem_wb_addrnext;

  reg[63:0] mem_wb_value;                                            // Write-back value

  reg[4:0] mem_wb_destreg;

  reg mem_wb_desthi, mem_wb_destlo;

  reg [4:0] mem_wb_destsyscon;

  /*

   * Combinational logic

   */

  // ALU

  assign alu_a_o = id_ex_alu_a;

  assign alu_b_o = id_ex_alu_b;

  assign alu_func_o = id_ex_alu_func;

  assign alu_signed_o = id_ex_alu_signed;

  // Multiplier

  assign mul_a_o = id_ex_alu_a;

  assign mul_b_o = id_ex_alu_b;

  assign mul_signed_o = id_ex_alu_signed;

  wire mul_ready = (mul_req_o==mul_ack_i);  // Convert ABP ack to true/false format

  wire mul_busy = !mul_ready;

  // Divider

  assign div_a_o = id_ex_alu_a;

  assign div_b_o = id_ex_alu_b;

  assign div_signed_o = id_ex_alu_signed;

  wire div_ready = (div_req_o==div_ack_i);  // Convert ABP ack to true/false format

  wire div_busy = !div_ready;

  // Incremented Program Counter

  wire[31:0] PCnext = PC + 4;

  // Instruction Memory

  assign imem_read_o = 1;

  assign imem_addr_o = PC;

  // Data Memory

  assign dmem_addr_o = ex_mem_aluout;

  assign dmem_read_o = ex_mem_load;

  assign dmem_write_o = ex_mem_store;

  assign dmem_data_o = ex_mem_store_value;

  assign dmem_sel_o = ex_mem_store_sel;

  // Decode fields from the Instruction Register

  wire[5:0] if_id_op = if_id_opcode[31:26];                                     // Operation code

  wire[4:0] if_id_rs = if_id_opcode[25:21];                                     // Source register

  wire[4:0] if_id_rt = if_id_opcode[20:16];                                     // Target register

  wire[4:0] if_id_rd = if_id_opcode[15:11];                                     // Destination register

  wire[31:0] if_id_imm_signext = {{16{if_id_opcode[15]}}, if_id_opcode[15:0]};  // Immediate field with sign-extension

  wire[31:0] if_id_imm_zeroext = {16'b0, if_id_opcode[15:0]};                   // Immediate field with zero-extension

  wire[25:0] if_id_index = if_id_opcode[25:0];                                  // Index field

  wire[4:0] if_id_shamt = if_id_opcode[10:6];                                   // Shift amount

  wire[5:0] if_id_func = if_id_opcode[5:0];                                     // Function

  // True for still undecoded operations that read GPR[rs]

  wire if_id_reads_rs = (

    if_id_op==`OPCODE_BEQ || if_id_op==`OPCODE_BNE || if_id_op==`OPCODE_BLEZ || if_id_op==`OPCODE_BGTZ ||

    if_id_op==`OPCODE_ADDI || if_id_op==`OPCODE_ADDIU || if_id_op==`OPCODE_SLTI || if_id_op==`OPCODE_SLTIU ||

    if_id_op==`OPCODE_ANDI || if_id_op==`OPCODE_ORI || if_id_op==`OPCODE_XORI || if_id_op==`OPCODE_LB ||

    if_id_op==`OPCODE_LH || if_id_op==`OPCODE_LWL || if_id_op==`OPCODE_LW || if_id_op==`OPCODE_LBU ||

    if_id_op==`OPCODE_LHU || if_id_op==`OPCODE_LWR || if_id_op==`OPCODE_SB || if_id_op==`OPCODE_SH ||

    if_id_op==`OPCODE_SWL || if_id_op==`OPCODE_SW || if_id_op==`OPCODE_SWR || (

      if_id_op==`OPCODE_SPECIAL && (

        if_id_func==`FUNCTION_SLLV || if_id_func==`FUNCTION_SRLV || if_id_func==`FUNCTION_SRAV ||

        if_id_func==`FUNCTION_JR || if_id_func==`FUNCTION_JALR || if_id_func==`FUNCTION_MTHI ||

        if_id_func==`FUNCTION_MTLO || if_id_func==`FUNCTION_MULT || if_id_func==`FUNCTION_MULTU ||

        if_id_func==`FUNCTION_DIV || if_id_func==`FUNCTION_DIVU || if_id_func==`FUNCTION_ADD ||

        if_id_func==`FUNCTION_ADDU || if_id_func==`FUNCTION_SUB || if_id_func==`FUNCTION_SUBU ||

        if_id_func==`FUNCTION_AND || if_id_func==`FUNCTION_OR || if_id_func==`FUNCTION_XOR ||

        if_id_func==`FUNCTION_NOR || if_id_func==`FUNCTION_SLT || if_id_func==`FUNCTION_SLTU

      )

    ) || (

      if_id_op==`OPCODE_BCOND && (

        if_id_rt==`BCOND_BLTZ || if_id_rt==`BCOND_BGEZ || if_id_rt==`BCOND_BLTZAL || if_id_rt==`BCOND_BGEZAL

      )

   )

  );

  // True for still undecoded operations that read GPR[rt]

  wire if_id_reads_rt = (

    if_id_op==`OPCODE_BEQ || if_id_op==`OPCODE_BNE || if_id_op==`OPCODE_SB || if_id_op==`OPCODE_SH ||

    if_id_op==`OPCODE_SWL || if_id_op==`OPCODE_SW || if_id_op==`OPCODE_SWR || (

      if_id_op==`OPCODE_SPECIAL && (

        if_id_func==`FUNCTION_SLL || if_id_func==`FUNCTION_SRL || if_id_func==`FUNCTION_SRA ||

        if_id_func==`FUNCTION_SLLV || if_id_func==`FUNCTION_SRLV || if_id_func==`FUNCTION_SRAV ||

        if_id_func==`FUNCTION_MULT || if_id_func==`FUNCTION_MULTU || if_id_func==`FUNCTION_DIV ||

        if_id_func==`FUNCTION_DIVU || if_id_func==`FUNCTION_ADD || if_id_func==`FUNCTION_ADDU ||

        if_id_func==`FUNCTION_SUB || if_id_func==`FUNCTION_SUBU || if_id_func==`FUNCTION_AND ||

        if_id_func==`FUNCTION_OR || if_id_func==`FUNCTION_XOR || if_id_func==`FUNCTION_NOR ||

        if_id_func==`FUNCTION_SLT || if_id_func==`FUNCTION_SLTU

      )

    )

  );

  // True for still undecoded operations that read the HI register

  wire if_id_reads_hi = (if_id_op==`OPCODE_SPECIAL && if_id_func==`FUNCTION_MFHI);

  // True for still undecoded operations that read the LO register

  wire if_id_reads_lo = (if_id_op==`OPCODE_SPECIAL && if_id_func==`FUNCTION_MFLO);

  // Finally detect a RAW hazard

  wire raw_detected = (

    (if_id_reads_rs && if_id_rs!=0 &&

      (if_id_rs==id_ex_destreg || if_id_rs==ex_mem_destreg || if_id_rs==mem_wb_destreg)) ||

    (if_id_reads_rt && if_id_rt!=0 &&

      (if_id_rt==id_ex_destreg || if_id_rt==ex_mem_destreg || if_id_rt==mem_wb_destreg)) ||

    (if_id_reads_hi && (id_ex_desthi || ex_mem_desthi || mem_wb_desthi)) ||

    (if_id_reads_lo && (id_ex_destlo || ex_mem_destlo || mem_wb_destlo))

  );

  // Stall signals for all the stages

  wire if_stall, id_stall, ex_stall, mem_stall, wb_stall;

  assign if_stall = id_stall || !imem_done_i;

  assign id_stall = ex_stall || raw_detected;

  assign ex_stall = mem_stall || mul_busy || div_busy;

  assign mem_stall = wb_stall || ( (dmem_read_o||dmem_write_o) && !dmem_done_i);

  assign wb_stall = 0;

  // Name the System Configuration registers

  wire[31:0] BadVAddr = SysCon[`SYSCON_BADVADDR];

  wire[31:0] Status = SysCon[`SYSCON_STATUS];

  wire[31:0] Cause = SysCon[`SYSCON_CAUSE];

  wire[31:0] EPC = SysCon[`SYSCON_EPC];

  wire[31:0] PrID = SysCon[`SYSCON_PRID];

  // Index for GPR initialization

  integer i;

  /*

   * Sequential logic

   */

  always @ (posedge sys_clock_i) begin

    // Initialize all the registers

    if (sys_reset_i==1) begin

      // GPRs initialization

      for(i=0; i<=31; i=i+1) GPR[i] <= 32'h00000000;

      // System registers

      PC <= `BOOT_ADDRESS;

      HI <= 0;

      LO <= 0;

      // Initialize system configuration registers

      for(i=0; i<=31; i=i+1) SysCon[i] <= 32'h00000000;

      // Initialize ABP requests to instantiated modules

      mul_req_o <= 0;

      div_req_o <= 0;

      // Latch 1: IF/ID

      if_id_opcode <= `NOP;

      if_id_addr <= `BOOT_ADDRESS;

      if_id_addrnext <= 0;

      // Latch 2: ID/EX

      id_ex_opcode <= 0;

      id_ex_addr <= 0;

      id_ex_addrnext <= 0;

      id_ex_addrjump <= 0;

      id_ex_addrbranch <= 0;

      id_ex_alu_a <= 0;

      id_ex_alu_b <= 0;

      id_ex_alu_func <= `ALU_OP_ADD;

      id_ex_alu_signed <= 0;

      id_ex_branch <= 0;

      id_ex_jump <= 0;

      id_ex_jr <=0;

      id_ex_linked <= 0;

      id_ex_mult <= 0;

      id_ex_div <= 0;

      id_ex_load <= 0;

      id_ex_store <= 0;

      id_ex_size <= 0;

      id_ex_store_value <= 0;

      id_ex_destreg <= 0;

      id_ex_desthi <= 0;

      id_ex_destlo <= 0;

      ex_mem_opcode <= 0;

      ex_mem_addr <= 0;

      ex_mem_addrnext <= 0;

      ex_mem_addrjump <= 0;

      ex_mem_addrbranch <= 0;

      ex_mem_aluout <= 0;

      ex_mem_carry <= 0;

      ex_mem_branch <= 0;

      ex_mem_jump <= 0;

      ex_mem_jr <= 0;

      ex_mem_linked <= 0;

      ex_mem_mult <= 0;

      ex_mem_div <= 0;

      ex_mem_load <= 0;

      ex_mem_store <= 0;

      ex_mem_store_value <= 0;

      ex_mem_store_sel <= 0;

      ex_mem_destreg <= 0;

      ex_mem_desthi <= 0;

      ex_mem_destlo <= 0;

      // Latch 4: MEM/WB

      mem_wb_opcode <= 0;

      mem_wb_addr <= 0;

      mem_wb_addrnext <= 0;

      mem_wb_value <= 0;

      mem_wb_destreg <= 0;

      mem_wb_desthi <= 0;

      mem_wb_destlo <= 0;

    end else begin

      $display("================> Time %t <================", $time);

      /*

       * Pipeline Stage 1: Instruction Fetch (IF)

       *

       * READ/WRITE:

       * - read memory

       * - write the IF/ID latch

       * - write the PC register

       *

       * DESCRIPTION:

       * This stage usually reads the next instruction from the PC address in memory and

       * then updates the PC value by incrementing it by 4.

       * When a hazard is detected this stage is idle.

       */

      // A RAW hazard will stall the CPU

      if(if_stall) begin

        if(id_stall) begin

          $display("INFO: CPU(%m)-IF: Fetching stalled and latch kept for following stalled pipeline stage");

        end else begin

          $display("INFO: CPU(%m)-IF: Fetching stalled and bubble inserted for following running pipeline stage");

          if_id_opcode <= `BUBBLE;

        end

      end else begin

        // If branch taken update the Program Counter

        if(ex_mem_branch==1 && ex_mem_aluout==32'h00000001) begin

          $display("INFO: CPU(%m)-IF: Bubble inserted due branch taken in EX/MEM instruction @ADDR=%X w/OPCODE=%X having ALUout=%X", ex_mem_addr, ex_mem_opcode, ex_mem_aluout);

          if_id_opcode <= `BUBBLE;

          PC <= ex_mem_addrbranch;

        // Jump to the required immediate address

        end else if(id_ex_jump==1) begin

          $display("INFO: CPU(%m)-IF: Bubble inserted due to jump in ID/EX instruction @ADDR=%X w/OPCODE=%X", id_ex_addr, id_ex_opcode);

          if_id_opcode <= `BUBBLE;

          PC <= id_ex_addrjump;

        // Jump to the required address stored in GPR

        end else if(id_ex_jr==1) begin

          $display("INFO: CPU(%m)-IF: Bubble inserted due to jump register in ID/EX instruction @ADDR=%X w/OPCODE=%X", id_ex_addr, id_ex_opcode);

          if_id_opcode <= `BUBBLE;

          PC <= id_ex_addrjr;

        // Normal execution

        end else begin

          $display("INFO: CPU(%m)-IF: Fetched from Program Counter @ADDR=%h getting OPCODE=%X", PC, imem_data_i);

          if_id_opcode <= imem_data_i;

          if_id_addr <= PC;

          if_id_addrnext <= PCnext;

          PC <= PCnext;

        end

      end

      /*

       * Pipeline Stage 2: Instruction Decode (ID)

       *

       * READ/WRITE:

       * - read the IF/ID latch

       * - read the register file

       * - write the ID/EX latch

       *

       * DESCRIPTION:

       * This stage decodes the instruction and puts the values for the ALU inputs

       */

      if(id_stall) begin

        if(ex_stall) begin

          $display("INFO: CPU(%m)-ID: Decoding stalled and latch kept for following stalled pipeline stage");

        end else begin

          $display("INFO: CPU(%m)-ID: Decoding stalled and bubble inserted for following running pipeline stage");

          id_ex_opcode <=`BUBBLE;

          id_ex_alu_a <= 0;

          id_ex_alu_b <= 0;

          id_ex_alu_func <= `ALU_OP_ADD;

          id_ex_alu_signed <= 0;

          id_ex_addr <= if_id_addr;

          id_ex_addrnext <= 0;

          id_ex_addrjump <= 0;

          id_ex_addrbranch <= 0;

          id_ex_branch <= 0;

          id_ex_jump <= 0;

          id_ex_jr <= 0;

          id_ex_linked <= 0;

          id_ex_mult <= 0;

          id_ex_div <= 0;

          id_ex_load <= 0;

          id_ex_store <= 0;

          id_ex_destreg <= 0;

          id_ex_desthi <= 0;

          id_ex_destlo <= 0;

        end

      end else begin

        id_ex_opcode <= if_id_opcode;

        id_ex_addr <= if_id_addr;

        id_ex_addrnext <= if_id_addrnext;

        id_ex_addrbranch <= if_id_addrnext + {if_id_imm_signext[29:0], 2'b00};

        id_ex_addrjump <= {if_id_addr[31:28], if_id_index, 2'b00};

        id_ex_addrjr <= GPR[if_id_rs];

        if(if_id_opcode==`BUBBLE) begin

          $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BUBBLE", if_id_addr, if_id_opcode);

          id_ex_alu_a <= 0;

          id_ex_alu_b <= 0;

          id_ex_alu_func <= `ALU_OP_ADD;

          id_ex_alu_signed <= 0;

          id_ex_branch <= 0;

          id_ex_jump <= 0;

          id_ex_jr <= 0;

          id_ex_linked <= 0;

          id_ex_mult <= 0;

          id_ex_div <= 0;

          id_ex_load <= 0;

          id_ex_store <= 0;

          id_ex_size <= 0;

          id_ex_store_value <= 0;

          id_ex_destreg <= 0;

          id_ex_desthi <= 0;

          id_ex_destlo <= 0;

        end else case(if_id_op)

          `OPCODE_J:

            begin

              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as J %h", if_id_addr, if_id_opcode, if_id_index);

              id_ex_alu_a <= 0;

              id_ex_alu_b <= 0;

              id_ex_alu_func <= `ALU_OP_ADD;

              id_ex_alu_signed <= 0;

              id_ex_branch <= 0;

              id_ex_jump <= 1;

              id_ex_jr <= 0;

              id_ex_linked <= 0;

              id_ex_mult <= 0;

              id_ex_div <= 0;

              id_ex_load <= 0;

              id_ex_store <= 0;

              id_ex_size <= 0;

              id_ex_store_value <= 0;

              id_ex_destreg <= 0;

              id_ex_desthi <= 0;

              id_ex_destlo <= 0;

            end

          `OPCODE_JAL:

            begin

              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as JAL %h", if_id_addr, if_id_opcode, if_id_index);

              id_ex_alu_a <= if_id_addrnext;

              id_ex_alu_b <= 4;

              id_ex_alu_func <= `ALU_OP_ADD;

              id_ex_alu_signed <= 0;

              id_ex_branch <= 0;

              id_ex_jump <= 1;

              id_ex_jr <= 0;

              id_ex_linked <= 1;

              id_ex_mult <= 0;

              id_ex_div <= 0;

              id_ex_load <= 0;

              id_ex_store <= 0;

              id_ex_size <= 0;

              id_ex_store_value <= 0;

              id_ex_destreg <= 31;

              id_ex_desthi <= 0;

              id_ex_destlo <= 0;

            end

          `OPCODE_BEQ:

            begin

              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BEQ r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_rt, if_id_imm_signext);

              id_ex_alu_a <= GPR[if_id_rs];

              id_ex_alu_b <= GPR[if_id_rt];

              id_ex_alu_func <= `ALU_OP_SEQ;

              id_ex_alu_signed <= 0;

              id_ex_branch <= 1;

              id_ex_jump <= 0;

              id_ex_jr <= 0;

              id_ex_linked <= 0;

              id_ex_mult <= 0;

              id_ex_div <= 0;

              id_ex_load <= 0;

              id_ex_store <= 0;

              id_ex_size <= 0;

              id_ex_store_value <= 0;

              id_ex_destreg <= 0;

              id_ex_desthi <= 0;

              id_ex_destlo <= 0;

            end

          `OPCODE_BNE:

            begin

              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BNE r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_rt, if_id_imm_signext);

              id_ex_alu_a <= GPR[if_id_rs];

              id_ex_alu_b <= GPR[if_id_rt];

              id_ex_alu_func <= `ALU_OP_SNE;

              id_ex_alu_signed <= 0;

              id_ex_branch <= 1;

              id_ex_jump <= 0;

              id_ex_jr <= 0;

              id_ex_linked <= 0;

              id_ex_mult <= 0;

              id_ex_div <= 0;

              id_ex_load <= 0;

              id_ex_store <= 0;

              id_ex_size <= 0;

              id_ex_store_value <= 0;

              id_ex_destreg <= 0;

              id_ex_desthi <= 0;

              id_ex_destlo <= 0;

            end

          `OPCODE_BLEZ:

            begin

              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BLEZ r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);

              id_ex_alu_a <= GPR[if_id_rs];

              id_ex_alu_b <= 0;

              id_ex_alu_func <= `ALU_OP_SLE;

              id_ex_alu_signed <= 0;

              id_ex_branch <= 1;

              id_ex_jump <= 0;

              id_ex_jr <= 0;

              id_ex_linked <= 0;

              id_ex_mult <= 0;

              id_ex_div <= 0;

              id_ex_load <= 0;

              id_ex_store <= 0;

              id_ex_size <= 0;

              id_ex_store_value <= 0;

              id_ex_destreg <= 0;

              id_ex_desthi <= 0;

              id_ex_destlo <= 0;

            end

          `OPCODE_BGTZ:

            begin

              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BGTZ r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);

              id_ex_alu_a <= GPR[if_id_rs];

              id_ex_alu_b <= 0;

              id_ex_alu_func <= `ALU_OP_SGT;

              id_ex_alu_signed <= 0;

              id_ex_branch <= 1;

              id_ex_jump <= 0;

              id_ex_jr <= 0;

              id_ex_linked <= 0;

              id_ex_mult <= 0;

              id_ex_div <= 0;

              id_ex_load <= 0;

              id_ex_store <= 0;

              id_ex_size <= 0;

              id_ex_store_value <= 0;

              id_ex_destreg <= 0;

              id_ex_desthi <= 0;

              id_ex_destlo <= 0;

            end

          `OPCODE_ADDI:

            begin

              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ADDI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);

              id_ex_alu_a <= GPR[if_id_rs];

              id_ex_alu_b <= if_id_imm_signext;

              id_ex_alu_func <= `ALU_OP_ADD;

              id_ex_alu_signed <= 1;

              id_ex_branch <= 0;

              id_ex_jump <= 0;

              id_ex_jr <= 0;

              id_ex_linked <= 0;

              id_ex_mult <= 0;

              id_ex_div <= 0;

              id_ex_load <= 0;

              id_ex_store <= 0;

              id_ex_size <= 0;

              id_ex_store_value <= 0;

              id_ex_destreg <= if_id_rt;

              id_ex_desthi <= 0;

              id_ex_destlo <= 0;

            end

          `OPCODE_ADDIU:

            begin

              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ADDIU r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);

              id_ex_alu_a <= GPR[if_id_rs];

              id_ex_alu_b <= if_id_imm_signext;

              id_ex_alu_func <= `ALU_OP_ADD;

              id_ex_alu_signed <= 0;

              id_ex_branch <= 0;

              id_ex_jump <= 0;

              id_ex_jr <= 0;

              id_ex_linked <= 0;

              id_ex_mult <= 0;

              id_ex_div <= 0;

              id_ex_load <= 0;

              id_ex_store <= 0;

              id_ex_size <= 0;

              id_ex_store_value <= 0;

              id_ex_destreg <= if_id_rt;

              id_ex_desthi <= 0;

              id_ex_destlo <= 0;

            end

          `OPCODE_SLTI:

            begin

              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLTI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);

              id_ex_alu_a <= GPR[if_id_rs];

              id_ex_alu_b <= if_id_imm_signext;

              id_ex_alu_func <= `ALU_OP_SLT;

              id_ex_alu_signed <= 1;

              id_ex_branch <= 0;

              id_ex_jump <= 0;

              id_ex_jr <= 0;

              id_ex_linked <= 0;

              id_ex_mult <= 0;

              id_ex_div <= 0;

              id_ex_load <= 0;