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[/] [m1_core/] [trunk/] [hdl/] [rtl/] [m1_core/] [m1_cpu.v] - Blame information for rev 51

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1 33 fafa1971
/*
2
 * Simply RISC M1 Central Processing Unit
3
 */
4
 
5
`include "m1_defs.vh"
6
 
7
module m1_cpu (
8
 
9
    // System
10
    input sys_clock_i,                            // System Clock
11
    input sys_reset_i,                            // System Reset
12
    input sys_irq_i,                              // Interrupt Request
13
 
14
    // ALU
15
    output[31:0] alu_a_o,                         // ALU Operand A
16
    output[31:0] alu_b_o,                         // ALU Operand B
17
    output[4:0] alu_func_o,                       // ALU Function
18
    output alu_signed_o,                          // ALU operation is Signed
19 48 fafa1971
    input[32:0] alu_result_i,                     // ALU Result with Carry
20 33 fafa1971
 
21
    // Multiplier
22
    output reg mul_req_o,                         // Multiplier Request
23
    output[31:0] mul_a_o,                         // Multiplier Operand A
24
    output[31:0] mul_b_o,                         // Multiplier Operand B
25
    output mul_signed_o,                          // Multiplication is Signed
26
    input mul_ack_i,                              // Multiplier Ack
27
    input[63:0] mul_product_i,                    // Multiplier Product
28
 
29
    // Divider
30
    output reg div_req_o,                         // Divider Request
31
    output[31:0] div_a_o,                         // Divider Operand A
32
    output[31:0] div_b_o,                         // Divider Operand B
33
    output div_signed_o,                          // Division is Signed
34
    input div_ack_i,                              // Divider Ack
35
    input[31:0] div_quotient_i,                   // Divider Quotient
36
    input[31:0] div_remainder_i,                  // Divider Remainder
37
 
38
    // Instruction Memory
39
    output imem_read_o,                           // I$ Read
40
    output[31:0] imem_addr_o,                     // I$ Address
41
    input imem_done_i,                            // I$ Done
42
    input[31:0] imem_data_i,                      // I$ Data
43
 
44
    // Data Memory
45
    output dmem_read_o,                           // D$ Read
46
    output dmem_write_o,                          // D$ Write
47
    output[3:0] dmem_sel_o,                       // D$ Byte selector
48
    output[31:0] dmem_addr_o,                     // D$ Address
49
    output[31:0] dmem_data_o,                     // D$ Write Data
50
    input dmem_done_i,                            // D$ Done
51
    input[31:0] dmem_data_i                       // D$ Read Data
52
 
53
  );
54
 
55
  /*
56
   * Registers
57
   */
58
 
59
  // Register file
60 46 fafa1971
  reg[31:0] GPR[31:0];                            // General Purpose Registers
61
  reg[31:0] PC;                                   // Program Counter
62
  reg[31:0] HI, LO;                               // HI and LO registers (for multiplication/division)
63
  reg[31:0] SysCon[0:31];                         // System Control registers
64
 
65 33 fafa1971
  /*
66
   * Pipeline latches
67
   */
68
 
69
  // Latch 1: IF/ID
70
  reg[31:0] if_id_opcode;                                            // Instruction Register
71
  reg[31:0] if_id_addr, if_id_addrnext;                              // Addresses of the fetched opcode and of the next one
72
 
73
  // Latch 2: ID/EX
74
  reg[31:0] id_ex_opcode;
75
  reg[31:0] id_ex_addr, id_ex_addrnext;
76
  reg[31:0] id_ex_addrbranch, id_ex_addrjump, id_ex_addrjr;          // Evaluated jump addresses
77
  reg[31:0] id_ex_alu_a, id_ex_alu_b;                                // ALU operands
78
  reg[4:0] id_ex_alu_func;                                           // ALU operation code
79
  reg id_ex_alu_signed;                                              // ALU operation is signed
80
  reg id_ex_branch, id_ex_jump, id_ex_jr, id_ex_linked;              // Instruction is a jump
81
  reg id_ex_mult, id_ex_div;                                         // Instruction is a multiplication/division
82
  reg id_ex_load, id_ex_store;                                       // Instruction is a load/store
83
  reg[2:0] id_ex_size;                                               // Load/store size (see defs.h)
84
  reg[31:0] id_ex_store_value;                                       // Store value
85
  reg[4:0] id_ex_destreg;                                            // Destination register (GPR number)
86
  reg id_ex_desthi, id_ex_destlo;                                    // Destination register (HI/LO)
87 46 fafa1971
  reg[4:0] id_ex_destsyscon;                                         // Destination register (System Control)
88 33 fafa1971
 
89
  // Latch 3: EX/MEM
90
  reg[31:0] ex_mem_opcode;
91
  reg[31:0] ex_mem_addr, ex_mem_addrnext;
92
  reg[31:0] ex_mem_addrbranch, ex_mem_addrjump, ex_mem_addrjr;
93
  reg[63:0] ex_mem_aluout;                                           // ALU result
94 48 fafa1971
  reg ex_mem_carry;                                                  // ALU carry
95 33 fafa1971
  reg ex_mem_branch, ex_mem_jump, ex_mem_jr, ex_mem_linked;
96
  reg ex_mem_mult, ex_mem_div;
97 50 fafa1971
  reg ex_mem_load, ex_mem_store;
98
  reg[2:0] ex_mem_size;
99 33 fafa1971
  reg[31:0] ex_mem_store_value;
100
  reg[3:0] ex_mem_store_sel;                                         // Byte Selector on Stores
101 51 fafa1971
  reg[31:0] ex_mem_destold;                                          // Old value for partial rewrite
102 33 fafa1971
  reg[4:0] ex_mem_destreg;
103
  reg ex_mem_desthi, ex_mem_destlo;
104 46 fafa1971
  reg[4:0] ex_mem_destsyscon;
105
 
106 33 fafa1971
  // Latch 4: MEM/WB
107
  reg[31:0] mem_wb_opcode;
108
  reg[31:0] mem_wb_addr, mem_wb_addrnext;
109
  reg[63:0] mem_wb_value;                                            // Write-back value
110
  reg[4:0] mem_wb_destreg;
111
  reg mem_wb_desthi, mem_wb_destlo;
112 46 fafa1971
  reg [4:0] mem_wb_destsyscon;
113 33 fafa1971
 
114
  /*
115
   * Combinational logic
116 46 fafa1971
   */
117 33 fafa1971
 
118
  // ALU
119
  assign alu_a_o = id_ex_alu_a;
120
  assign alu_b_o = id_ex_alu_b;
121
  assign alu_func_o = id_ex_alu_func;
122
  assign alu_signed_o = id_ex_alu_signed;
123
 
124
  // Multiplier
125
  assign mul_a_o = id_ex_alu_a;
126
  assign mul_b_o = id_ex_alu_b;
127
  assign mul_signed_o = id_ex_alu_signed;
128
  wire mul_ready = (mul_req_o==mul_ack_i);  // Convert ABP ack to true/false format
129
  wire mul_busy = !mul_ready;
130
 
131
  // Divider
132
  assign div_a_o = id_ex_alu_a;
133
  assign div_b_o = id_ex_alu_b;
134
  assign div_signed_o = id_ex_alu_signed;
135
  wire div_ready = (div_req_o==div_ack_i);  // Convert ABP ack to true/false format
136
  wire div_busy = !div_ready;
137
 
138
  // Incremented Program Counter
139
  wire[31:0] PCnext = PC + 4;
140
 
141
  // Instruction Memory
142
  assign imem_read_o = 1;
143
  assign imem_addr_o = PC;
144
 
145
  // Data Memory
146
  assign dmem_addr_o = ex_mem_aluout;
147
  assign dmem_read_o = ex_mem_load;
148
  assign dmem_write_o = ex_mem_store;
149
  assign dmem_data_o = ex_mem_store_value;
150
  assign dmem_sel_o = ex_mem_store_sel;
151
 
152
  // Decode fields from the Instruction Register
153
  wire[5:0] if_id_op = if_id_opcode[31:26];                                     // Operation code
154
  wire[4:0] if_id_rs = if_id_opcode[25:21];                                     // Source register
155
  wire[4:0] if_id_rt = if_id_opcode[20:16];                                     // Target register
156
  wire[4:0] if_id_rd = if_id_opcode[15:11];                                     // Destination register
157
  wire[31:0] if_id_imm_signext = {{16{if_id_opcode[15]}}, if_id_opcode[15:0]};  // Immediate field with sign-extension
158
  wire[31:0] if_id_imm_zeroext = {16'b0, if_id_opcode[15:0]};                   // Immediate field with zero-extension
159
  wire[25:0] if_id_index = if_id_opcode[25:0];                                  // Index field
160
  wire[4:0] if_id_shamt = if_id_opcode[10:6];                                   // Shift amount
161
  wire[5:0] if_id_func = if_id_opcode[5:0];                                     // Function
162
 
163
  // True for still undecoded operations that read GPR[rs]
164
  wire if_id_reads_rs = (
165
    if_id_op==`OPCODE_BEQ || if_id_op==`OPCODE_BNE || if_id_op==`OPCODE_BLEZ || if_id_op==`OPCODE_BGTZ ||
166
    if_id_op==`OPCODE_ADDI || if_id_op==`OPCODE_ADDIU || if_id_op==`OPCODE_SLTI || if_id_op==`OPCODE_SLTIU ||
167
    if_id_op==`OPCODE_ANDI || if_id_op==`OPCODE_ORI || if_id_op==`OPCODE_XORI || if_id_op==`OPCODE_LB ||
168
    if_id_op==`OPCODE_LH || if_id_op==`OPCODE_LWL || if_id_op==`OPCODE_LW || if_id_op==`OPCODE_LBU ||
169
    if_id_op==`OPCODE_LHU || if_id_op==`OPCODE_LWR || if_id_op==`OPCODE_SB || if_id_op==`OPCODE_SH ||
170
    if_id_op==`OPCODE_SWL || if_id_op==`OPCODE_SW || if_id_op==`OPCODE_SWR || (
171
      if_id_op==`OPCODE_SPECIAL && (
172
        if_id_func==`FUNCTION_SLLV || if_id_func==`FUNCTION_SRLV || if_id_func==`FUNCTION_SRAV ||
173
        if_id_func==`FUNCTION_JR || if_id_func==`FUNCTION_JALR || if_id_func==`FUNCTION_MTHI ||
174
        if_id_func==`FUNCTION_MTLO || if_id_func==`FUNCTION_MULT || if_id_func==`FUNCTION_MULTU ||
175
        if_id_func==`FUNCTION_DIV || if_id_func==`FUNCTION_DIVU || if_id_func==`FUNCTION_ADD ||
176
        if_id_func==`FUNCTION_ADDU || if_id_func==`FUNCTION_SUB || if_id_func==`FUNCTION_SUBU ||
177
        if_id_func==`FUNCTION_AND || if_id_func==`FUNCTION_OR || if_id_func==`FUNCTION_XOR ||
178
        if_id_func==`FUNCTION_NOR || if_id_func==`FUNCTION_SLT || if_id_func==`FUNCTION_SLTU
179
      )
180
    ) || (
181
      if_id_op==`OPCODE_BCOND && (
182
        if_id_rt==`BCOND_BLTZ || if_id_rt==`BCOND_BGEZ || if_id_rt==`BCOND_BLTZAL || if_id_rt==`BCOND_BGEZAL
183
      )
184
   )
185
  );
186
 
187
  // True for still undecoded operations that read GPR[rt]
188
  wire if_id_reads_rt = (
189
    if_id_op==`OPCODE_BEQ || if_id_op==`OPCODE_BNE || if_id_op==`OPCODE_SB || if_id_op==`OPCODE_SH ||
190
    if_id_op==`OPCODE_SWL || if_id_op==`OPCODE_SW || if_id_op==`OPCODE_SWR || (
191
      if_id_op==`OPCODE_SPECIAL && (
192
        if_id_func==`FUNCTION_SLL || if_id_func==`FUNCTION_SRL || if_id_func==`FUNCTION_SRA ||
193
        if_id_func==`FUNCTION_SLLV || if_id_func==`FUNCTION_SRLV || if_id_func==`FUNCTION_SRAV ||
194
        if_id_func==`FUNCTION_MULT || if_id_func==`FUNCTION_MULTU || if_id_func==`FUNCTION_DIV ||
195
        if_id_func==`FUNCTION_DIVU || if_id_func==`FUNCTION_ADD || if_id_func==`FUNCTION_ADDU ||
196
        if_id_func==`FUNCTION_SUB || if_id_func==`FUNCTION_SUBU || if_id_func==`FUNCTION_AND ||
197
        if_id_func==`FUNCTION_OR || if_id_func==`FUNCTION_XOR || if_id_func==`FUNCTION_NOR ||
198
        if_id_func==`FUNCTION_SLT || if_id_func==`FUNCTION_SLTU
199
      )
200
    )
201
  );
202
 
203
  // True for still undecoded operations that read the HI register
204
  wire if_id_reads_hi = (if_id_op==`OPCODE_SPECIAL && if_id_func==`FUNCTION_MFHI);
205
 
206
  // True for still undecoded operations that read the LO register
207
  wire if_id_reads_lo = (if_id_op==`OPCODE_SPECIAL && if_id_func==`FUNCTION_MFLO);
208
 
209
  // Finally detect a RAW hazard
210
  wire raw_detected = (
211
    (if_id_reads_rs && if_id_rs!=0 &&
212
      (if_id_rs==id_ex_destreg || if_id_rs==ex_mem_destreg || if_id_rs==mem_wb_destreg)) ||
213
    (if_id_reads_rt && if_id_rt!=0 &&
214
      (if_id_rt==id_ex_destreg || if_id_rt==ex_mem_destreg || if_id_rt==mem_wb_destreg)) ||
215
    (if_id_reads_hi && (id_ex_desthi || ex_mem_desthi || mem_wb_desthi)) ||
216
    (if_id_reads_lo && (id_ex_destlo || ex_mem_destlo || mem_wb_destlo))
217
  );
218
 
219
  // Stall signals for all the stages
220
  wire if_stall, id_stall, ex_stall, mem_stall, wb_stall;
221
  assign if_stall = id_stall || !imem_done_i;
222
  assign id_stall = ex_stall || raw_detected;
223
  assign ex_stall = mem_stall || mul_busy || div_busy;
224
  assign mem_stall = wb_stall || ( (dmem_read_o||dmem_write_o) && !dmem_done_i);
225
  assign wb_stall = 0;
226
 
227 46 fafa1971
  // Name the System Configuration registers
228
  wire[31:0] BadVAddr = SysCon[`SYSCON_BADVADDR];
229
  wire[31:0] Status = SysCon[`SYSCON_STATUS];
230
  wire[31:0] Cause = SysCon[`SYSCON_CAUSE];
231
  wire[31:0] EPC = SysCon[`SYSCON_EPC];
232
  wire[31:0] PrID = SysCon[`SYSCON_PRID];
233
 
234 33 fafa1971
  // Index for GPR initialization
235
  integer i;
236
 
237
  /*
238
   * Sequential logic
239
   */
240
 
241
  always @ (posedge sys_clock_i) begin
242
 
243
    // Initialize all the registers
244
    if (sys_reset_i==1) begin
245
 
246
      // GPRs initialization
247
      for(i=0; i<=31; i=i+1) GPR[i] <= 32'h00000000;
248
 
249
      // System registers
250
      PC <= `BOOT_ADDRESS;
251
      HI <= 0;
252
      LO <= 0;
253
 
254 46 fafa1971
      // Initialize system configuration registers
255
      for(i=0; i<=31; i=i+1) SysCon[i] <= 32'h00000000;
256
 
257 33 fafa1971
      // Initialize ABP requests to instantiated modules
258
      mul_req_o <= 0;
259
      div_req_o <= 0;
260
 
261
      // Latch 1: IF/ID
262
      if_id_opcode <= `NOP;
263
      if_id_addr <= `BOOT_ADDRESS;
264
      if_id_addrnext <= 0;
265
 
266
      // Latch 2: ID/EX
267
      id_ex_opcode <= 0;
268
      id_ex_addr <= 0;
269
      id_ex_addrnext <= 0;
270
      id_ex_addrjump <= 0;
271
      id_ex_addrbranch <= 0;
272
      id_ex_alu_a <= 0;
273
      id_ex_alu_b <= 0;
274
      id_ex_alu_func <= `ALU_OP_ADD;
275
      id_ex_alu_signed <= 0;
276
      id_ex_branch <= 0;
277
      id_ex_jump <= 0;
278
      id_ex_jr <=0;
279
      id_ex_linked <= 0;
280
      id_ex_mult <= 0;
281
      id_ex_div <= 0;
282
      id_ex_load <= 0;
283
      id_ex_store <= 0;
284
      id_ex_size <= 0;
285
      id_ex_store_value <= 0;
286
      id_ex_destreg <= 0;
287
      id_ex_desthi <= 0;
288
      id_ex_destlo <= 0;
289
 
290
      ex_mem_opcode <= 0;
291
      ex_mem_addr <= 0;
292
      ex_mem_addrnext <= 0;
293
      ex_mem_addrjump <= 0;
294
      ex_mem_addrbranch <= 0;
295
      ex_mem_aluout <= 0;
296 49 fafa1971
      ex_mem_carry <= 0;
297 33 fafa1971
      ex_mem_branch <= 0;
298
      ex_mem_jump <= 0;
299
      ex_mem_jr <= 0;
300
      ex_mem_linked <= 0;
301
      ex_mem_mult <= 0;
302
      ex_mem_div <= 0;
303
      ex_mem_load <= 0;
304
      ex_mem_store <= 0;
305
      ex_mem_store_value <= 0;
306
      ex_mem_store_sel <= 0;
307
      ex_mem_destreg <= 0;
308
      ex_mem_desthi <= 0;
309
      ex_mem_destlo <= 0;
310
 
311
      // Latch 4: MEM/WB
312
      mem_wb_opcode <= 0;
313
      mem_wb_addr <= 0;
314
      mem_wb_addrnext <= 0;
315
      mem_wb_value <= 0;
316
      mem_wb_destreg <= 0;
317
      mem_wb_desthi <= 0;
318
      mem_wb_destlo <= 0;
319
 
320
    end else begin
321
 
322
      $display("================> Time %t <================", $time);
323
 
324
      /*
325
       * Pipeline Stage 1: Instruction Fetch (IF)
326
       *
327
       * READ/WRITE:
328
       * - read memory
329
       * - write the IF/ID latch
330
       * - write the PC register
331
       *
332
       * DESCRIPTION:
333
       * This stage usually reads the next instruction from the PC address in memory and
334
       * then updates the PC value by incrementing it by 4.
335
       * When a hazard is detected this stage is idle.
336
       */
337
 
338
      // A RAW hazard will stall the CPU
339
      if(if_stall) begin
340
 
341
        if(id_stall) begin
342
          $display("INFO: CPU(%m)-IF: Fetching stalled and latch kept for following stalled pipeline stage");
343
        end else begin
344
          $display("INFO: CPU(%m)-IF: Fetching stalled and bubble inserted for following running pipeline stage");
345
          if_id_opcode <= `BUBBLE;
346
        end
347
 
348
      end else begin
349
 
350 49 fafa1971
        // If branch taken update the Program Counter
351 33 fafa1971
        if(ex_mem_branch==1 && ex_mem_aluout==32'h00000001) begin
352
 
353
          $display("INFO: CPU(%m)-IF: Bubble inserted due branch taken in EX/MEM instruction @ADDR=%X w/OPCODE=%X having ALUout=%X", ex_mem_addr, ex_mem_opcode, ex_mem_aluout);
354
          if_id_opcode <= `BUBBLE;
355
          PC <= ex_mem_addrbranch;
356
 
357 49 fafa1971
        // Jump to the required immediate address
358 33 fafa1971
        end else if(id_ex_jump==1) begin
359
 
360
          $display("INFO: CPU(%m)-IF: Bubble inserted due to jump in ID/EX instruction @ADDR=%X w/OPCODE=%X", id_ex_addr, id_ex_opcode);
361
          if_id_opcode <= `BUBBLE;
362
          PC <= id_ex_addrjump;
363
 
364
        // Jump to the required address stored in GPR
365
        end else if(id_ex_jr==1) begin
366
 
367
          $display("INFO: CPU(%m)-IF: Bubble inserted due to jump register in ID/EX instruction @ADDR=%X w/OPCODE=%X", id_ex_addr, id_ex_opcode);
368
          if_id_opcode <= `BUBBLE;
369
          PC <= id_ex_addrjr;
370
 
371
        // Normal execution
372
        end else begin
373
 
374
          $display("INFO: CPU(%m)-IF: Fetched from Program Counter @ADDR=%h getting OPCODE=%X", PC, imem_data_i);
375
          if_id_opcode <= imem_data_i;
376
          if_id_addr <= PC;
377
          if_id_addrnext <= PCnext;
378
          PC <= PCnext;
379
 
380
        end
381
      end
382
 
383
      /*
384
       * Pipeline Stage 2: Instruction Decode (ID)
385
       *
386
       * READ/WRITE:
387
       * - read the IF/ID latch
388
       * - read the register file
389
       * - write the ID/EX latch
390
       *
391
       * DESCRIPTION:
392
       * This stage decodes the instruction and puts the values for the ALU inputs
393
       */
394
 
395
      if(id_stall) begin
396
 
397
        if(ex_stall) begin
398
          $display("INFO: CPU(%m)-ID: Decoding stalled and latch kept for following stalled pipeline stage");
399
        end else begin
400
          $display("INFO: CPU(%m)-ID: Decoding stalled and bubble inserted for following running pipeline stage");
401
          id_ex_opcode <=`BUBBLE;
402
          id_ex_alu_a <= 0;
403
          id_ex_alu_b <= 0;
404
          id_ex_alu_func <= `ALU_OP_ADD;
405
          id_ex_alu_signed <= 0;
406
          id_ex_addr <= if_id_addr;
407
          id_ex_addrnext <= 0;
408
          id_ex_addrjump <= 0;
409
          id_ex_addrbranch <= 0;
410
          id_ex_branch <= 0;
411
          id_ex_jump <= 0;
412
          id_ex_jr <= 0;
413
          id_ex_linked <= 0;
414
          id_ex_mult <= 0;
415
          id_ex_div <= 0;
416
          id_ex_load <= 0;
417
          id_ex_store <= 0;
418
          id_ex_destreg <= 0;
419
          id_ex_desthi <= 0;
420
          id_ex_destlo <= 0;
421
        end
422
      end else begin
423
        id_ex_opcode <= if_id_opcode;
424
        id_ex_addr <= if_id_addr;
425
        id_ex_addrnext <= if_id_addrnext;
426
        id_ex_addrbranch <= if_id_addrnext + {if_id_imm_signext[29:0], 2'b00};
427
        id_ex_addrjump <= {if_id_addr[31:28], if_id_index, 2'b00};
428
        id_ex_addrjr <= GPR[if_id_rs];
429
 
430
        if(if_id_opcode==`BUBBLE) begin
431
          $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BUBBLE", if_id_addr, if_id_opcode);
432
          id_ex_alu_a <= 0;
433
          id_ex_alu_b <= 0;
434
          id_ex_alu_func <= `ALU_OP_ADD;
435
          id_ex_alu_signed <= 0;
436
          id_ex_branch <= 0;
437
          id_ex_jump <= 0;
438
          id_ex_jr <= 0;
439
          id_ex_linked <= 0;
440
          id_ex_mult <= 0;
441
          id_ex_div <= 0;
442
          id_ex_load <= 0;
443
          id_ex_store <= 0;
444
          id_ex_size <= 0;
445
          id_ex_store_value <= 0;
446
          id_ex_destreg <= 0;
447
          id_ex_desthi <= 0;
448
          id_ex_destlo <= 0;
449
        end else case(if_id_op)
450
          `OPCODE_J:
451
            begin
452
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as J %h", if_id_addr, if_id_opcode, if_id_index);
453
              id_ex_alu_a <= 0;
454
              id_ex_alu_b <= 0;
455
              id_ex_alu_func <= `ALU_OP_ADD;
456
              id_ex_alu_signed <= 0;
457
              id_ex_branch <= 0;
458
              id_ex_jump <= 1;
459
              id_ex_jr <= 0;
460
              id_ex_linked <= 0;
461
              id_ex_mult <= 0;
462
              id_ex_div <= 0;
463
              id_ex_load <= 0;
464
              id_ex_store <= 0;
465
              id_ex_size <= 0;
466
              id_ex_store_value <= 0;
467
              id_ex_destreg <= 0;
468
              id_ex_desthi <= 0;
469
              id_ex_destlo <= 0;
470
            end
471
          `OPCODE_JAL:
472
            begin
473
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as JAL %h", if_id_addr, if_id_opcode, if_id_index);
474
              id_ex_alu_a <= if_id_addrnext;
475
              id_ex_alu_b <= 4;
476
              id_ex_alu_func <= `ALU_OP_ADD;
477
              id_ex_alu_signed <= 0;
478
              id_ex_branch <= 0;
479
              id_ex_jump <= 1;
480
              id_ex_jr <= 0;
481
              id_ex_linked <= 1;
482
              id_ex_mult <= 0;
483
              id_ex_div <= 0;
484
              id_ex_load <= 0;
485
              id_ex_store <= 0;
486
              id_ex_size <= 0;
487
              id_ex_store_value <= 0;
488
              id_ex_destreg <= 31;
489
              id_ex_desthi <= 0;
490
              id_ex_destlo <= 0;
491
            end
492
          `OPCODE_BEQ:
493
            begin
494
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BEQ r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_rt, if_id_imm_signext);
495
              id_ex_alu_a <= GPR[if_id_rs];
496
              id_ex_alu_b <= GPR[if_id_rt];
497
              id_ex_alu_func <= `ALU_OP_SEQ;
498
              id_ex_alu_signed <= 0;
499
              id_ex_branch <= 1;
500
              id_ex_jump <= 0;
501
              id_ex_jr <= 0;
502
              id_ex_linked <= 0;
503
              id_ex_mult <= 0;
504
              id_ex_div <= 0;
505
              id_ex_load <= 0;
506
              id_ex_store <= 0;
507
              id_ex_size <= 0;
508
              id_ex_store_value <= 0;
509
              id_ex_destreg <= 0;
510
              id_ex_desthi <= 0;
511
              id_ex_destlo <= 0;
512
            end
513
          `OPCODE_BNE:
514
            begin
515
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BNE r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_rt, if_id_imm_signext);
516
              id_ex_alu_a <= GPR[if_id_rs];
517
              id_ex_alu_b <= GPR[if_id_rt];
518
              id_ex_alu_func <= `ALU_OP_SNE;
519
              id_ex_alu_signed <= 0;
520
              id_ex_branch <= 1;
521
              id_ex_jump <= 0;
522
              id_ex_jr <= 0;
523
              id_ex_linked <= 0;
524
              id_ex_mult <= 0;
525
              id_ex_div <= 0;
526
              id_ex_load <= 0;
527
              id_ex_store <= 0;
528
              id_ex_size <= 0;
529
              id_ex_store_value <= 0;
530
              id_ex_destreg <= 0;
531
              id_ex_desthi <= 0;
532
              id_ex_destlo <= 0;
533
            end
534
          `OPCODE_BLEZ:
535
            begin
536
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BLEZ r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
537
              id_ex_alu_a <= GPR[if_id_rs];
538
              id_ex_alu_b <= 0;
539
              id_ex_alu_func <= `ALU_OP_SLE;
540
              id_ex_alu_signed <= 0;
541
              id_ex_branch <= 1;
542
              id_ex_jump <= 0;
543
              id_ex_jr <= 0;
544
              id_ex_linked <= 0;
545
              id_ex_mult <= 0;
546
              id_ex_div <= 0;
547
              id_ex_load <= 0;
548
              id_ex_store <= 0;
549
              id_ex_size <= 0;
550
              id_ex_store_value <= 0;
551
              id_ex_destreg <= 0;
552
              id_ex_desthi <= 0;
553
              id_ex_destlo <= 0;
554
            end
555
          `OPCODE_BGTZ:
556
            begin
557
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BGTZ r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
558
              id_ex_alu_a <= GPR[if_id_rs];
559
              id_ex_alu_b <= 0;
560
              id_ex_alu_func <= `ALU_OP_SGT;
561
              id_ex_alu_signed <= 0;
562
              id_ex_branch <= 1;
563
              id_ex_jump <= 0;
564
              id_ex_jr <= 0;
565
              id_ex_linked <= 0;
566
              id_ex_mult <= 0;
567
              id_ex_div <= 0;
568
              id_ex_load <= 0;
569
              id_ex_store <= 0;
570
              id_ex_size <= 0;
571
              id_ex_store_value <= 0;
572
              id_ex_destreg <= 0;
573
              id_ex_desthi <= 0;
574
              id_ex_destlo <= 0;
575
            end
576
          `OPCODE_ADDI:
577
            begin
578
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ADDI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);
579
              id_ex_alu_a <= GPR[if_id_rs];
580
              id_ex_alu_b <= if_id_imm_signext;
581
              id_ex_alu_func <= `ALU_OP_ADD;
582
              id_ex_alu_signed <= 1;
583
              id_ex_branch <= 0;
584
              id_ex_jump <= 0;
585
              id_ex_jr <= 0;
586
              id_ex_linked <= 0;
587
              id_ex_mult <= 0;
588
              id_ex_div <= 0;
589
              id_ex_load <= 0;
590
              id_ex_store <= 0;
591
              id_ex_size <= 0;
592
              id_ex_store_value <= 0;
593
              id_ex_destreg <= if_id_rt;
594
              id_ex_desthi <= 0;
595
              id_ex_destlo <= 0;
596
            end
597
          `OPCODE_ADDIU:
598
            begin
599
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ADDIU r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);
600
              id_ex_alu_a <= GPR[if_id_rs];
601
              id_ex_alu_b <= if_id_imm_signext;
602
              id_ex_alu_func <= `ALU_OP_ADD;
603
              id_ex_alu_signed <= 0;
604
              id_ex_branch <= 0;
605
              id_ex_jump <= 0;
606
              id_ex_jr <= 0;
607
              id_ex_linked <= 0;
608
              id_ex_mult <= 0;
609
              id_ex_div <= 0;
610
              id_ex_load <= 0;
611
              id_ex_store <= 0;
612
              id_ex_size <= 0;
613
              id_ex_store_value <= 0;
614
              id_ex_destreg <= if_id_rt;
615
              id_ex_desthi <= 0;
616
              id_ex_destlo <= 0;
617
            end
618
          `OPCODE_SLTI:
619
            begin
620
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLTI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);
621
              id_ex_alu_a <= GPR[if_id_rs];
622
              id_ex_alu_b <= if_id_imm_signext;
623
              id_ex_alu_func <= `ALU_OP_SLT;
624
              id_ex_alu_signed <= 1;
625
              id_ex_branch <= 0;
626
              id_ex_jump <= 0;
627
              id_ex_jr <= 0;
628
              id_ex_linked <= 0;
629
              id_ex_mult <= 0;
630
              id_ex_div <= 0;
631
              id_ex_load <= 0;
632
              id_ex_store <= 0;
633
              id_ex_size <= 0;
634
              id_ex_store_value <= 0;
635
              id_ex_destreg <= if_id_rt;
636
              id_ex_desthi <= 0;
637
              id_ex_destlo <= 0;
638
            end
639
          `OPCODE_SLTIU:
640
            begin
641
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLTIU r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_signext);
642
              id_ex_alu_a <= GPR[if_id_rs];
643
              id_ex_alu_b <= if_id_imm_signext;
644
              id_ex_alu_func <= `ALU_OP_SLT;
645
              id_ex_alu_signed <= 0;
646
              id_ex_branch <= 0;
647
              id_ex_jump <= 0;
648
              id_ex_jr <= 0;
649
              id_ex_linked <= 0;
650
              id_ex_mult <= 0;
651
              id_ex_div <= 0;
652
              id_ex_load <= 0;
653
              id_ex_store <= 0;
654
              id_ex_size <= 0;
655
              id_ex_store_value <= 0;
656
              id_ex_destreg <= if_id_rt;
657
              id_ex_desthi <= 0;
658
              id_ex_destlo <= 0;
659
            end
660
          `OPCODE_ANDI:
661
            begin
662
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ANDI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_zeroext);
663
              id_ex_alu_a <= GPR[if_id_rs];
664
              id_ex_alu_b <= if_id_imm_zeroext;
665
              id_ex_alu_func <= `ALU_OP_AND;
666
              id_ex_alu_signed <= 0;
667
              id_ex_branch <= 0;
668
              id_ex_jump <= 0;
669
              id_ex_jr <= 0;
670
              id_ex_linked <= 0;
671
              id_ex_mult <= 0;
672
              id_ex_div <= 0;
673
              id_ex_load <= 0;
674
              id_ex_store <= 0;
675
              id_ex_size <= 0;
676
              id_ex_store_value <= 0;
677
              id_ex_destreg <= if_id_rt;
678
              id_ex_desthi <= 0;
679
              id_ex_destlo <= 0;
680
            end
681
          `OPCODE_ORI:
682
            begin
683
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ORI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_zeroext);
684
              id_ex_alu_a <= GPR[if_id_rs];
685
              id_ex_alu_b <= if_id_imm_zeroext;
686
              id_ex_alu_func <= `ALU_OP_OR;
687
              id_ex_alu_signed <= 0;
688
              id_ex_branch <= 0;
689
              id_ex_jump <= 0;
690
              id_ex_jr <= 0;
691
              id_ex_linked <= 0;
692
              id_ex_mult <= 0;
693
              id_ex_div <= 0;
694
              id_ex_load <= 0;
695
              id_ex_store <= 0;
696
              id_ex_size <= 0;
697
              id_ex_store_value <= 0;
698
              id_ex_destreg <= if_id_rt;
699
              id_ex_desthi <= 0;
700
              id_ex_destlo <= 0;
701
            end
702
          `OPCODE_XORI:
703
            begin
704
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as XORI r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_rs, if_id_imm_zeroext);
705
              id_ex_alu_a <= GPR[if_id_rs];
706
              id_ex_alu_b <= if_id_imm_zeroext;
707
              id_ex_alu_func <= `ALU_OP_XOR;
708
              id_ex_alu_signed <= 0;
709
              id_ex_branch <= 0;
710
              id_ex_jump <= 0;
711
              id_ex_jr <= 0;
712
              id_ex_linked <= 0;
713
              id_ex_mult <= 0;
714
              id_ex_div <= 0;
715
              id_ex_load <= 0;
716
              id_ex_store <= 0;
717
              id_ex_size <= 0;
718
              id_ex_store_value <= 0;
719
              id_ex_destreg <= if_id_rt;
720
              id_ex_desthi <= 0;
721
              id_ex_destlo <= 0;
722
            end
723
          `OPCODE_LUI:
724
            begin
725
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LUI r%d, %h", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_zeroext);
726
              id_ex_alu_a <= if_id_imm_zeroext;
727
              id_ex_alu_b <= 16;
728
              id_ex_alu_func <= `ALU_OP_SLL;
729
              id_ex_alu_signed <= 0;
730
              id_ex_branch <= 0;
731
              id_ex_jump <= 0;
732
              id_ex_jr <= 0;
733
              id_ex_linked <= 0;
734
              id_ex_mult <= 0;
735
              id_ex_div <= 0;
736
              id_ex_load <= 0;
737
              id_ex_store <= 0;
738
              id_ex_size <= 0;
739
              id_ex_store_value <= 0;
740
              id_ex_destreg <= if_id_rt;
741
              id_ex_desthi <= 0;
742
              id_ex_destlo <= 0;
743
            end
744
          `OPCODE_COP0:
745
            begin
746
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as COP0", if_id_addr, if_id_opcode);
747
            end
748
          `OPCODE_COP1:
749
            begin
750
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as COP1", if_id_addr, if_id_opcode);
751
            end
752
          `OPCODE_COP2:
753
            begin
754
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as COP2", if_id_addr, if_id_opcode);
755
            end
756
          `OPCODE_COP3:
757
            begin
758
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as COP3", if_id_addr, if_id_opcode);
759
            end
760
          `OPCODE_LB:
761
            begin
762
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LB r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
763
              id_ex_alu_a <= GPR[if_id_rs];
764
              id_ex_alu_b <= if_id_imm_signext;
765
              id_ex_alu_func <= `ALU_OP_ADD;
766
              id_ex_alu_signed <= 1;
767
              id_ex_branch <= 0;
768
              id_ex_jump <= 0;
769
              id_ex_jr <= 0;
770
              id_ex_linked <= 0;
771
              id_ex_mult <= 0;
772
              id_ex_div <= 0;
773
              id_ex_load <= 1;
774
              id_ex_store <= 0;
775
              id_ex_size <= `SIZE_BYTE;
776
              id_ex_store_value <= 0;
777
              id_ex_destreg <= if_id_rt;
778
              id_ex_desthi <= 0;
779
              id_ex_destlo <= 0;
780
            end
781
          `OPCODE_LH:
782
            begin
783
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LH r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
784
              id_ex_alu_a <= GPR[if_id_rs];
785
              id_ex_alu_b <= if_id_imm_signext;
786
              id_ex_alu_func <= `ALU_OP_ADD;
787
              id_ex_alu_signed <= 1;
788
              id_ex_branch <= 0;
789
              id_ex_jump <= 0;
790
              id_ex_jr <= 0;
791
              id_ex_linked <= 0;
792
              id_ex_mult <= 0;
793
              id_ex_div <= 0;
794
              id_ex_load <= 1;
795
              id_ex_store <= 0;
796
              id_ex_size <= `SIZE_HALF;
797
              id_ex_store_value <= 0;
798
              id_ex_destreg <= if_id_rt;
799
              id_ex_desthi <= 0;
800
              id_ex_destlo <= 0;
801
            end
802
          `OPCODE_LWL:
803
            begin
804
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LWL r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
805
              id_ex_alu_a <= GPR[if_id_rs];
806
              id_ex_alu_b <= if_id_imm_signext;
807
              id_ex_alu_func <= `ALU_OP_ADD;
808
              id_ex_alu_signed <= 1;
809
              id_ex_branch <= 0;
810
              id_ex_jump <= 0;
811
              id_ex_jr <= 0;
812
              id_ex_linked <= 0;
813
              id_ex_mult <= 0;
814
              id_ex_div <= 0;
815
              id_ex_load <= 1;
816
              id_ex_store <= 0;
817
              id_ex_size <= `SIZE_LEFT;
818 51 fafa1971
              id_ex_store_value <= GPR[if_id_rt];
819 33 fafa1971
              id_ex_destreg <= if_id_rt;
820
              id_ex_desthi <= 0;
821
              id_ex_destlo <= 0;
822
            end
823
          `OPCODE_LW:
824
            begin
825
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LW r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
826
              id_ex_alu_a <= GPR[if_id_rs];
827
              id_ex_alu_b <= if_id_imm_signext;
828
              id_ex_alu_func <= `ALU_OP_ADD;
829
              id_ex_alu_signed <= 1;
830
              id_ex_branch <= 0;
831
              id_ex_jump <= 0;
832
              id_ex_jr <= 0;
833
              id_ex_linked <= 0;
834
              id_ex_mult <= 0;
835
              id_ex_div <= 0;
836
              id_ex_load <= 1;
837
              id_ex_store <= 0;
838
              id_ex_size <= `SIZE_WORD;
839
              id_ex_store_value <= 0;
840
              id_ex_destreg <= if_id_rt;
841
              id_ex_desthi <= 0;
842
              id_ex_destlo <= 0;
843
            end
844
          `OPCODE_LBU:
845
            begin
846
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LBU r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
847
              id_ex_alu_a <= GPR[if_id_rs];
848
              id_ex_alu_b <= if_id_imm_signext;
849
              id_ex_alu_func <= `ALU_OP_ADD;
850
              id_ex_alu_signed <= 0;
851
              id_ex_branch <= 0;
852
              id_ex_jump <= 0;
853
              id_ex_jr <= 0;
854
              id_ex_linked <= 0;
855
              id_ex_mult <= 0;
856
              id_ex_div <= 0;
857
              id_ex_load <= 1;
858
              id_ex_store <= 0;
859
              id_ex_size <= `SIZE_BYTE;
860
              id_ex_store_value <= 0;
861
              id_ex_destreg <= if_id_rt;
862
              id_ex_desthi <= 0;
863
              id_ex_destlo <= 0;
864
            end
865
          `OPCODE_LHU:
866
            begin
867
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LHU r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
868
              id_ex_alu_a <= GPR[if_id_rs];
869
              id_ex_alu_b <= if_id_imm_signext;
870
              id_ex_alu_func <= `ALU_OP_ADD;
871
              id_ex_alu_signed <= 0;
872
              id_ex_branch <= 0;
873
              id_ex_jump <= 0;
874
              id_ex_jr <= 0;
875
              id_ex_linked <= 0;
876
              id_ex_mult <= 0;
877
              id_ex_div <= 0;
878
              id_ex_load <= 1;
879
              id_ex_store <= 0;
880
              id_ex_size <= `SIZE_HALF;
881
              id_ex_store_value <= 0;
882
              id_ex_destreg <= if_id_rt;
883
              id_ex_desthi <= 0;
884
              id_ex_destlo <= 0;
885
            end
886
          `OPCODE_LWR:
887
            begin
888
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LWR r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
889
              id_ex_alu_a <= GPR[if_id_rs];
890
              id_ex_alu_b <= if_id_imm_signext;
891
              id_ex_alu_func <= `ALU_OP_ADD;
892
              id_ex_alu_signed <= 1;
893
              id_ex_branch <= 0;
894
              id_ex_jump <= 0;
895
              id_ex_jr <= 0;
896
              id_ex_linked <= 0;
897
              id_ex_mult <= 0;
898
              id_ex_div <= 0;
899
              id_ex_load <= 1;
900
              id_ex_store <= 0;
901
              id_ex_size <= `SIZE_RIGHT;
902 51 fafa1971
              id_ex_store_value <= GPR[if_id_rt];
903 33 fafa1971
              id_ex_destreg <= if_id_rt;
904
              id_ex_desthi <= 0;
905
              id_ex_destlo <= 0;
906
            end
907
          `OPCODE_SB:
908
            begin
909
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SB r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
910
              id_ex_alu_a <= GPR[if_id_rs];
911
              id_ex_alu_b <= if_id_imm_signext;
912
              id_ex_alu_func <= `ALU_OP_ADD;
913
              id_ex_alu_signed <= 1;
914
              id_ex_branch <= 0;
915
              id_ex_jump <= 0;
916
              id_ex_jr <= 0;
917
              id_ex_linked <= 0;
918
              id_ex_mult <= 0;
919
              id_ex_div <= 0;
920
              id_ex_load <= 0;
921
              id_ex_store <= 1;
922
              id_ex_size <= `SIZE_BYTE;
923
              id_ex_store_value <= GPR[if_id_rt];
924
              id_ex_destreg <= 0;
925
              id_ex_desthi <= 0;
926
              id_ex_destlo <= 0;
927
            end
928
          `OPCODE_SH:
929
            begin
930
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SH r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
931
              id_ex_alu_a <= GPR[if_id_rs];
932
              id_ex_alu_b <= if_id_imm_signext;
933
              id_ex_alu_func <= `ALU_OP_ADD;
934
              id_ex_alu_signed <= 1;
935
              id_ex_branch <= 0;
936
              id_ex_jump <= 0;
937
              id_ex_jr <= 0;
938
              id_ex_linked <= 0;
939
              id_ex_mult <= 0;
940
              id_ex_div <= 0;
941
              id_ex_load <= 0;
942
              id_ex_store <= 1;
943
              id_ex_size <= `SIZE_HALF;
944
              id_ex_store_value <= GPR[if_id_rt];
945
              id_ex_destreg <= 0;
946
              id_ex_desthi <= 0;
947
              id_ex_destlo <= 0;
948
             end
949
          `OPCODE_SWL:
950
            begin
951
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SWL r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
952
              id_ex_alu_a <= GPR[if_id_rs];
953
              id_ex_alu_b <= if_id_imm_signext;
954
              id_ex_alu_func <= `ALU_OP_ADD;
955
              id_ex_alu_signed <= 1;
956
              id_ex_branch <= 0;
957
              id_ex_jump <= 0;
958
              id_ex_jr <= 0;
959
              id_ex_linked <= 0;
960
              id_ex_mult <= 0;
961
              id_ex_div <= 0;
962
              id_ex_load <= 0;
963
              id_ex_store <= 1;
964
              id_ex_size <= `SIZE_LEFT;
965
              id_ex_store_value <= GPR[if_id_rt];
966
              id_ex_destreg <= 0;
967
              id_ex_desthi <= 0;
968
              id_ex_destlo <= 0;
969
            end
970
          `OPCODE_SW:
971
            begin
972
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SW r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
973
              id_ex_alu_a <= GPR[if_id_rs];
974
              id_ex_alu_b <= if_id_imm_signext;
975
              id_ex_alu_func <= `ALU_OP_ADD;
976
              id_ex_alu_signed <= 1;
977
              id_ex_branch <= 0;
978
              id_ex_jump <= 0;
979
              id_ex_jr <= 0;
980
              id_ex_linked <= 0;
981
              id_ex_mult <= 0;
982
              id_ex_div <= 0;
983
              id_ex_load <= 0;
984
              id_ex_store <= 1;
985
              id_ex_size <= `SIZE_WORD;
986
              id_ex_store_value <= GPR[if_id_rt];
987
              id_ex_destreg <= 0;
988
              id_ex_desthi <= 0;
989
              id_ex_destlo <= 0;
990
            end
991
          `OPCODE_SWR:
992
            begin
993
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SWR r%d, %d(r%d)", if_id_addr, if_id_opcode, if_id_rt, if_id_imm_signext, if_id_rs);
994
              id_ex_alu_a <= GPR[if_id_rs];
995
              id_ex_alu_b <= if_id_imm_signext;
996
              id_ex_alu_func <= `ALU_OP_ADD;
997
              id_ex_alu_signed <= 1;
998
              id_ex_branch <= 0;
999
              id_ex_jump <= 0;
1000
              id_ex_jr <= 0;
1001
              id_ex_linked <= 0;
1002
              id_ex_mult <= 0;
1003
              id_ex_div <= 0;
1004
              id_ex_load <= 0;
1005
              id_ex_store <= 1;
1006
              id_ex_size <= `SIZE_RIGHT;
1007
              id_ex_store_value <= GPR[if_id_rt];
1008
              id_ex_destreg <= 0;
1009
              id_ex_desthi <= 0;
1010
              id_ex_destlo <= 0;
1011
            end
1012
          `OPCODE_LWC1:
1013
            begin
1014
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LWC1", if_id_addr, if_id_opcode);
1015
           end
1016
          `OPCODE_LWC2:
1017
            begin
1018
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LWC2", if_id_addr, if_id_opcode);
1019
            end
1020
          `OPCODE_LWC3:
1021
            begin
1022
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as LWC3", if_id_addr, if_id_opcode);
1023
            end
1024
          `OPCODE_SWC1:
1025
            begin
1026
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SWC1", if_id_addr, if_id_opcode);
1027
            end
1028
          `OPCODE_SWC2:
1029
            begin
1030
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SWC2", if_id_addr, if_id_opcode);
1031
            end
1032
          `OPCODE_SWC3:
1033
            begin
1034
              $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SWC3", if_id_addr, if_id_opcode);
1035
            end
1036
          `OPCODE_SPECIAL:
1037
            case(if_id_func)
1038
              `FUNCTION_SLL:
1039
                begin
1040
                  if(if_id_opcode==`NOP) $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as NOP", if_id_addr, if_id_opcode);
1041
                  else $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLL r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_shamt);
1042
                  id_ex_alu_a <= GPR[if_id_rt];
1043
                  id_ex_alu_b <= if_id_shamt;
1044
                  id_ex_alu_func <= `ALU_OP_SLL;
1045
                  id_ex_alu_signed <= 0;
1046
                  id_ex_branch <= 0;
1047
                  id_ex_jump <= 0;
1048
                  id_ex_jr <= 0;
1049
                  id_ex_linked <= 0;
1050
                  id_ex_mult <= 0;
1051
                  id_ex_div <= 0;
1052
                  id_ex_load <= 0;
1053
                  id_ex_store <= 0;
1054
                  id_ex_size <= 0;
1055
                  id_ex_store_value <= 0;
1056
                  id_ex_destreg <= if_id_rd;
1057
                  id_ex_desthi <= 0;
1058
                  id_ex_destlo <= 0;
1059
                end
1060
              `FUNCTION_SRL:
1061
                begin
1062
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SRL r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_shamt);
1063
                  id_ex_alu_a <= GPR[if_id_rt];
1064
                  id_ex_alu_b <= if_id_shamt;
1065
                  id_ex_alu_func <= `ALU_OP_SRL;
1066
                  id_ex_alu_signed <= 0;
1067
                  id_ex_branch <= 0;
1068
                  id_ex_jump <= 0;
1069
                  id_ex_jr <= 0;
1070
                  id_ex_linked <= 0;
1071
                  id_ex_mult <= 0;
1072
                  id_ex_div <= 0;
1073
                  id_ex_load <= 0;
1074
                  id_ex_store <= 0;
1075
                  id_ex_size <= 0;
1076
                  id_ex_store_value <= 0;
1077
                  id_ex_destreg <= if_id_rd;
1078
                  id_ex_desthi <= 0;
1079
                  id_ex_destlo <= 0;
1080
                end
1081
              `FUNCTION_SRA:
1082
                begin
1083
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SRA r%d, r%d, %h", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_shamt);
1084
                  id_ex_alu_a <= GPR[if_id_rt];
1085
                  id_ex_alu_b <= if_id_shamt;
1086
                  id_ex_alu_func <= `ALU_OP_SRA;
1087 49 fafa1971
                  id_ex_alu_signed <= 1;
1088 33 fafa1971
                  id_ex_branch <= 0;
1089
                  id_ex_jump <= 0;
1090
                  id_ex_jr <= 0;
1091
                  id_ex_linked <= 0;
1092
                  id_ex_mult <= 0;
1093
                  id_ex_div <= 0;
1094
                  id_ex_load <= 0;
1095
                  id_ex_store <= 0;
1096
                  id_ex_size <= 0;
1097
                  id_ex_store_value <= 0;
1098
                  id_ex_destreg <= if_id_rd;
1099
                  id_ex_desthi <= 0;
1100
                  id_ex_destlo <= 0;
1101
                end
1102
              `FUNCTION_SLLV:
1103
                begin
1104
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLLV r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_rs);
1105
                  id_ex_alu_a <= GPR[if_id_rt];
1106
                  id_ex_alu_b <= GPR[if_id_rs];
1107
                  id_ex_alu_func <= `ALU_OP_SLL;
1108
                  id_ex_alu_signed <= 0;
1109
                  id_ex_branch <= 0;
1110
                  id_ex_jump <= 0;
1111
                  id_ex_jr <= 0;
1112
                  id_ex_linked <= 0;
1113
                  id_ex_mult <= 0;
1114
                  id_ex_div <= 0;
1115
                  id_ex_load <= 0;
1116
                  id_ex_store <= 0;
1117
                  id_ex_size <= 0;
1118
                  id_ex_store_value <= 0;
1119
                  id_ex_destreg <= if_id_rd;
1120
                  id_ex_desthi <= 0;
1121
                  id_ex_destlo <= 0;
1122
                end
1123
              `FUNCTION_SRLV:
1124
                begin
1125
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SRLV r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_rs);
1126
                  id_ex_alu_a <= GPR[if_id_rt];
1127
                  id_ex_alu_b <= GPR[if_id_rs];
1128
                  id_ex_alu_func <= `ALU_OP_SRL;
1129
                  id_ex_alu_signed <= 0;
1130
                  id_ex_branch <= 0;
1131
                  id_ex_jump <= 0;
1132
                  id_ex_jr <= 0;
1133
                  id_ex_linked <= 0;
1134
                  id_ex_mult <= 0;
1135
                  id_ex_div <= 0;
1136
                  id_ex_load <= 0;
1137
                  id_ex_store <= 0;
1138
                  id_ex_size <= 0;
1139
                  id_ex_store_value <= 0;
1140
                  id_ex_destreg <= if_id_rd;
1141
                  id_ex_desthi <= 0;
1142
                  id_ex_destlo <= 0;
1143
                end
1144
              `FUNCTION_SRAV:
1145
                begin
1146
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SRAV r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rt, if_id_rs);
1147
                  id_ex_alu_a <= GPR[if_id_rt];
1148
                  id_ex_alu_b <= GPR[if_id_rs];
1149
                  id_ex_alu_func <= `ALU_OP_SRA;
1150
                  id_ex_alu_signed <= 1;
1151
                  id_ex_branch <= 0;
1152
                  id_ex_jump <= 0;
1153
                  id_ex_jr <= 0;
1154
                  id_ex_linked <= 0;
1155
                  id_ex_mult <= 0;
1156
                  id_ex_div <= 0;
1157
                  id_ex_load <= 0;
1158
                  id_ex_store <= 0;
1159
                  id_ex_size <= 0;
1160
                  id_ex_store_value <= 0;
1161
                  id_ex_destreg <= if_id_rd;
1162
                  id_ex_desthi <= 0;
1163
                  id_ex_destlo <= 0;
1164
                end
1165
              `FUNCTION_JR:
1166
                begin
1167
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as JR r%d", if_id_addr, if_id_opcode, if_id_rs);
1168
                  id_ex_alu_a <= 0;
1169
                  id_ex_alu_b <= 0;
1170
                  id_ex_alu_func <= `ALU_OP_ADD;
1171
                  id_ex_alu_signed <= 0;
1172
                  id_ex_branch <= 0;
1173
                  id_ex_jump <= 0;
1174
                  id_ex_jr <= 1;
1175
                  id_ex_linked <= 0;
1176
                  id_ex_mult <= 0;
1177
                  id_ex_div <= 0;
1178
                  id_ex_load <= 0;
1179
                  id_ex_store <= 0;
1180
                  id_ex_size <= 0;
1181
                  id_ex_store_value <= 0;
1182
                  id_ex_destreg <= 0;
1183
                  id_ex_desthi <= 0;
1184
                  id_ex_destlo <= 0;
1185
                end
1186
              `FUNCTION_JALR:
1187
                begin
1188
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as JALR [r%d,] r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs);
1189
                  id_ex_alu_a <= if_id_addrnext;
1190
                  id_ex_alu_b <= 4;
1191
                  id_ex_alu_func <= `ALU_OP_ADD;
1192
                  id_ex_alu_signed <= 0;
1193
                  id_ex_branch <= 0;
1194
                  id_ex_jump <= 0;
1195
                  id_ex_jr <= 1;
1196
                  id_ex_linked <= 1;
1197
                  id_ex_mult <= 0;
1198
                  id_ex_div <= 0;
1199
                  id_ex_load <= 0;
1200
                  id_ex_store <= 0;
1201
                  id_ex_size <= 0;
1202
                  id_ex_store_value <= 0;
1203
                  id_ex_destreg <= if_id_rd;
1204
                  id_ex_desthi <= 0;
1205
                  id_ex_destlo <= 0;
1206
                end
1207
              `FUNCTION_SYSCALL:
1208
                begin
1209
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SYSCALL", if_id_addr, if_id_opcode);
1210
//                  id_ex_alu_a <= 0;
1211
//                  id_ex_alu_b <= 0;
1212
//                  id_ex_alu_func <= `ALU_OP_ADD;
1213
//                  id_ex_alu_signed <= 0;
1214
//                  id_ex_branch <= 0;
1215
//                  id_ex_jump <= 0;
1216
//                  id_ex_jr <= 0;
1217
//                  id_ex_linked <= 0;
1218
//                  id_ex_mult <= 0;
1219
//                  id_ex_div <= 0;
1220
//                  id_ex_load <= 0;
1221
//                  id_ex_store <= 0;
1222
//                  id_ex_size <= 0;
1223
//                  id_ex_store_value <= 0;
1224
//                  id_ex_destreg <= 0;
1225
//                  id_ex_desthi <= 0;
1226
//                  id_ex_destlo <= 0;
1227
                end
1228
              `FUNCTION_BREAK:
1229
                begin
1230
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BREAK", if_id_addr, if_id_opcode);
1231
//                  id_ex_alu_a <= 0;
1232
//                  id_ex_alu_b <= 0;
1233
//                  id_ex_alu_func <= `ALU_OP_ADD;
1234
//                  id_ex_alu_signed <= 0;
1235
//                  id_ex_branch <= 0;
1236
//                  id_ex_jump <= 0;
1237
//                  id_ex_jr <= 0;
1238
//                  id_ex_linked <= 0;
1239
//                  id_ex_mult <= 0;
1240
//                  id_ex_div <= 0;
1241
//                  id_ex_load <= 0;
1242
//                  id_ex_store <= 0;
1243
//                  id_ex_size <= 0;
1244
//                  id_ex_store_value <= 0;
1245
//                  id_ex_destreg <= 0;
1246
//                  id_ex_desthi <= 0;
1247
//                  id_ex_destlo <= 0;
1248
                end
1249
              `FUNCTION_MFHI:
1250
                begin
1251
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MFHI r%d", if_id_addr, if_id_opcode, if_id_rd);
1252
                  id_ex_alu_a <= HI;
1253
                  id_ex_alu_b <= 0;
1254
                  id_ex_alu_func <= `ALU_OP_ADD;
1255
                  id_ex_alu_signed <= 0;
1256
                  id_ex_branch <= 0;
1257
                  id_ex_jump <= 0;
1258
                  id_ex_jr <= 0;
1259
                  id_ex_linked <= 0;
1260
                  id_ex_mult <= 0;
1261
                  id_ex_div <= 0;
1262
                  id_ex_load <= 0;
1263
                  id_ex_store <= 0;
1264
                  id_ex_size <= 0;
1265
                  id_ex_store_value <= 0;
1266
                  id_ex_destreg <= if_id_rd;
1267
                  id_ex_desthi <= 0;
1268
                  id_ex_destlo <= 0;
1269
                end
1270
              `FUNCTION_MTHI:
1271
                begin
1272
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MTHI r%d", if_id_addr, if_id_opcode, if_id_rs);
1273
                  id_ex_alu_a <= GPR[if_id_rs];
1274
                  id_ex_alu_b <= 0;
1275
                  id_ex_alu_func <= `ALU_OP_ADD;
1276
                  id_ex_alu_signed <= 0;
1277
                  id_ex_branch <= 0;
1278
                  id_ex_jump <= 0;
1279
                  id_ex_jr <= 0;
1280
                  id_ex_linked <= 0;
1281
                  id_ex_mult <= 0;
1282
                  id_ex_div <= 0;
1283
                  id_ex_load <= 0;
1284
                  id_ex_store <= 0;
1285
                  id_ex_size <= 0;
1286
                  id_ex_store_value <= 0;
1287
                  id_ex_destreg <= 0;
1288
                  id_ex_desthi <= 1;
1289
                  id_ex_destlo <= 0;
1290
                end
1291
              `FUNCTION_MFLO:
1292
                begin
1293
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MFLO r%d", if_id_addr, if_id_opcode, if_id_rd);
1294
                  id_ex_alu_a <= LO;
1295
                  id_ex_alu_b <= 0;
1296
                  id_ex_alu_func <= `ALU_OP_ADD;
1297
                  id_ex_alu_signed <= 0;
1298
                  id_ex_branch <= 0;
1299
                  id_ex_jump <= 0;
1300
                  id_ex_jr <= 0;
1301
                  id_ex_linked <= 0;
1302
                  id_ex_mult <= 0;
1303
                  id_ex_div <= 0;
1304
                  id_ex_load <= 0;
1305
                  id_ex_store <= 0;
1306
                  id_ex_size <= 0;
1307
                  id_ex_store_value <= 0;
1308
                  id_ex_destreg <= if_id_rd;
1309
                  id_ex_desthi <= 0;
1310
                  id_ex_destlo <= 0;
1311
                end
1312
              `FUNCTION_MTLO:
1313
                begin
1314
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MTLO r%d", if_id_addr, if_id_opcode, if_id_rs);
1315
                  id_ex_alu_a <= GPR[if_id_rs];
1316
                  id_ex_alu_b <= 0;
1317
                  id_ex_alu_func <= `ALU_OP_ADD;
1318
                  id_ex_alu_signed <= 0;
1319
                  id_ex_branch <= 0;
1320
                  id_ex_jump <= 0;
1321
                  id_ex_linked <= 0;
1322
                  id_ex_mult <= 0;
1323
                  id_ex_div <= 0;
1324
                  id_ex_load <= 0;
1325
                  id_ex_store <= 0;
1326
                  id_ex_size <= 0;
1327
                  id_ex_store_value <= 0;
1328
                  id_ex_destreg <= 0;
1329
                  id_ex_desthi <= 0;
1330
                  id_ex_destlo <= 1;
1331
                end
1332
              `FUNCTION_MULT:
1333
                begin
1334
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MULT r%d, r%d", if_id_addr, if_id_opcode, if_id_rs, if_id_rt);
1335
                  id_ex_alu_a <= GPR[if_id_rs];
1336
                  id_ex_alu_b <= GPR[if_id_rt];
1337
                  id_ex_alu_func <= `ALU_OP_MULT;
1338
                  id_ex_alu_signed <= 1;
1339
                  id_ex_branch <= 0;
1340
                  id_ex_jump <= 0;
1341
                  id_ex_jr <= 0;
1342
                  id_ex_linked <= 0;
1343
                  id_ex_mult <= 1;
1344
                  id_ex_div <= 0;
1345
                  id_ex_load <= 0;
1346
                  id_ex_store <= 0;
1347
                  id_ex_size <= 0;
1348
                  id_ex_store_value <= 0;
1349
                  id_ex_destreg <= 0;
1350
                  id_ex_desthi <= 1;
1351
                  id_ex_destlo <= 1;
1352
                  mul_req_o <= !mul_req_o;  // Toggle the ABP request
1353
                end
1354
              `FUNCTION_MULTU:
1355
                begin
1356
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as MULTU r%d, r%d", if_id_addr, if_id_opcode, if_id_rs, if_id_rt);
1357
                  id_ex_alu_a <= GPR[if_id_rs];
1358
                  id_ex_alu_b <= GPR[if_id_rt];
1359
                  id_ex_alu_func <= `ALU_OP_MULT;
1360
                  id_ex_alu_signed <= 0;
1361
                  id_ex_branch <= 0;
1362
                  id_ex_jump <= 0;
1363
                  id_ex_jr <= 0;
1364
                  id_ex_linked <= 0;
1365
                  id_ex_mult <= 1;
1366
                  id_ex_div <= 0;
1367
                  id_ex_load <= 0;
1368
                  id_ex_store <= 0;
1369
                  id_ex_size <= 0;
1370
                  id_ex_store_value <= 0;
1371
                  id_ex_destreg <= 0;
1372
                  id_ex_desthi <= 1;
1373
                  id_ex_destlo <= 1;
1374
                  mul_req_o <= !mul_req_o;  // Toggle the ABP request
1375
                end
1376
              `FUNCTION_DIV:
1377
                begin
1378
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as DIV r%d, r%d", if_id_addr, if_id_opcode, if_id_rs, if_id_rt);
1379
                  id_ex_alu_a <= GPR[if_id_rs];
1380
                  id_ex_alu_b <= GPR[if_id_rt];
1381
                  id_ex_alu_func <= `ALU_OP_DIV;
1382
                  id_ex_alu_signed <= 1;
1383
                  id_ex_branch <= 0;
1384
                  id_ex_jump <= 0;
1385
                  id_ex_jr <= 0;
1386
                  id_ex_linked <= 0;
1387
                  id_ex_mult <= 0;
1388
                  id_ex_div <= 1;
1389
                  id_ex_load <= 0;
1390
                  id_ex_store <= 0;
1391
                  id_ex_size <= 0;
1392
                  id_ex_store_value <= 0;
1393
                  id_ex_destreg <= 0;
1394
                  id_ex_desthi <= 1;
1395
                  id_ex_destlo <= 1;
1396
                  div_req_o <= !div_req_o;  // Toggle the ABP request
1397
                end
1398
              `FUNCTION_DIVU:
1399
                begin
1400
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as DIVU r%d, r%d", if_id_addr, if_id_opcode, if_id_rs, if_id_rt);
1401
                  id_ex_alu_a <= GPR[if_id_rs];
1402
                  id_ex_alu_b <= GPR[if_id_rt];
1403
                  id_ex_alu_func <= `ALU_OP_DIV;
1404
                  id_ex_alu_signed <= 0;
1405
                  id_ex_branch <= 0;
1406
                  id_ex_jump <= 0;
1407
                  id_ex_jr <= 0;
1408
                  id_ex_linked <= 0;
1409
                  id_ex_mult <= 0;
1410
                  id_ex_div <= 1;
1411
                  id_ex_load <= 0;
1412
                  id_ex_store <= 0;
1413
                  id_ex_size <= 0;
1414
                  id_ex_store_value <= 0;
1415
                  id_ex_destreg <= 0;
1416
                  id_ex_desthi <= 1;
1417
                  id_ex_destlo <= 1;
1418
                  div_req_o <= !div_req_o;  // Toggle the ABP request
1419
                end
1420
              `FUNCTION_ADD:
1421
                begin
1422
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ADD r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
1423
                  id_ex_alu_a <= GPR[if_id_rs];
1424
                  id_ex_alu_b <= GPR[if_id_rt];
1425
                  id_ex_alu_func <= `ALU_OP_ADD;
1426
                  id_ex_alu_signed <= 1;
1427
                  id_ex_branch <= 0;
1428
                  id_ex_jump <= 0;
1429
                  id_ex_jr <= 0;
1430
                  id_ex_linked <= 0;
1431
                  id_ex_mult <= 0;
1432
                  id_ex_div <= 0;
1433
                  id_ex_load <= 0;
1434
                  id_ex_store <= 0;
1435
                  id_ex_size <= 0;
1436
                  id_ex_store_value <= 0;
1437
                  id_ex_destreg <= if_id_rd;
1438
                  id_ex_desthi <= 0;
1439
                  id_ex_destlo <= 0;
1440
                end
1441
              `FUNCTION_ADDU:
1442
                begin
1443
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as ADDU r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
1444
                  id_ex_alu_a <= GPR[if_id_rs];
1445
                  id_ex_alu_b <= GPR[if_id_rt];
1446
                  id_ex_alu_func <= `ALU_OP_ADD;
1447
                  id_ex_alu_signed <= 0;
1448
                  id_ex_branch <= 0;
1449
                  id_ex_jump <= 0;
1450
                  id_ex_jr <= 0;
1451
                  id_ex_linked <= 0;
1452
                  id_ex_mult <= 0;
1453
                  id_ex_div <= 0;
1454
                  id_ex_load <= 0;
1455
                  id_ex_store <= 0;
1456
                  id_ex_size <= 0;
1457
                  id_ex_store_value <= 0;
1458
                  id_ex_destreg <= if_id_rd;
1459
                  id_ex_desthi <= 0;
1460
                  id_ex_destlo <= 0;
1461
                end
1462
              `FUNCTION_SUB:
1463
                begin
1464
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SUB r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
1465
                  id_ex_alu_a <= GPR[if_id_rs];
1466
                  id_ex_alu_b <= GPR[if_id_rt];
1467
                  id_ex_alu_func <= `ALU_OP_SUB;
1468
                  id_ex_alu_signed <= 1;
1469
                  id_ex_branch <= 0;
1470
                  id_ex_jump <= 0;
1471
                  id_ex_jr <= 0;
1472
                  id_ex_linked <= 0;
1473
                  id_ex_mult <= 0;
1474
                  id_ex_div <= 0;
1475
                  id_ex_load <= 0;
1476
                  id_ex_store <= 0;
1477
                  id_ex_size <= 0;
1478
                  id_ex_store_value <= 0;
1479
                  id_ex_destreg <= if_id_rd;
1480
                  id_ex_desthi <= 0;
1481
                  id_ex_destlo <= 0;
1482
                end
1483
              `FUNCTION_SUBU:
1484
                begin
1485
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SUBU r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
1486
                  id_ex_alu_a <= GPR[if_id_rs];
1487
                  id_ex_alu_b <= GPR[if_id_rt];
1488
                  id_ex_alu_func <= `ALU_OP_SUB;
1489
                  id_ex_alu_signed <= 0;
1490
                  id_ex_branch <= 0;
1491
                  id_ex_jump <= 0;
1492
                  id_ex_jr <= 0;
1493
                  id_ex_linked <= 0;
1494
                  id_ex_mult <= 0;
1495
                  id_ex_div <= 0;
1496
                  id_ex_load <= 0;
1497
                  id_ex_store <= 0;
1498
                  id_ex_size <= 0;
1499
                  id_ex_store_value <= 0;
1500
                  id_ex_destreg <= if_id_rd;
1501
                  id_ex_desthi <= 0;
1502
                  id_ex_destlo <= 0;
1503
                end
1504
              `FUNCTION_AND:
1505
                begin
1506
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as AND r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
1507
                  id_ex_alu_a <= GPR[if_id_rs];
1508
                  id_ex_alu_b <= GPR[if_id_rt];
1509
                  id_ex_alu_func <= `ALU_OP_AND;
1510
                  id_ex_alu_signed <= 0;
1511
                  id_ex_branch <= 0;
1512
                  id_ex_jump <= 0;
1513
                  id_ex_jr <= 0;
1514
                  id_ex_linked <= 0;
1515
                  id_ex_mult <= 0;
1516
                  id_ex_div <= 0;
1517
                  id_ex_load <= 0;
1518
                  id_ex_store <= 0;
1519
                  id_ex_size <= 0;
1520
                  id_ex_store_value <= 0;
1521
                  id_ex_destreg <= if_id_rd;
1522
                  id_ex_desthi <= 0;
1523
                  id_ex_destlo <= 0;
1524
                end
1525
              `FUNCTION_OR:
1526
                begin
1527
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as OR r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
1528
                  id_ex_alu_a <= GPR[if_id_rs];
1529
                  id_ex_alu_b <= GPR[if_id_rt];
1530
                  id_ex_alu_func <= `ALU_OP_OR;
1531
                  id_ex_alu_signed <= 0;
1532
                  id_ex_branch <= 0;
1533
                  id_ex_jump <= 0;
1534
                  id_ex_jr <= 0;
1535
                  id_ex_linked <= 0;
1536
                  id_ex_mult <= 0;
1537
                  id_ex_div <= 0;
1538
                  id_ex_load <= 0;
1539
                  id_ex_store <= 0;
1540
                  id_ex_size <= 0;
1541
                  id_ex_store_value <= 0;
1542
                  id_ex_destreg <= if_id_rd;
1543
                  id_ex_desthi <= 0;
1544
                  id_ex_destlo <= 0;
1545
                end
1546
              `FUNCTION_XOR:
1547
                begin
1548
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as XOR r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
1549
                  id_ex_alu_a <= GPR[if_id_rs];
1550
                  id_ex_alu_b <= GPR[if_id_rt];
1551
                  id_ex_alu_func <= `ALU_OP_XOR;
1552
                  id_ex_alu_signed <= 0;
1553
                  id_ex_branch <= 0;
1554
                  id_ex_jump <= 0;
1555
                  id_ex_jr <= 0;
1556
                  id_ex_linked <= 0;
1557
                  id_ex_mult <= 0;
1558
                  id_ex_div <= 0;
1559
                  id_ex_load <= 0;
1560
                  id_ex_store <= 0;
1561
                  id_ex_size <= 0;
1562
                  id_ex_store_value <= 0;
1563
                  id_ex_destreg <= if_id_rd;
1564
                  id_ex_desthi <= 0;
1565
                  id_ex_destlo <= 0;
1566
                end
1567
              `FUNCTION_NOR:
1568
                begin
1569
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as NOR r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
1570
                  id_ex_alu_a <= GPR[if_id_rs];
1571
                  id_ex_alu_b <= GPR[if_id_rt];
1572
                  id_ex_alu_func <= `ALU_OP_NOR;
1573
                  id_ex_alu_signed <= 0;
1574
                  id_ex_branch <= 0;
1575
                  id_ex_jump <= 0;
1576
                  id_ex_jr <= 0;
1577
                  id_ex_linked <= 0;
1578
                  id_ex_mult <= 0;
1579
                  id_ex_div <= 0;
1580
                  id_ex_load <= 0;
1581
                  id_ex_store <= 0;
1582
                  id_ex_size <= 0;
1583
                  id_ex_store_value <= 0;
1584
                  id_ex_destreg <= if_id_rd;
1585
                  id_ex_desthi <= 0;
1586
                  id_ex_destlo <= 0;
1587
                end
1588
              `FUNCTION_SLT:
1589
                begin
1590
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLT r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
1591
                  id_ex_alu_a <= GPR[if_id_rs];
1592
                  id_ex_alu_b <= GPR[if_id_rt];
1593
                  id_ex_alu_func <= `ALU_OP_SLT;
1594
                  id_ex_alu_signed <= 1;
1595
                  id_ex_branch <= 0;
1596
                  id_ex_jump <= 0;
1597
                  id_ex_jr <= 0;
1598
                  id_ex_linked <= 0;
1599
                  id_ex_mult <= 0;
1600
                  id_ex_div <= 0;
1601
                  id_ex_load <= 0;
1602
                  id_ex_store <= 0;
1603
                  id_ex_size <= 0;
1604
                  id_ex_store_value <= 0;
1605
                  id_ex_destreg <= if_id_rd;
1606
                  id_ex_desthi <= 0;
1607
                  id_ex_destlo <= 0;
1608
                end
1609
              `FUNCTION_SLTU:
1610
                begin
1611
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as SLTU r%d, r%d, r%d", if_id_addr, if_id_opcode, if_id_rd, if_id_rs, if_id_rt);
1612
                  id_ex_alu_a <= GPR[if_id_rs];
1613
                  id_ex_alu_b <= GPR[if_id_rt];
1614
                  id_ex_alu_func <= `ALU_OP_SLT;
1615
                  id_ex_alu_signed <= 0;
1616
                  id_ex_branch <= 0;
1617
                  id_ex_jump <= 0;
1618
                  id_ex_jr <= 0;
1619
                  id_ex_linked <= 0;
1620
                  id_ex_mult <= 0;
1621
                  id_ex_div <= 0;
1622
                  id_ex_load <= 0;
1623
                  id_ex_store <= 0;
1624
                  id_ex_size <= 0;
1625
                  id_ex_store_value <= 0;
1626
                  id_ex_destreg <= if_id_rd;
1627
                  id_ex_desthi <= 0;
1628
                  id_ex_destlo <= 0;
1629
                end
1630
            endcase
1631
          `OPCODE_BCOND:
1632
            case(if_id_rt)
1633
              `BCOND_BLTZ:
1634
                begin
1635
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BLTZ r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
1636
                  id_ex_alu_a <= GPR[if_id_rs];
1637
                  id_ex_alu_b <= 0;
1638
                  id_ex_alu_func <= `ALU_OP_SLT;
1639
                  id_ex_alu_signed <= 1;
1640
                  id_ex_branch <= 1;
1641
                  id_ex_jump <= 0;
1642
                  id_ex_jr <= 0;
1643
                  id_ex_linked <= 0;
1644
                  id_ex_mult <= 0;
1645
                  id_ex_div <= 0;
1646
                  id_ex_load <= 0;
1647
                  id_ex_store <= 0;
1648
                  id_ex_size <= 0;
1649
                  id_ex_store_value <= 0;
1650
                  id_ex_destreg <= if_id_rd;
1651
                  id_ex_desthi <= 0;
1652
                  id_ex_destlo <= 0;
1653
                end
1654
              `BCOND_BGEZ:
1655
                begin
1656
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BGEZ r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
1657
                  id_ex_alu_a <= GPR[if_id_rs];
1658
                  id_ex_alu_b <= 0;
1659
                  id_ex_alu_func <= `ALU_OP_SGE;
1660
                  id_ex_alu_signed <= 1;
1661
                  id_ex_branch <= 1;
1662
                  id_ex_jump <= 0;
1663
                  id_ex_jr <= 0;
1664
                  id_ex_linked <= 0;
1665
                  id_ex_mult <= 0;
1666
                  id_ex_div <= 0;
1667
                  id_ex_load <= 0;
1668
                  id_ex_store <= 0;
1669
                  id_ex_size <= 0;
1670
                  id_ex_store_value <= 0;
1671
                  id_ex_destreg <= if_id_rd;
1672
                  id_ex_desthi <= 0;
1673
                  id_ex_destlo <= 0;
1674
                end
1675
              `BCOND_BLTZAL:
1676
                begin
1677
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BLTZAL r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
1678
                  id_ex_alu_a <= GPR[if_id_rs];
1679
                  id_ex_alu_b <= 0;
1680
                  id_ex_alu_func <= `ALU_OP_SLT;
1681
                  id_ex_alu_signed <= 1;
1682
                  id_ex_branch <= 1;
1683
                  id_ex_jump <= 0;
1684
                  id_ex_jr <= 0;
1685
                  id_ex_linked <= 1;
1686
                  id_ex_mult <= 0;
1687
                  id_ex_div <= 0;
1688
                  id_ex_load <= 0;
1689
                  id_ex_store <= 0;
1690
                  id_ex_size <= 0;
1691
                  id_ex_store_value <= 0;
1692
                  id_ex_destreg <= 31;
1693
                  id_ex_desthi <= 0;
1694
                  id_ex_destlo <= 0;
1695
                end
1696
              `BCOND_BGEZAL:
1697
                begin
1698
                  $display("INFO: CPU(%m)-ID: Decoded instruction @ADDR=%X w/OPCODE=%X as BGEZAL r%d, %h", if_id_addr, if_id_opcode, if_id_rs, if_id_imm_signext);
1699
                  id_ex_alu_a <= GPR[if_id_rs];
1700
                  id_ex_alu_b <= 0;
1701
                  id_ex_alu_func <=`ALU_OP_SGE;
1702
                  id_ex_alu_signed <= 1;
1703
                  id_ex_branch <= 1;
1704
                  id_ex_jump <= 0;
1705
                  id_ex_jr <= 0;
1706
                  id_ex_linked <= 1;
1707
                  id_ex_mult <= 0;
1708
                  id_ex_div <= 0;
1709
                  id_ex_load <= 0;
1710
                  id_ex_store <= 0;
1711
                  id_ex_size <= 0;
1712
                  id_ex_store_value <= 0;
1713
                  id_ex_destreg <= 31;
1714
                  id_ex_desthi <= 0;
1715
                  id_ex_destlo <= 0;
1716
                end
1717
            endcase
1718
 
1719
        endcase
1720
 
1721
      end
1722
 
1723
      /*
1724
       * Pipeline Stage 3: Execute (EX)
1725
       *
1726
       * READ/WRITE:
1727
       * - read the ID/EX latch
1728
       * - write the EX/MEM latch
1729
       *
1730
       * DESCRIPTION:
1731
       * This stage takes the result from the ALU and put it in the proper latch.
1732
       * Please note that assignments to ALU inputs are done outside since they're wires.
1733
       */
1734
 
1735
      if(ex_stall) begin
1736
 
1737
        if(mem_stall) begin
1738
          $display("INFO: CPU(%m)-EX: Execution stalled and latch kept for following stalled pipeline stage");
1739
        end else begin
1740
          $display("INFO: CPU(%m)-EX: Execution stalled and bubble inserted for following running pipeline stage");
1741
          ex_mem_opcode <= `BUBBLE;
1742
          ex_mem_addr <= id_ex_addr;
1743
          ex_mem_addrnext <= 0;
1744
          ex_mem_destreg <= 0;
1745
          ex_mem_desthi <= 0;
1746
          ex_mem_destlo <= 0;
1747
        end
1748
 
1749
      end else begin
1750
 
1751
        // If not stalled propagate values to next latches
1752
        ex_mem_opcode      <= id_ex_opcode;
1753
        ex_mem_addr        <= id_ex_addr;
1754
        ex_mem_addrnext    <= id_ex_addrnext;
1755
        ex_mem_addrjump    <= id_ex_addrjump;
1756
        ex_mem_addrbranch  <= id_ex_addrbranch;
1757
        ex_mem_branch      <= id_ex_branch;
1758
        ex_mem_jump        <= id_ex_jump;
1759
        ex_mem_jr          <= id_ex_jr;
1760
        ex_mem_linked      <= id_ex_linked;
1761
        ex_mem_mult        <= id_ex_mult;
1762
        ex_mem_div         <= id_ex_div;
1763
        ex_mem_load        <= id_ex_load;
1764
        ex_mem_store       <= id_ex_store;
1765 50 fafa1971
        ex_mem_size        <= id_ex_size;
1766 51 fafa1971
        ex_mem_destold     <= id_ex_store_value;
1767 33 fafa1971
        ex_mem_destreg     <= id_ex_destreg;
1768
        ex_mem_desthi      <= id_ex_desthi;
1769
        ex_mem_destlo      <= id_ex_destlo;
1770
 
1771
        // Choose the output from ALU, Multiplier or Divider
1772 49 fafa1971
        if(id_ex_mult) begin
1773
          ex_mem_aluout <= mul_product_i;
1774 50 fafa1971
          ex_mem_carry <= 1'b0;
1775 49 fafa1971
        end else if(id_ex_div) begin
1776 50 fafa1971
          ex_mem_aluout <= { div_remainder_i, div_quotient_i };
1777
          ex_mem_carry <= 1'b0;
1778 49 fafa1971
        end else begin
1779 48 fafa1971
          ex_mem_aluout <= {32'b0, alu_result_i[31:0]};
1780
          ex_mem_carry <= alu_result_i[32];
1781
        end
1782 33 fafa1971
 
1783 50 fafa1971
        // Handle all supported store sizes
1784 33 fafa1971
        if(id_ex_store) begin
1785
          $display("INFO: CPU(%m)-EX: Execution of Store instruction @ADDR=%X w/OPCODE=%X started to STORE_ADDR=%X w/STORE_DATA=%X", id_ex_addr, id_ex_opcode, alu_result_i, id_ex_store_value);
1786
          case(id_ex_size)
1787
            `SIZE_WORD: begin
1788
              ex_mem_store_value <= id_ex_store_value;
1789
              ex_mem_store_sel <= 4'b1111;
1790
            end
1791
            `SIZE_HALF: begin
1792
              if(alu_result_i[1]==0) begin
1793 50 fafa1971
                ex_mem_store_value <= {{16'b0}, id_ex_store_value[15:0]};
1794 33 fafa1971
                ex_mem_store_sel <= 4'b0011;
1795
              end else begin
1796 50 fafa1971
                ex_mem_store_value <= {id_ex_store_value[15:0], {16'b0}};
1797 33 fafa1971
                ex_mem_store_sel <= 4'b1100;
1798
              end
1799
            end
1800
            `SIZE_BYTE: begin
1801
              case(alu_result_i[1:0])
1802
                2'b00: begin
1803 50 fafa1971
                  ex_mem_store_value <= {{24'b0}, id_ex_store_value[7:0]};
1804 33 fafa1971
                  ex_mem_store_sel <= 4'b0001;
1805
                end
1806
                2'b01: begin
1807 50 fafa1971
                  ex_mem_store_value <= {{16'b0}, id_ex_store_value[7:0],{8'b0}};
1808 33 fafa1971
                  ex_mem_store_sel <= 4'b0010;
1809
                end
1810
                2'b10: begin
1811 50 fafa1971
                  ex_mem_store_value <= {{8'b0}, id_ex_store_value[7:0],{16'b0}};
1812 33 fafa1971
                  ex_mem_store_sel <= 4'b0100;
1813
                end
1814
                2'b11: begin
1815 50 fafa1971
                  ex_mem_store_value <= {id_ex_store_value[7:0], {24'b0}};
1816 33 fafa1971
                  ex_mem_store_sel <= 4'b1000;
1817
                end
1818
              endcase
1819
            end
1820 51 fafa1971
            `SIZE_LEFT: begin
1821
              case(alu_result_i[1:0])
1822
                2'b00: begin
1823
                  ex_mem_store_value <= {24'b0, id_ex_store_value[31:24]};
1824
                  ex_mem_store_sel <= 4'b0001;
1825
                end
1826
                2'b01: begin
1827
                  ex_mem_store_value <= {16'b0, id_ex_store_value[31:16]};
1828
                  ex_mem_store_sel <= 4'b0011;
1829
                end
1830
                2'b10: begin
1831
                  ex_mem_store_value <= {8'b0, id_ex_store_value[31:8]};
1832
                  ex_mem_store_sel <= 4'b0111;
1833
                end
1834
                2'b11: begin
1835
                  ex_mem_store_value <= id_ex_store_value;
1836
                  ex_mem_store_sel <= 4'b1111;
1837
                end
1838
              endcase
1839
            end
1840
            `SIZE_RIGHT: begin
1841
              case(alu_result_i[1:0])
1842
                2'b00: begin
1843
                  ex_mem_store_value <= id_ex_store_value;
1844
                  ex_mem_store_sel <= 4'b1111;
1845
                end
1846
                2'b01: begin
1847
                  ex_mem_store_value <= {id_ex_store_value[23:0], 8'b0};
1848
                  ex_mem_store_sel <= 4'b1110;
1849
                end
1850
                2'b10: begin
1851
                  ex_mem_store_value <= {id_ex_store_value[15:0], 16'b0};
1852
                  ex_mem_store_sel <= 4'b1100;
1853
                end
1854
                2'b11: begin
1855
                  ex_mem_store_value <= {id_ex_store_value[7:0], 24'b0};
1856
                  ex_mem_store_sel <= 4'b1000;
1857
                end
1858
              endcase
1859
            end
1860 33 fafa1971
          endcase
1861
 
1862 50 fafa1971
        // Not a store
1863 33 fafa1971
        end else begin
1864
          $display("INFO: CPU(%m)-EX: Execution of instruction @ADDR=%X w/OPCODE=%X gave ALU result %X", id_ex_addr, id_ex_opcode, alu_result_i);
1865
        end
1866
 
1867
      end
1868
 
1869
      /*
1870
       * Pipeline Stage 4: Memory access (MEM)
1871
       *
1872
       * READ/WRITE:
1873
       * - read the EX/MEM latch
1874
       * - read or write memory
1875
       * - write the MEM/WB latch
1876
       *
1877
       * DESCRIPTION:
1878
       * This stage perform accesses to memory to read/write the data during
1879
       * the load/store operations.
1880
       */
1881
 
1882
      if(mem_stall) begin
1883
 
1884
        $display("INFO: CPU(%m)-MEM: Memory stalled");
1885
 
1886
      end else begin
1887
 
1888
        mem_wb_opcode     <= ex_mem_opcode;
1889
        mem_wb_addr       <= ex_mem_addr;
1890
        mem_wb_addrnext   <= ex_mem_addrnext;
1891
        mem_wb_destreg    <= ex_mem_destreg;
1892
        mem_wb_desthi     <= ex_mem_desthi;
1893
        mem_wb_destlo     <= ex_mem_destlo;
1894
 
1895 50 fafa1971
        // Handle all supported load sizes
1896 33 fafa1971
        if(ex_mem_load) begin
1897
 
1898
          $display("INFO: CPU(%m)-MEM: Loading value %X", dmem_data_i);
1899
          mem_wb_value[63:32] <= 32'b0;
1900 50 fafa1971
          case(ex_mem_size)
1901
            `SIZE_WORD: begin
1902
              mem_wb_value[31:0] <= dmem_data_i;
1903
            end
1904
            `SIZE_HALF: begin
1905
              if(ex_mem_aluout[1]==0) mem_wb_value[31:0] <= {{16{dmem_data_i[15]}}, dmem_data_i[15:0]};
1906
              else mem_wb_value[31:0] <= {{16{dmem_data_i[31]}}, dmem_data_i[31:16]};
1907
            end
1908
            `SIZE_BYTE: begin
1909
              case(ex_mem_aluout[1:0])
1910
                2'b00: mem_wb_value[31:0] <= {{24{dmem_data_i[7]}},  dmem_data_i[7:0]};
1911
                2'b01: mem_wb_value[31:0] <= {{24{dmem_data_i[15]}}, dmem_data_i[15:8]};
1912
                2'b10: mem_wb_value[31:0] <= {{24{dmem_data_i[23]}}, dmem_data_i[23:16]};
1913
                2'b11: mem_wb_value[31:0] <= {{24{dmem_data_i[31]}}, dmem_data_i[31:24]};
1914
              endcase
1915
            end
1916 51 fafa1971
            `SIZE_LEFT: begin
1917
              case(ex_mem_aluout[1:0])
1918
                2'b00: mem_wb_value[31:0] <= {dmem_data_i[7:0],  ex_mem_destold[23:0]};
1919
                2'b01: mem_wb_value[31:0] <= {dmem_data_i[15:0], ex_mem_destold[15:0]};
1920
                2'b10: mem_wb_value[31:0] <= {dmem_data_i[23:0], ex_mem_destold[7:0]};
1921
                2'b11: mem_wb_value[31:0] <= dmem_data_i;
1922
              endcase
1923
            end
1924
            `SIZE_RIGHT: begin
1925
              case(ex_mem_aluout[1:0])
1926
                2'b00: mem_wb_value[31:0] <= dmem_data_i;
1927
                2'b01: mem_wb_value[31:0] <= {ex_mem_destold[31:24], dmem_data_i[31:8]};
1928
                2'b10: mem_wb_value[31:0] <= {ex_mem_destold[31:16], dmem_data_i[31:16]};
1929
                2'b11: mem_wb_value[31:0] <= {ex_mem_destold[31:8],  dmem_data_i[31:24]};
1930
              endcase
1931
            end
1932 50 fafa1971
          endcase
1933 33 fafa1971
 
1934 50 fafa1971
        // For multiplications and divisions the result is 64-bit wide
1935 33 fafa1971
        end else if (ex_mem_desthi && ex_mem_destlo) begin
1936
 
1937
          $display("INFO: CPU(%m)-MEM: Propagating value %X", ex_mem_aluout);
1938 50 fafa1971
          mem_wb_value[63:32] <= ex_mem_aluout[63:32];
1939 33 fafa1971
          mem_wb_value[31:0] <= ex_mem_aluout[31:0];
1940
 
1941 50 fafa1971
        // For MTHI instruction we must move the value to the correct side of the bus
1942 33 fafa1971
        end else if (ex_mem_desthi) begin
1943
 
1944
          $display("INFO: CPU(%m)-MEM: Propagating value %X", ex_mem_aluout);
1945
          mem_wb_value[63:32] <= ex_mem_aluout[31:0];
1946
          mem_wb_value[31:0] <= 32'b0;
1947
 
1948 50 fafa1971
        // The default is working with 32-bit values
1949 33 fafa1971
        end else begin
1950
 
1951
          $display("INFO: CPU(%m)-MEM: Propagating value %X", ex_mem_aluout);
1952 50 fafa1971
          mem_wb_value[63:32] <= 32'b0;
1953 33 fafa1971
          mem_wb_value[31:0] <= ex_mem_aluout[31:0];
1954
 
1955
        end
1956
 
1957
      end
1958
 
1959
      /*
1960
       * Pipeline Stage 5: Write Back (WB)
1961
       *
1962
       * READ/WRITE:
1963
       * - read the MEM/WB latch
1964
       * - write the register file
1965
       *
1966
       * DESCRIPTION:
1967
       * This stage writes back the result into the proper register (GPR, HI, LO).
1968
       */
1969
 
1970
      if(wb_stall) begin
1971
 
1972
        $display("INFO: CPU(%m)-WB: Write-Back stalled");
1973
 
1974
      end else begin
1975
 
1976
        // GPRs
1977
        if(mem_wb_destreg!=0) begin
1978
          $display("INFO: CPU(%m)-WB: Writing Back GPR[%d]=%X", mem_wb_destreg, mem_wb_value[31:0]);
1979
          GPR[mem_wb_destreg] <= mem_wb_value[31:0];
1980
        end
1981
 
1982
        // HI
1983
        if(mem_wb_desthi) begin
1984
          $display("INFO: CPU(%m)-WB: Writing Back HI=%X", mem_wb_value[63:32]);
1985
          HI <= mem_wb_value[63:32];
1986
        end
1987
 
1988
        // LO
1989
        if(mem_wb_destlo) begin
1990
          $display("INFO: CPU(%m)-WB: Writing Back LO=%X", mem_wb_value[31:0]);
1991
          LO <= mem_wb_value[31:0];
1992
        end
1993
 
1994 46 fafa1971
        // SysCon
1995
        if(mem_wb_destsyscon!=0) begin
1996
          $display("INFO: CPU(%m)-WB: Writing Back SysCon[%d]=%X", mem_wb_destsyscon, mem_wb_value[31:0]);
1997
          SysCon[mem_wb_destsyscon] <= mem_wb_value[31:0];
1998
        end
1999
 
2000 33 fafa1971
        // Idle
2001
        if(mem_wb_destreg==0 & mem_wb_desthi==0 & mem_wb_destlo==0)
2002
          $display("INFO: CPU(%m)-WB: Write-Back has nothing to do");
2003
 
2004
      end
2005
 
2006
      // Display register file at each raising edge
2007
      $display("INFO: CPU(%m)-Regs: R00=%X R01=%X R02=%X R03=%X R04=%X R05=%X R06=%X R07=%X",
2008
        GPR[0], GPR[1], GPR[2], GPR[3], GPR[4], GPR[5], GPR[6], GPR[7]);
2009
      $display("INFO: CPU(%m)-Regs: R08=%X R09=%X R10=%X R11=%X R12=%X R13=%X R14=%X R15=%X",
2010
        GPR[8], GPR[9], GPR[10], GPR[11], GPR[12], GPR[13], GPR[14], GPR[15]);
2011
      $display("INFO: CPU(%m)-Regs: R16=%X R17=%X R18=%X R19=%X R20=%X R21=%X R22=%X R23=%X",
2012
        GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[23]);
2013
      $display("INFO: CPU(%m)-Regs: R24=%X R25=%X R26=%X R27=%X R28=%X R29=%X R30=%X R31=%X",
2014
        GPR[24], GPR[25], GPR[26], GPR[27], GPR[28], GPR[29], GPR[30], GPR[31]);
2015
      $display("INFO: CPU(%m)-Regs: PC=%X HI=%X LO=%X",
2016
        PC, HI, LO);
2017
 
2018
    end
2019
  end
2020
 
2021
endmodule
2022
 

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