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[/] [m1_core/] [trunk/] [hdl/] [rtl/] [m1_core/] [m1_mmu.v] - Blame information for rev 54

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/*
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 * Simply RISC M1 Memory Management Unit
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 *
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 * This block converts Harvard architecture requests to access the
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 * small internal prefetch buffer, and just in case the external
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 * Wishbone bus.
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 * Memory size is 256 word * 4 byte = 1024 byte,
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 * so 10 address bits are required => [9:0]
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 * and being the lower 2 bits unused the offset in memory is [9:2].
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 */
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module m1_mmu (
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    // System
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    input sys_clock_i,                            // System Clock
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    input sys_reset_i,                            // System Reset
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    // Instruction Memory
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    input imem_read_i,                            // I$ Read
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    input[31:0] imem_addr_i,                      // I$ Address
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    output imem_done_o,                           // I$ Done
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    output[31:0] imem_data_o,                     // I$ Data
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    // Data Memory
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    input dmem_read_i,                            // D$ Read
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    input dmem_write_i,                           // D$ Write
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    input[31:0] dmem_addr_i,                      // D$ Address
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    input[31:0] dmem_data_i,                      // D$ Write Data
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    input[3:0] dmem_sel_i,                        // D$ Byte selector
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    output dmem_done_o,                           // D$ Done
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    output[31:0] dmem_data_o,                     // D$ Read Data
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    // Wishbone Master interface
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    output wb_cyc_o,                              // Cycle Start
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    output wb_stb_o,                              // Strobe Request
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    output wb_we_o,                               // Write Enable
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    output[31:0] wb_adr_o,                        // Address Bus
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    output[31:0] wb_dat_o,                        // Data Out
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    output[3:0] wb_sel_o,                         // Byte Select
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    input wb_ack_i,                               // Ack
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    input[31:0] wb_dat_i                          // Data In
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  );
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  /*
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   * Registers
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   */
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  // Prefetch buffer
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  reg[31:0] MEM[255:0];
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  // Initialize memory content
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  initial begin
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`include "m1_mmu_initial.vh"
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  end
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  /*
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   * Wires
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   */
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  // See if there are pending requests
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  wire access_pending_imem = imem_read_i;
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  wire access_pending_dmem = 0;
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  wire access_pending_ext = (dmem_read_i || dmem_write_i);
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  // Default grant for memories
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  assign imem_done_o = access_pending_imem;
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  assign dmem_done_o = access_pending_dmem || (access_pending_ext && wb_ack_i);
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  // Set Wishbone outputs
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  assign wb_cyc_o = access_pending_ext;
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  assign wb_stb_o = access_pending_ext;
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  assign wb_we_o = access_pending_ext && dmem_write_i;
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  assign wb_sel_o = dmem_sel_i;
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  assign wb_adr_o = dmem_addr_i;
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  assign wb_dat_o = dmem_data_i;
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  // Return read data
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  assign imem_data_o = MEM[imem_addr_i[9:2]];
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  assign dmem_data_o = wb_dat_i;
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endmodule

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