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[/] [m1_core/] [trunk/] [hdl/] [rtl/] [wb_ddr_ctrl/] [dpram.v] - Blame information for rev 54

Line No.	Rev	Author	Line
1	34	fafa1971	`//----------------------------------------------------------------------------`
2			`// Wishbone DDR Controller`
3			`//`
4			`// (c) Joerg Bornschein (<jb@capsec.org>)`
5			`//----------------------------------------------------------------------------`
6
7			`module dpram`
8			`#(`
9			`parameter adr_width = 9,`
10			`parameter dat_width = 36`
11			`) (`
12			`input clk,`
13			`// Port 0`
14			`input [adr_width-1:0] adr0,`
15			`input we0,`
16			`input [dat_width-1:0] din0,`
17			`output reg [dat_width-1:0] dout0,`
18			`// Port 1`
19			`input [adr_width-1:0] adr1,`
20			`input we1,`
21			`input [dat_width-1:0] din1,`
22			`output reg [dat_width-1:0] dout1`
23			`);`
24
25			`parameter depth = (1 << adr_width);`
26
27			`// actual ram`
28			`reg [dat_width-1:0] ram [0:depth-1];`
29
30			`//------------------------------------------------------------------`
31			`// Syncronous Dual Port RAM Access`
32			`//------------------------------------------------------------------`
33			`always @(posedge clk)`
34			`begin`
35			`// Frst port`
36			`if (we0)`
37			`ram[adr0] <= din0;`
38
39			`dout0 <= ram[adr0];`
40			`end`
41
42
43			`always @(posedge clk)`
44			`begin`
45			`// Second port`
46			`if (we1)`
47			`ram[adr1] <= din1;`
48
49			`dout1 <= ram[adr1];`
50			`end`
51
52			`//------------------------------------------------------------------`
53			`// Initialize content to Zero`
54			`//------------------------------------------------------------------`
55			`integer i;`
56
57			`initial`
58			`begin`
59			`for(i=0; i<depth; i=i+1)`
60			`ram[i] <= 'b0;`
61			`end`
62
63			`endmodule`