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[/] [m1_core/] [trunk/] [hdl/] [rtl/] [wb_ddr_ctrl/] [wb_ddr.v] - Blame information for rev 54

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//----------------------------------------------------------------------------
// Wishbone DDR Controller
// 
// (c) Joerg Bornschein (<jb@capsec.org>)
//----------------------------------------------------------------------------
 
`include "ddr_include.v"
 
module wb_ddr
#(
        parameter phase_shift  = 0,
        parameter clk_multiply = 12,
        parameter clk_divide   = 5,
        parameter wait200_init = 26
) (
        input                   clk,
        input                   reset,
        // XXX -- DCM phase control -- XXX
        input  [2:0]            rot,
        //  DDR ports
        output                   ddr_clk,
        output                   ddr_clk_n,
        input                    ddr_clk_fb,
        output                   ddr_ras_n,
        output                   ddr_cas_n,
        output                   ddr_we_n,
        output                   ddr_cke,
        output                   ddr_cs_n,
        output        [  `A_RNG] ddr_a,
        output        [ `BA_RNG] ddr_ba,
        inout         [ `DQ_RNG] ddr_dq,
        inout         [`DQS_RNG] ddr_dqs,
        output        [ `DM_RNG] ddr_dm,
        // Wishbone Slave Interface
        input      [`WB_ADR_RNG] wb_adr_i,
        input      [`WB_DAT_RNG] wb_dat_i,
        output reg [`WB_DAT_RNG] wb_dat_o,
        input      [`WB_SEL_RNG] wb_sel_i,
        input                    wb_cyc_i,
        input                    wb_stb_i,
        input                    wb_we_i,
        output reg               wb_ack_o
);
 
//----------------------------------------------------------------------------
// Wishbone handling
//----------------------------------------------------------------------------
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i;
wire wb_wr = wb_stb_i & wb_cyc_i &  wb_we_i;
 
wire [`WB_WORD_RNG] wb_adr_word = wb_adr_i[`WB_WORD_RNG]; // word in bufferline
wire [`WB_SET_RNG]  wb_adr_set  = wb_adr_i[`WB_SET_RNG];  // index into wayX_ram
wire [`WB_TAG_RNG]  wb_adr_tag  = wb_adr_i[`WB_TAG_RNG];  // more significant bits
 
//----------------------------------------------------------------------------
// TAG RAM (2-way set assioziative)
//----------------------------------------------------------------------------
wire [`TAG_LINE_RNG] tag_load;
wire [`TAG_LINE_RNG] tag_store;
wire                 tag_we;
 
wire [`WB_TAG_RNG] tag_load_set0   = tag_load[`TAG_LINE_TAG0_RNG];
wire [`WB_TAG_RNG] tag_load_set1   = tag_load[`TAG_LINE_TAG1_RNG];
wire               tag_load_dirty0 = tag_load[`TAG_LINE_DIRTY0_RNG];
wire               tag_load_dirty1 = tag_load[`TAG_LINE_DIRTY1_RNG];
wire               tag_load_lru    = tag_load[`TAG_LINE_LRU_RNG];
 
reg [`WB_TAG_RNG] tag_store_set0;
reg [`WB_TAG_RNG] tag_store_set1;
reg               tag_store_dirty0;
reg               tag_store_dirty1;
reg               tag_store_lru;
 
assign tag_store[`TAG_LINE_TAG0_RNG]   = tag_store_set0;
assign tag_store[`TAG_LINE_TAG1_RNG]   = tag_store_set1;
assign tag_store[`TAG_LINE_DIRTY0_RNG] = tag_store_dirty0;
assign tag_store[`TAG_LINE_DIRTY1_RNG] = tag_store_dirty1;
assign tag_store[`TAG_LINE_LRU_RNG]    = tag_store_lru;
 
wire [`WB_SET_RNG]   ls_tag_adr;
wire [`TAG_LINE_RNG] ls_tag_load;
reg  [`TAG_LINE_RNG] ls_tag_store;
reg                  ls_tag_we;
 
dpram #(
        .adr_width(   7 ),
        .dat_width(  33 )
) tag_ram (
        .clk (     clk         ),
        //
        .adr0(     wb_adr_set  ),
        .dout0(    tag_load    ),
        .din0(     tag_store   ),
        .we0(      tag_we      ),
        //
        .adr1(     ls_tag_adr   ),
        .dout1(    ls_tag_load  ),
        .din1(     ls_tag_store ),
        .we1(      ls_tag_we    )
);
 
wire tag_load_match0 = (tag_load_set0 == wb_adr_tag);
wire tag_load_match1 = (tag_load_set1 == wb_adr_tag);
wire tag_load_match  = tag_load_match0 | tag_load_match1;
 
//----------------------------------------------------------------------------
// Buffer cache ram (2 ways)
//----------------------------------------------------------------------------
wire [8:0] wayX_adr = { wb_adr_set, wb_adr_word };
 
wire [`WAY_LINE_RNG]  way0_load, way1_load;
wire [`WAY_LINE_RNG]  wayX_store;
 
wire [31:0]   way0_load_dat   = way0_load[`WAY_DAT_RNG];
wire [31:0]   way1_load_dat   = way1_load[`WAY_DAT_RNG];
wire [3:0]    way0_load_valid = way0_load[`WAY_VALID_RNG];
wire [3:0]    way1_load_valid = way1_load[`WAY_VALID_RNG];
 
wire          way0_we;
wire          way1_we;
reg  [31:0]   wayX_store_dat;
reg  [3:0]    wayX_store_valid;
 
assign wayX_store[`WAY_DAT_RNG]   = wayX_store_dat;
assign wayX_store[`WAY_VALID_RNG] = wayX_store_valid;
 
wire [8:0]            ls_wayX_adr;
wire [`WAY_LINE_RNG]  ls_way0_load;
wire [`WAY_LINE_RNG]  ls_way1_load;
wire [`WAY_LINE_RNG]  ls_wayX_store;
wire                  ls_way0_we;
wire                  ls_way1_we;
reg                   ls_wayX_we;
 
wire way0_sel_valid = ( (~way0_load_valid & wb_sel_i) == 'b0);
wire way1_sel_valid = ( (~way1_load_valid & wb_sel_i) == 'b0);
wire wayX_sel_valid = (tag_load_match0) ? way0_sel_valid : way1_sel_valid;
 
// synthesis attribute ram_style of way0_ram is block
dpram #(
        .adr_width(   9 ),
        .dat_width(  36 )
) way0_ram (
        .clk(    clk         ),
        //
        .adr0(   wayX_adr    ),
        .dout0(  way0_load   ),
        .din0(   wayX_store  ),
        .we0(    way0_we     ),
        //
        .adr1(   ls_wayX_adr   ),
        .dout1(  ls_way0_load  ),
        .we1(    ls_way0_we    ),
        .din1(   ls_wayX_store )
);
 
// synthesis attribute ram_style of way1_ram is block
dpram #(
        .adr_width(   9 ),
        .dat_width(  36 )
) way1_ram (
        .clk(    clk         ),
        //
        .adr0(   wayX_adr    ),
        .dout0(  way1_load   ),
        .din0(   wayX_store  ),
        .we0(    way1_we     ),
        //
        .adr1(   ls_wayX_adr   ),
        .dout1(  ls_way1_load  ),
        .we1(    ls_way1_we    ),
        .din1(   ls_wayX_store )
);
 
//----------------------------------------------------------------------------
// Write/update buffer cache from wishbone side
//----------------------------------------------------------------------------
wire store_to_way0 =  tag_load_lru & ~tag_load_dirty0;   // store new data into way0?  XXX spill_done XXX
wire store_to_way1 = ~tag_load_lru & ~tag_load_dirty1;   // store new data into way1?  XXX spill_done XXX
wire store_to_way  =  store_to_way0 | store_to_way1;
 
reg update_lru0;  // 
reg update_lru1;
 
reg update_way0;  //
reg update_way1;
 
assign way0_we = update_way0;
assign way1_we = update_way1;
assign tag_we  = way0_we | way1_we | update_lru0 | update_lru1;
 
//----------------------------------------------------------------------------
// MUX wayX_store input
//----------------------------------------------------------------------------
 
integer  i;
always @(*)
begin
/*
        for(i=0; i<4; i=i+1) begin
                if (wb_sel_i[i]) begin
                        wayX_store_dat[8*i+7:8*i] = wb_dat_i[8*i+7:8*i];
                        wayX_store_valid[i]       = 1;
                end else if (update_way0) begin
                        wayX_store_dat[8*i+7:8*i] = way0_load_dat[8*i+7:8*i];
                        wayX_store_valid[i]       = way0_load_valid[i];
                end else begin
                        wayX_store_dat[8*i+7:8*i] = way1_load_dat[8*i+7:8*i];
                        wayX_store_valid[i]       = way1_load_valid[i];
                end
        end
*/
 
        if (wb_sel_i[0]) begin
                wayX_store_dat[8*0+7:8*0] = wb_dat_i[8*0+7:8*0];
                wayX_store_valid[0]       = 1;
        end else if (update_way0) begin
                wayX_store_dat[8*0+7:8*0] = way0_load_dat[8*0+7:8*0];
                wayX_store_valid[0]       = way0_load_valid[0];
        end else begin
                wayX_store_dat[8*0+7:8*0] = way1_load_dat[8*0+7:8*0];
                wayX_store_valid[0]       = way1_load_valid[0];
        end
 
        if (wb_sel_i[1]) begin
                wayX_store_dat[8*1+7:8*1] = wb_dat_i[8*1+7:8*1];
                wayX_store_valid[1]       = 1;
        end else if (update_way0) begin
                wayX_store_dat[8*1+7:8*1] = way0_load_dat[8*1+7:8*1];
                wayX_store_valid[1]       = way0_load_valid[1];
        end else begin
                wayX_store_dat[8*1+7:8*1] = way1_load_dat[8*1+7:8*1];
                wayX_store_valid[1]       = way1_load_valid[1];
        end
 
        if (wb_sel_i[2]) begin
                wayX_store_dat[8*2+7:8*2] = wb_dat_i[8*2+7:8*2];
                wayX_store_valid[2]       = 1;
        end else if (update_way0) begin
                wayX_store_dat[8*2+7:8*2] = way0_load_dat[8*2+7:8*2];
                wayX_store_valid[2]       = way0_load_valid[2];
        end else begin
                wayX_store_dat[8*2+7:8*2] = way1_load_dat[8*2+7:8*2];
                wayX_store_valid[2]       = way1_load_valid[2];
        end
 
        if (wb_sel_i[3]) begin
                wayX_store_dat[8*3+7:8*3] = wb_dat_i[8*3+7:8*3];
                wayX_store_valid[3]       = 1;
        end else if (update_way0) begin
                wayX_store_dat[8*3+7:8*3] = way0_load_dat[8*3+7:8*3];
                wayX_store_valid[3]       = way0_load_valid[3];
        end else begin
                wayX_store_dat[8*3+7:8*3] = way1_load_dat[8*3+7:8*3];
                wayX_store_valid[3]       = way1_load_valid[3];
        end
end
 
always @(*)
begin
        if (update_way0) begin
                tag_store_set0    = wb_adr_tag;
                tag_store_dirty0  = 1;
        end else begin
                tag_store_set0    = tag_load_set0;
                tag_store_dirty0  = tag_load_dirty0;
        end
 
        if (update_way1) begin
                tag_store_set1    = wb_adr_tag;
                tag_store_dirty1  = 1;
        end else begin
                tag_store_set1    = tag_load_set1;
                tag_store_dirty1  = tag_load_dirty1;
        end
 
        if (update_lru0)
                tag_store_lru     = 0;
        else if (update_lru1)
                tag_store_lru     = 1;
        else
                tag_store_lru     = tag_load_lru;
end
 
//----------------------------------------------------------------------------
// Wishbone FSM
//----------------------------------------------------------------------------
reg  ls_fill;
reg  ls_spill;
reg  ls_way;
wire ls_busy;
 
reg [`WB_TAG_RNG]  ls_adr_tag;
reg [`WB_SET_RNG]  ls_adr_set;
reg [`WB_WORD_RNG] ls_adr_word;
 
reg  [2:0] state;
 
parameter s_idle   = 0;
parameter s_read   = 1;
parameter s_rspill = 2;
parameter s_rfill  = 3;
parameter s_write  = 4;
parameter s_wspill = 5;
 
// Syncronous part of FSM
always @(posedge clk)
begin
        if (reset) begin
                state    <= s_idle;
                ls_spill <= 0;
                ls_fill  <= 0;
                ls_way   <= 0;
        end else begin
                ls_fill   <=  0;
                ls_spill  <=  0;
 
                case (state)
                s_idle: begin
                        if (wb_rd)
                                state      <= s_read;
 
                        if (wb_wr)
                                state      <= s_write;
                end
                s_read: begin
                        if ((tag_load_match0 & way0_sel_valid) | (tag_load_match1 & way1_sel_valid)) begin
                                state      <= s_idle;
                        end else if (store_to_way & ~ls_busy) begin
                                state      <= s_rfill;
                                ls_fill    <=  1;
                                ls_way     <= ~tag_load_lru;
                                ls_adr_tag <=  wb_adr_tag;
                                ls_adr_set <=  wb_adr_set;
                        end else if (~ls_busy) begin
                                state      <= s_rspill;
                                ls_spill   <=  1;
                                ls_way     <= ~tag_load_lru;
                                ls_adr_set <=  wb_adr_set;
                                if (tag_load_lru == 1)
                                        ls_adr_tag <=  tag_load_set0;
                                else
                                        ls_adr_tag <=  tag_load_set1;
                        end
                end
                s_rspill: begin
                        if (~ls_busy) begin
                                state      <= s_rfill;
                                ls_fill    <=  1;
                                ls_way     <= ~tag_load_lru;
                                ls_adr_tag <=  wb_adr_tag;
                                ls_adr_set <=  wb_adr_set;
                        end
                end
                s_rfill: begin
                        if (tag_load_match & wayX_sel_valid)
                                state      <= s_idle;
                end
                s_write: begin
                        if (tag_load_match | store_to_way) begin
                                state      <= s_idle;
                        end else if (~ls_busy) begin
                                state      <= s_wspill;
                                ls_spill   <=  1;
                                ls_way     <= ~tag_load_lru;
                                ls_adr_set <=  wb_adr_set;
                                if (tag_load_lru == 1)
                                        ls_adr_tag <=  tag_load_set0;
                                else
                                        ls_adr_tag <=  tag_load_set1;
                        end
                end
                s_wspill: begin
                        if (tag_load_match | store_to_way) begin
                                state      <= s_idle;
                        end
                end
                default:
                        state <= s_idle;
                endcase
        end
end
 
// Asyncronous part of FSM
always @(*)
begin
        update_lru0  <= 0;
        update_lru1  <= 0;
        update_way0  <= 0;
        update_way1  <= 0;
        wb_dat_o     <= 0;
        wb_ack_o     <= 0;
 
        case (state)
        s_idle: begin end
        s_read: begin
                if (tag_load_match0 & way0_sel_valid) begin
                        update_lru0  <= 1;
                        wb_dat_o     <= way0_load_dat;
                        wb_ack_o     <= 1;
                end else if (tag_load_match1 & way1_sel_valid) begin
                        update_lru1  <= 1;
                        wb_dat_o     <= way1_load_dat;
                        wb_ack_o     <= 1;
                end
        end
        s_write: begin
                if (tag_load_match0 | store_to_way0) begin
                        update_lru0  <= 1;
                        update_way0  <= 1;
                        wb_ack_o     <= 1;
                end else if (tag_load_match1 | store_to_way1) begin
                        update_lru1  <= 1;
                        update_way1  <= 1;
                        wb_ack_o     <= 1;
                end
        end
        endcase
end
 
 
 
//----------------------------------------------------------------------------
// DDR Controller Engine (including clkgen, [rw]-path)
//----------------------------------------------------------------------------
reg                 fml_rd;
reg                 fml_wr;
wire                fml_done;
wire [`FML_ADR_RNG] fml_adr;
wire [`FML_DAT_RNG] fml_wdat;
wire [`FML_BE_RNG]  fml_wbe;
reg                 fml_wnext;
reg                 fml_wnext2;
wire                fml_rempty;
reg                 fml_rnext;
wire [`FML_DAT_RNG] fml_rdat;
 
ddr_ctrl #(
        .phase_shift(  phase_shift  ),
        .clk_multiply( clk_multiply ),
        .clk_divide(   clk_divide   ),
        .wait200_init( wait200_init )
) ctrl0 (
        .clk(          clk         ),
        .reset(        reset       ),
        .rot(          rot         ),
        // DDR Ports
        .ddr_clk(      ddr_clk     ),
        .ddr_clk_n(    ddr_clk_n   ),
        .ddr_clk_fb(   ddr_clk_fb  ),
        .ddr_ras_n(    ddr_ras_n   ),
        .ddr_cas_n(    ddr_cas_n   ),
        .ddr_we_n(     ddr_we_n    ),
        .ddr_cke(      ddr_cke     ),
        .ddr_cs_n(     ddr_cs_n    ),
        .ddr_a(        ddr_a       ),
        .ddr_ba(       ddr_ba      ),
        .ddr_dq(       ddr_dq      ),
        .ddr_dqs(      ddr_dqs     ),
        .ddr_dm(       ddr_dm      ),
        // FML (FastMemoryLink)
        .fml_rd(       fml_rd      ),
        .fml_wr(       fml_wr      ),
        .fml_done(     fml_done    ),
        .fml_adr(      fml_adr     ),
        .fml_wdat(     fml_wdat    ),
        .fml_wbe(      fml_wbe     ),
        .fml_wnext(    fml_wnext2  ),
        .fml_rempty(   fml_rempty  ),
        .fml_rdat(     fml_rdat    ),
        .fml_rnext(    fml_rnext   )
);
 
assign fml_adr = { ls_adr_tag, ls_adr_set };
 
assign fml_wdat  = (ls_way) ? ls_way1_load[`WAY_DAT_RNG] :
                              ls_way0_load[`WAY_DAT_RNG];
 
assign fml_wbe   = (ls_way) ? ls_way1_load[`WAY_VALID_RNG] :
                              ls_way0_load[`WAY_VALID_RNG];
 
assign ls_tag_adr    = { ls_adr_set };
assign ls_wayX_adr   = { ls_adr_set, ls_adr_word };
assign ls_way0_we    = ls_wayX_we & ~ls_way;
assign ls_way1_we    = ls_wayX_we &  ls_way;
 
assign ls_wayX_store[`WAY_DAT_RNG]   = fml_rdat;
assign ls_wayX_store[`WAY_VALID_RNG] = 4'b1111;
 
 
//----------------------------------------------------------------------------
// LS (Load and Store) Engine
//----------------------------------------------------------------------------
parameter l_idle     = 0;
parameter l_fill     = 1;
parameter l_spill    = 2;
parameter l_waitdone = 3;
 
reg [2:0] ls_state;
assign ls_busy = (ls_state != l_idle) || ls_fill || ls_spill;
 
// Syncronous part FSM
always @(posedge clk)
begin
        if (reset) begin
                ls_state     <= l_idle;
                ls_adr_word  <= 0;
                fml_wr       <= 0;
                fml_rd       <= 0;
        end else begin
                fml_wnext2 <= fml_wnext;
 
                case (ls_state)
                l_idle: begin
                        ls_adr_word <= 0;
 
                        if (ls_spill) begin
                                ls_state    <= l_spill;
                                ls_adr_word <= ls_adr_word + 1;
                        end
                        if (ls_fill) begin
                                ls_state    <= l_fill;
                                fml_rd      <= 1;
                        end
                end
                l_spill: begin
                        ls_adr_word <= ls_adr_word + 1;
 
                        if (ls_adr_word == 3) begin
                                ls_state    <= l_waitdone;
                                fml_wr      <= 1;
                        end
                end
                l_waitdone: begin
                        ls_adr_word <= 0;
 
                        if (fml_done) begin
                                ls_state    <= l_idle;
                                fml_wr      <= 0;
                        end
                end
                l_fill: begin
                        if (fml_done)
                                fml_rd <= 0;
 
                        if (~fml_rempty)
                                ls_adr_word <= ls_adr_word + 1;
 
                        if (~fml_rempty & (ls_adr_word == 3))
                                ls_state    <= l_idle;
                end
                endcase
        end
end
 
always @(*)
begin
        fml_wnext      <= 0;
        fml_rnext      <= 0;
        ls_tag_we      <= 0;
        ls_tag_store   <= ls_tag_load;
        ls_wayX_we     <= 0;
 
        case (ls_state)
        l_idle: begin
                if (ls_spill) begin
                        fml_wnext  <= 1;
                end
        end
        l_spill: begin
                fml_wnext      <= 1;
        end
        l_waitdone: begin
                if (ls_way == 0)
                        ls_tag_store[`TAG_LINE_DIRTY0_RNG] <= 0;
                else
                        ls_tag_store[`TAG_LINE_DIRTY1_RNG] <= 0;
 
                if (fml_done)
                        ls_tag_we    <= 1;
        end
        l_fill: begin
                if (ls_way == 0) begin
                        ls_tag_store[`TAG_LINE_DIRTY0_RNG] <= 0;
                        ls_tag_store[`TAG_LINE_TAG0_RNG]   <= ls_adr_tag;
                end else begin
                        ls_tag_store[`TAG_LINE_DIRTY1_RNG] <= 0;
                        ls_tag_store[`TAG_LINE_TAG1_RNG]   <= ls_adr_tag;
                end
 
                if (~fml_rempty) begin
                        ls_wayX_we  <= 1;
                        fml_rnext   <= 1;
                end
 
                if (~fml_rempty & (ls_adr_word == 3))
                        ls_tag_we   <= 1;
        end
        endcase
end
 
always @(posedge clk)
begin
        if (ls_fill)
                $display ("At time %t WB_DDR fill cacheline: TAG = %h, SET = %h)", $time, ls_adr_tag, ls_adr_set);
 
        if (ls_spill)
                $display ("At time %t WB_DDR spill cacheline: TAG = %h, SET = %h)", $time, ls_adr_tag, ls_adr_set);
end
 
 
endmodule

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[/] [m1_core/] [trunk/] [hdl/] [rtl/] [wb_ddr_ctrl/] [wb_ddr.v] - Blame information for rev 54

Line No.	Rev	Author	Line
1	34	fafa1971	`//----------------------------------------------------------------------------`
2			`// Wishbone DDR Controller`
3			`//`
4			`// (c) Joerg Bornschein (<jb@capsec.org>)`
5			`//----------------------------------------------------------------------------`
6
7			`include "ddr_include.v"
8
9			`module wb_ddr`
10			`#(`
11			`parameter phase_shift = 0,`
12			`parameter clk_multiply = 12,`
13			`parameter clk_divide = 5,`
14			`parameter wait200_init = 26`
15			`) (`
16			`input clk,`
17			`input reset,`
18			`// XXX -- DCM phase control -- XXX`
19			`input [2:0] rot,`
20			`// DDR ports`
21			`output ddr_clk,`
22			`output ddr_clk_n,`
23			`input ddr_clk_fb,`
24			`output ddr_ras_n,`
25			`output ddr_cas_n,`
26			`output ddr_we_n,`
27			`output ddr_cke,`
28			`output ddr_cs_n,`
29			output [ `A_RNG] ddr_a,
30			output [ `BA_RNG] ddr_ba,
31			inout [ `DQ_RNG] ddr_dq,
32			inout [`DQS_RNG] ddr_dqs,
33			output [ `DM_RNG] ddr_dm,
34			`// Wishbone Slave Interface`
35			input [`WB_ADR_RNG] wb_adr_i,
36			input [`WB_DAT_RNG] wb_dat_i,
37			output reg [`WB_DAT_RNG] wb_dat_o,
38			input [`WB_SEL_RNG] wb_sel_i,
39			`input wb_cyc_i,`
40			`input wb_stb_i,`
41			`input wb_we_i,`
42			`output reg wb_ack_o`
43			`);`
44
45			`//----------------------------------------------------------------------------`
46			`// Wishbone handling`
47			`//----------------------------------------------------------------------------`
48			`wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i;`
49			`wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i;`
50
51			wire [`WB_WORD_RNG] wb_adr_word = wb_adr_i[`WB_WORD_RNG]; // word in bufferline
52			wire [`WB_SET_RNG] wb_adr_set = wb_adr_i[`WB_SET_RNG]; // index into wayX_ram
53			wire [`WB_TAG_RNG] wb_adr_tag = wb_adr_i[`WB_TAG_RNG]; // more significant bits
54
55			`//----------------------------------------------------------------------------`
56			`// TAG RAM (2-way set assioziative)`
57			`//----------------------------------------------------------------------------`
58			wire [`TAG_LINE_RNG] tag_load;
59			wire [`TAG_LINE_RNG] tag_store;
60			`wire tag_we;`
61
62			wire [`WB_TAG_RNG] tag_load_set0 = tag_load[`TAG_LINE_TAG0_RNG];
63			wire [`WB_TAG_RNG] tag_load_set1 = tag_load[`TAG_LINE_TAG1_RNG];
64			wire tag_load_dirty0 = tag_load[`TAG_LINE_DIRTY0_RNG];
65			wire tag_load_dirty1 = tag_load[`TAG_LINE_DIRTY1_RNG];
66			wire tag_load_lru = tag_load[`TAG_LINE_LRU_RNG];
67
68			reg [`WB_TAG_RNG] tag_store_set0;
69			reg [`WB_TAG_RNG] tag_store_set1;
70			`reg tag_store_dirty0;`
71			`reg tag_store_dirty1;`
72			`reg tag_store_lru;`
73
74			assign tag_store[`TAG_LINE_TAG0_RNG] = tag_store_set0;
75			assign tag_store[`TAG_LINE_TAG1_RNG] = tag_store_set1;
76			assign tag_store[`TAG_LINE_DIRTY0_RNG] = tag_store_dirty0;
77			assign tag_store[`TAG_LINE_DIRTY1_RNG] = tag_store_dirty1;
78			assign tag_store[`TAG_LINE_LRU_RNG] = tag_store_lru;
79
80			wire [`WB_SET_RNG] ls_tag_adr;
81			wire [`TAG_LINE_RNG] ls_tag_load;
82			reg [`TAG_LINE_RNG] ls_tag_store;
83			`reg ls_tag_we;`
84
85			`dpram #(`
86			`.adr_width( 7 ),`
87			`.dat_width( 33 )`
88			`) tag_ram (`
89			`.clk ( clk ),`
90			`//`
91			`.adr0( wb_adr_set ),`
92			`.dout0( tag_load ),`
93			`.din0( tag_store ),`
94			`.we0( tag_we ),`
95			`//`
96			`.adr1( ls_tag_adr ),`
97			`.dout1( ls_tag_load ),`
98			`.din1( ls_tag_store ),`
99			`.we1( ls_tag_we )`
100			`);`
101
102			`wire tag_load_match0 = (tag_load_set0 == wb_adr_tag);`
103			`wire tag_load_match1 = (tag_load_set1 == wb_adr_tag);`
104			`wire tag_load_match = tag_load_match0 \| tag_load_match1;`
105
106			`//----------------------------------------------------------------------------`
107			`// Buffer cache ram (2 ways)`
108			`//----------------------------------------------------------------------------`
109			`wire [8:0] wayX_adr = { wb_adr_set, wb_adr_word };`
110
111			wire [`WAY_LINE_RNG] way0_load, way1_load;
112			wire [`WAY_LINE_RNG] wayX_store;
113
114			wire [31:0] way0_load_dat = way0_load[`WAY_DAT_RNG];
115			wire [31:0] way1_load_dat = way1_load[`WAY_DAT_RNG];
116			wire [3:0] way0_load_valid = way0_load[`WAY_VALID_RNG];
117			wire [3:0] way1_load_valid = way1_load[`WAY_VALID_RNG];
118
119			`wire way0_we;`
120			`wire way1_we;`
121			`reg [31:0] wayX_store_dat;`
122			`reg [3:0] wayX_store_valid;`
123
124			assign wayX_store[`WAY_DAT_RNG] = wayX_store_dat;
125			assign wayX_store[`WAY_VALID_RNG] = wayX_store_valid;
126
127			`wire [8:0] ls_wayX_adr;`
128			wire [`WAY_LINE_RNG] ls_way0_load;
129			wire [`WAY_LINE_RNG] ls_way1_load;
130			wire [`WAY_LINE_RNG] ls_wayX_store;
131			`wire ls_way0_we;`
132			`wire ls_way1_we;`
133			`reg ls_wayX_we;`
134
135			`wire way0_sel_valid = ( (~way0_load_valid & wb_sel_i) == 'b0);`
136			`wire way1_sel_valid = ( (~way1_load_valid & wb_sel_i) == 'b0);`
137			`wire wayX_sel_valid = (tag_load_match0) ? way0_sel_valid : way1_sel_valid;`
138
139			`// synthesis attribute ram_style of way0_ram is block`
140			`dpram #(`
141			`.adr_width( 9 ),`
142			`.dat_width( 36 )`
143			`) way0_ram (`
144			`.clk( clk ),`
145			`//`
146			`.adr0( wayX_adr ),`
147			`.dout0( way0_load ),`
148			`.din0( wayX_store ),`
149			`.we0( way0_we ),`
150			`//`
151			`.adr1( ls_wayX_adr ),`
152			`.dout1( ls_way0_load ),`
153			`.we1( ls_way0_we ),`
154			`.din1( ls_wayX_store )`
155			`);`
156
157			`// synthesis attribute ram_style of way1_ram is block`
158			`dpram #(`
159			`.adr_width( 9 ),`
160			`.dat_width( 36 )`
161			`) way1_ram (`
162			`.clk( clk ),`
163			`//`
164			`.adr0( wayX_adr ),`
165			`.dout0( way1_load ),`
166			`.din0( wayX_store ),`
167			`.we0( way1_we ),`
168			`//`
169			`.adr1( ls_wayX_adr ),`
170			`.dout1( ls_way1_load ),`
171			`.we1( ls_way1_we ),`
172			`.din1( ls_wayX_store )`
173			`);`
174
175			`//----------------------------------------------------------------------------`
176			`// Write/update buffer cache from wishbone side`
177			`//----------------------------------------------------------------------------`
178			`wire store_to_way0 = tag_load_lru & ~tag_load_dirty0; // store new data into way0? XXX spill_done XXX`
179			`wire store_to_way1 = ~tag_load_lru & ~tag_load_dirty1; // store new data into way1? XXX spill_done XXX`
180			`wire store_to_way = store_to_way0 \| store_to_way1;`
181
182			`reg update_lru0; //`
183			`reg update_lru1;`
184
185			`reg update_way0; //`
186			`reg update_way1;`
187
188			`assign way0_we = update_way0;`
189			`assign way1_we = update_way1;`
190			`assign tag_we = way0_we \| way1_we \| update_lru0 \| update_lru1;`
191
192			`//----------------------------------------------------------------------------`
193			`// MUX wayX_store input`
194			`//----------------------------------------------------------------------------`
195
196			`integer i;`
197			`always @(*)`
198			`begin`
199			`/*`
200			`for(i=0; i<4; i=i+1) begin`
201			`if (wb_sel_i[i]) begin`
202			`wayX_store_dat[8i+7:8i] = wb_dat_i[8i+7:8i];`
203			`wayX_store_valid[i] = 1;`
204			`end else if (update_way0) begin`
205			`wayX_store_dat[8i+7:8i] = way0_load_dat[8i+7:8i];`
206			`wayX_store_valid[i] = way0_load_valid[i];`
207			`end else begin`
208			`wayX_store_dat[8i+7:8i] = way1_load_dat[8i+7:8i];`
209			`wayX_store_valid[i] = way1_load_valid[i];`
210			`end`
211			`end`
212			`*/`
213
214			`if (wb_sel_i[0]) begin`
215			`wayX_store_dat[80+7:80] = wb_dat_i[80+7:80];`
216			`wayX_store_valid[0] = 1;`
217			`end else if (update_way0) begin`
218			`wayX_store_dat[80+7:80] = way0_load_dat[80+7:80];`
219			`wayX_store_valid[0] = way0_load_valid[0];`
220			`end else begin`
221			`wayX_store_dat[80+7:80] = way1_load_dat[80+7:80];`
222			`wayX_store_valid[0] = way1_load_valid[0];`
223			`end`
224
225			`if (wb_sel_i[1]) begin`
226			`wayX_store_dat[81+7:81] = wb_dat_i[81+7:81];`
227			`wayX_store_valid[1] = 1;`
228			`end else if (update_way0) begin`
229			`wayX_store_dat[81+7:81] = way0_load_dat[81+7:81];`
230			`wayX_store_valid[1] = way0_load_valid[1];`
231			`end else begin`
232			`wayX_store_dat[81+7:81] = way1_load_dat[81+7:81];`
233			`wayX_store_valid[1] = way1_load_valid[1];`
234			`end`
235
236			`if (wb_sel_i[2]) begin`
237			`wayX_store_dat[82+7:82] = wb_dat_i[82+7:82];`
238			`wayX_store_valid[2] = 1;`
239			`end else if (update_way0) begin`
240			`wayX_store_dat[82+7:82] = way0_load_dat[82+7:82];`
241			`wayX_store_valid[2] = way0_load_valid[2];`
242			`end else begin`
243			`wayX_store_dat[82+7:82] = way1_load_dat[82+7:82];`
244			`wayX_store_valid[2] = way1_load_valid[2];`
245			`end`
246
247			`if (wb_sel_i[3]) begin`
248			`wayX_store_dat[83+7:83] = wb_dat_i[83+7:83];`
249			`wayX_store_valid[3] = 1;`
250			`end else if (update_way0) begin`
251			`wayX_store_dat[83+7:83] = way0_load_dat[83+7:83];`
252			`wayX_store_valid[3] = way0_load_valid[3];`
253			`end else begin`
254			`wayX_store_dat[83+7:83] = way1_load_dat[83+7:83];`
255			`wayX_store_valid[3] = way1_load_valid[3];`
256			`end`
257			`end`
258
259			`always @(*)`
260			`begin`
261			`if (update_way0) begin`
262			`tag_store_set0 = wb_adr_tag;`
263			`tag_store_dirty0 = 1;`
264			`end else begin`
265			`tag_store_set0 = tag_load_set0;`
266			`tag_store_dirty0 = tag_load_dirty0;`
267			`end`
268
269			`if (update_way1) begin`
270			`tag_store_set1 = wb_adr_tag;`
271			`tag_store_dirty1 = 1;`
272			`end else begin`
273			`tag_store_set1 = tag_load_set1;`
274			`tag_store_dirty1 = tag_load_dirty1;`
275			`end`
276
277			`if (update_lru0)`
278			`tag_store_lru = 0;`
279			`else if (update_lru1)`
280			`tag_store_lru = 1;`
281			`else`
282			`tag_store_lru = tag_load_lru;`
283			`end`
284
285			`//----------------------------------------------------------------------------`
286			`// Wishbone FSM`
287			`//----------------------------------------------------------------------------`
288			`reg ls_fill;`
289			`reg ls_spill;`
290			`reg ls_way;`
291			`wire ls_busy;`
292
293			reg [`WB_TAG_RNG] ls_adr_tag;
294			reg [`WB_SET_RNG] ls_adr_set;
295			reg [`WB_WORD_RNG] ls_adr_word;
296
297			`reg [2:0] state;`
298
299			`parameter s_idle = 0;`
300			`parameter s_read = 1;`
301			`parameter s_rspill = 2;`
302			`parameter s_rfill = 3;`
303			`parameter s_write = 4;`
304			`parameter s_wspill = 5;`
305
306			`// Syncronous part of FSM`
307			`always @(posedge clk)`
308			`begin`
309			`if (reset) begin`
310			`state <= s_idle;`
311			`ls_spill <= 0;`
312			`ls_fill <= 0;`
313			`ls_way <= 0;`
314			`end else begin`
315			`ls_fill <= 0;`
316			`ls_spill <= 0;`
317
318			`case (state)`
319			`s_idle: begin`
320			`if (wb_rd)`
321			`state <= s_read;`
322
323			`if (wb_wr)`
324			`state <= s_write;`
325			`end`
326			`s_read: begin`
327			`if ((tag_load_match0 & way0_sel_valid) \| (tag_load_match1 & way1_sel_valid)) begin`
328			`state <= s_idle;`
329			`end else if (store_to_way & ~ls_busy) begin`
330			`state <= s_rfill;`
331			`ls_fill <= 1;`
332			`ls_way <= ~tag_load_lru;`
333			`ls_adr_tag <= wb_adr_tag;`
334			`ls_adr_set <= wb_adr_set;`
335			`end else if (~ls_busy) begin`
336			`state <= s_rspill;`
337			`ls_spill <= 1;`
338			`ls_way <= ~tag_load_lru;`
339			`ls_adr_set <= wb_adr_set;`
340			`if (tag_load_lru == 1)`
341			`ls_adr_tag <= tag_load_set0;`
342			`else`
343			`ls_adr_tag <= tag_load_set1;`
344			`end`
345			`end`
346			`s_rspill: begin`
347			`if (~ls_busy) begin`
348			`state <= s_rfill;`
349			`ls_fill <= 1;`
350			`ls_way <= ~tag_load_lru;`
351			`ls_adr_tag <= wb_adr_tag;`
352			`ls_adr_set <= wb_adr_set;`
353			`end`
354			`end`
355			`s_rfill: begin`
356			`if (tag_load_match & wayX_sel_valid)`
357			`state <= s_idle;`
358			`end`
359			`s_write: begin`
360			`if (tag_load_match \| store_to_way) begin`
361			`state <= s_idle;`
362			`end else if (~ls_busy) begin`
363			`state <= s_wspill;`
364			`ls_spill <= 1;`
365			`ls_way <= ~tag_load_lru;`
366			`ls_adr_set <= wb_adr_set;`
367			`if (tag_load_lru == 1)`
368			`ls_adr_tag <= tag_load_set0;`
369			`else`
370			`ls_adr_tag <= tag_load_set1;`
371			`end`
372			`end`
373			`s_wspill: begin`
374			`if (tag_load_match \| store_to_way) begin`
375			`state <= s_idle;`
376			`end`
377			`end`
378			`default:`
379			`state <= s_idle;`
380			`endcase`
381			`end`
382			`end`
383
384			`// Asyncronous part of FSM`
385			`always @(*)`
386			`begin`
387			`update_lru0 <= 0;`
388			`update_lru1 <= 0;`
389			`update_way0 <= 0;`
390			`update_way1 <= 0;`
391			`wb_dat_o <= 0;`
392			`wb_ack_o <= 0;`
393
394			`case (state)`
395			`s_idle: begin end`
396			`s_read: begin`
397			`if (tag_load_match0 & way0_sel_valid) begin`
398			`update_lru0 <= 1;`
399			`wb_dat_o <= way0_load_dat;`
400			`wb_ack_o <= 1;`
401			`end else if (tag_load_match1 & way1_sel_valid) begin`
402			`update_lru1 <= 1;`
403			`wb_dat_o <= way1_load_dat;`
404			`wb_ack_o <= 1;`
405			`end`
406			`end`
407			`s_write: begin`
408			`if (tag_load_match0 \| store_to_way0) begin`
409			`update_lru0 <= 1;`
410			`update_way0 <= 1;`
411			`wb_ack_o <= 1;`
412			`end else if (tag_load_match1 \| store_to_way1) begin`
413			`update_lru1 <= 1;`
414			`update_way1 <= 1;`
415			`wb_ack_o <= 1;`
416			`end`
417			`end`
418			`endcase`
419			`end`
420
421
422
423			`//----------------------------------------------------------------------------`
424			`// DDR Controller Engine (including clkgen, [rw]-path)`
425			`//----------------------------------------------------------------------------`
426			`reg fml_rd;`
427			`reg fml_wr;`
428			`wire fml_done;`
429			wire [`FML_ADR_RNG] fml_adr;
430			wire [`FML_DAT_RNG] fml_wdat;
431			wire [`FML_BE_RNG] fml_wbe;
432			`reg fml_wnext;`
433			`reg fml_wnext2;`
434			`wire fml_rempty;`
435			`reg fml_rnext;`
436			wire [`FML_DAT_RNG] fml_rdat;
437
438			`ddr_ctrl #(`
439			`.phase_shift( phase_shift ),`
440			`.clk_multiply( clk_multiply ),`
441			`.clk_divide( clk_divide ),`
442			`.wait200_init( wait200_init )`
443			`) ctrl0 (`
444			`.clk( clk ),`
445			`.reset( reset ),`
446			`.rot( rot ),`
447			`// DDR Ports`
448			`.ddr_clk( ddr_clk ),`
449			`.ddr_clk_n( ddr_clk_n ),`
450			`.ddr_clk_fb( ddr_clk_fb ),`
451			`.ddr_ras_n( ddr_ras_n ),`
452			`.ddr_cas_n( ddr_cas_n ),`
453			`.ddr_we_n( ddr_we_n ),`
454			`.ddr_cke( ddr_cke ),`
455			`.ddr_cs_n( ddr_cs_n ),`
456			`.ddr_a( ddr_a ),`
457			`.ddr_ba( ddr_ba ),`
458			`.ddr_dq( ddr_dq ),`
459			`.ddr_dqs( ddr_dqs ),`
460			`.ddr_dm( ddr_dm ),`
461			`// FML (FastMemoryLink)`
462			`.fml_rd( fml_rd ),`
463			`.fml_wr( fml_wr ),`
464			`.fml_done( fml_done ),`
465			`.fml_adr( fml_adr ),`
466			`.fml_wdat( fml_wdat ),`
467			`.fml_wbe( fml_wbe ),`
468			`.fml_wnext( fml_wnext2 ),`
469			`.fml_rempty( fml_rempty ),`
470			`.fml_rdat( fml_rdat ),`
471			`.fml_rnext( fml_rnext )`
472			`);`
473
474			`assign fml_adr = { ls_adr_tag, ls_adr_set };`
475
476			assign fml_wdat = (ls_way) ? ls_way1_load[`WAY_DAT_RNG] :
477			ls_way0_load[`WAY_DAT_RNG];
478
479			assign fml_wbe = (ls_way) ? ls_way1_load[`WAY_VALID_RNG] :
480			ls_way0_load[`WAY_VALID_RNG];
481
482			`assign ls_tag_adr = { ls_adr_set };`
483			`assign ls_wayX_adr = { ls_adr_set, ls_adr_word };`
484			`assign ls_way0_we = ls_wayX_we & ~ls_way;`
485			`assign ls_way1_we = ls_wayX_we & ls_way;`
486
487			assign ls_wayX_store[`WAY_DAT_RNG] = fml_rdat;
488			assign ls_wayX_store[`WAY_VALID_RNG] = 4'b1111;
489
490
491			`//----------------------------------------------------------------------------`
492			`// LS (Load and Store) Engine`
493			`//----------------------------------------------------------------------------`
494			`parameter l_idle = 0;`
495			`parameter l_fill = 1;`
496			`parameter l_spill = 2;`
497			`parameter l_waitdone = 3;`
498
499			`reg [2:0] ls_state;`
500			`assign ls_busy = (ls_state != l_idle) \|\| ls_fill \|\| ls_spill;`
501
502			`// Syncronous part FSM`
503			`always @(posedge clk)`
504			`begin`
505			`if (reset) begin`
506			`ls_state <= l_idle;`
507			`ls_adr_word <= 0;`
508			`fml_wr <= 0;`
509			`fml_rd <= 0;`
510			`end else begin`
511			`fml_wnext2 <= fml_wnext;`
512
513			`case (ls_state)`
514			`l_idle: begin`
515			`ls_adr_word <= 0;`
516
517			`if (ls_spill) begin`
518			`ls_state <= l_spill;`
519			`ls_adr_word <= ls_adr_word + 1;`
520			`end`
521			`if (ls_fill) begin`
522			`ls_state <= l_fill;`
523			`fml_rd <= 1;`
524			`end`
525			`end`
526			`l_spill: begin`
527			`ls_adr_word <= ls_adr_word + 1;`
528
529			`if (ls_adr_word == 3) begin`
530			`ls_state <= l_waitdone;`
531			`fml_wr <= 1;`
532			`end`
533			`end`
534			`l_waitdone: begin`
535			`ls_adr_word <= 0;`
536
537			`if (fml_done) begin`
538			`ls_state <= l_idle;`
539			`fml_wr <= 0;`
540			`end`
541			`end`
542			`l_fill: begin`
543			`if (fml_done)`
544			`fml_rd <= 0;`
545
546			`if (~fml_rempty)`
547			`ls_adr_word <= ls_adr_word + 1;`
548
549			`if (~fml_rempty & (ls_adr_word == 3))`
550			`ls_state <= l_idle;`
551			`end`
552			`endcase`
553			`end`
554			`end`
555
556			`always @(*)`
557			`begin`
558			`fml_wnext <= 0;`
559			`fml_rnext <= 0;`
560			`ls_tag_we <= 0;`
561			`ls_tag_store <= ls_tag_load;`
562			`ls_wayX_we <= 0;`
563
564			`case (ls_state)`
565			`l_idle: begin`
566			`if (ls_spill) begin`
567			`fml_wnext <= 1;`
568			`end`
569			`end`
570			`l_spill: begin`
571			`fml_wnext <= 1;`
572			`end`
573			`l_waitdone: begin`
574			`if (ls_way == 0)`
575			ls_tag_store[`TAG_LINE_DIRTY0_RNG] <= 0;
576			`else`
577			ls_tag_store[`TAG_LINE_DIRTY1_RNG] <= 0;
578
579			`if (fml_done)`
580			`ls_tag_we <= 1;`
581			`end`
582			`l_fill: begin`
583			`if (ls_way == 0) begin`
584			ls_tag_store[`TAG_LINE_DIRTY0_RNG] <= 0;
585			ls_tag_store[`TAG_LINE_TAG0_RNG] <= ls_adr_tag;
586			`end else begin`
587			ls_tag_store[`TAG_LINE_DIRTY1_RNG] <= 0;
588			ls_tag_store[`TAG_LINE_TAG1_RNG] <= ls_adr_tag;
589			`end`
590
591			`if (~fml_rempty) begin`
592			`ls_wayX_we <= 1;`
593			`fml_rnext <= 1;`
594			`end`
595
596			`if (~fml_rempty & (ls_adr_word == 3))`
597			`ls_tag_we <= 1;`
598			`end`
599			`endcase`
600			`end`
601
602			`always @(posedge clk)`
603			`begin`
604			`if (ls_fill)`
605			`$display ("At time %t WB_DDR fill cacheline: TAG = %h, SET = %h)", $time, ls_adr_tag, ls_adr_set);`
606
607			`if (ls_spill)`
608			`$display ("At time %t WB_DDR spill cacheline: TAG = %h, SET = %h)", $time, ls_adr_tag, ls_adr_set);`
609			`end`
610
611
612			`endmodule`