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[/] [m1_core/] [trunk/] [hdl/] [rtl/] [wb_ps2_keyboard/] [ps2_translation_table.v] - Blame information for rev 54

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ps2_translation_table.v                                     ////
////                                                              ////
////  This file is part of the "ps2" project                      ////
////  http://www.opencores.org/cores/ps2/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2003/07/01 12:34:03  mihad
// Added an option to use constant values instead of RAM
// in the translation table.
//
// Revision 1.3  2003/06/02 17:13:22  simons
// resetall keyword removed. ifdef moved to a separated line.
//
// Revision 1.2  2002/04/09 13:21:15  mihad
// Added mouse interface and everything for its handling, cleaned up some unused code
//
// Revision 1.1.1.1  2002/02/18 16:16:56  mihad
// Initial project import - working
//
//
 
`include "ps2_defines.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module ps2_translation_table
(
    reset_i,
    clock_i,
    translate_i,
    code_i,
    code_o,
    address_i,
    data_i,
    we_i,
    re_i,
    data_o,
    rx_data_ready_i,
    rx_translated_data_ready_o,
    rx_read_i,
    rx_read_o,
    rx_released_i
) ;
 
input reset_i,
      clock_i,
      translate_i ;
 
input  [7:0] code_i ;
output [7:0] code_o ;
input  [7:0] address_i ;
input  [7:0] data_i ;
input        we_i,
             re_i ;
 
output [7:0] data_o ;
 
input rx_data_ready_i,
      rx_read_i ;
 
output rx_translated_data_ready_o ;
output rx_read_o ;
 
input  rx_released_i ;
 
wire translation_table_write_enable  = we_i && (!translate_i || !rx_data_ready_i) ;
wire [7:0] translation_table_address = ((we_i || re_i) && (!rx_data_ready_i || !translate_i)) ? address_i : code_i ;
wire translation_table_enable        = we_i || re_i || (translate_i && rx_data_ready_i) ;
 
reg rx_translated_data_ready ;
always@(posedge clock_i or posedge reset_i)
begin
    if ( reset_i )
        rx_translated_data_ready <= #1 1'b0 ;
    else if ( rx_read_i || !translate_i )
        rx_translated_data_ready <= #1 1'b0 ;
    else
        rx_translated_data_ready <= #1 rx_data_ready_i ;
end
 
`ifdef PS2_RAMB4
    `define PS2_RAM_SELECTED
 
    wire [7:0] ram_out ;
    RAMB4_S8
             `ifdef SIM
             #("ignore",
               `PS2_TRANSLATION_TABLE_31_0,
               `PS2_TRANSLATION_TABLE_63_32,
               `PS2_TRANSLATION_TABLE_95_64,
               `PS2_TRANSLATION_TABLE_127_96,
               `PS2_TRANSLATION_TABLE_159_128,
               `PS2_TRANSLATION_TABLE_191_160,
               `PS2_TRANSLATION_TABLE_223_192,
               `PS2_TRANSLATION_TABLE_255_224)
              `endif
    ps2_ram
    (
        .DO   (ram_out),
        .ADDR ({1'b0, translation_table_address}),
        .DI   (data_i),
        .EN   (translation_table_enable),
        .CLK  (clock_i),
        .WE   (translation_table_write_enable),
        .RST  (reset_i)
    ) ;
 
`endif
 
`ifdef PS2_CONSTANTS_ROM
    `define PS2_RAM_SELECTED
 
    reg [32 * 8 - 1:0] ps2_32byte_constant ;
    reg [7:0] ram_out ;
 
    always@(translation_table_address)
    begin
        case (translation_table_address[7:5])
            3'b000:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_31_0    ;
            3'b001:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_63_32   ;
            3'b010:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_95_64   ;
            3'b011:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_127_96  ;
            3'b100:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_159_128 ;
            3'b101:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_191_160 ;
            3'b110:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_223_192 ;
            3'b111:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_255_224 ;
        endcase
    end
 
    always@(posedge clock_i or posedge reset_i)
    begin
        if ( reset_i )
            ram_out <= #1 8'h0 ;
        else if ( translation_table_enable )
        begin:get_dat_out
            reg [7:0] bit_num ;
 
            bit_num = translation_table_address[4:0] << 3 ;
 
            repeat(8)
            begin
                ram_out[bit_num % 8] <= #1 ps2_32byte_constant[bit_num] ;
                bit_num = bit_num + 1'b1 ;
            end
        end
    end
 
`endif
 
`ifdef PS2_RAM_SELECTED
`else
    `define PS2_RAM_SELECTED
 
    reg [7:0] ps2_ram [0:255] ;
    reg [7:0] ram_out ;
 
    always@(posedge clock_i or posedge reset_i)
    begin
        if ( reset_i )
            ram_out <= #1 8'h0 ;
        else if ( translation_table_enable )
            ram_out <= #1 ps2_ram[translation_table_address] ;
    end
 
    always@(posedge clock_i)
    begin
        if ( translation_table_write_enable )
            ps2_ram[translation_table_address] <= #1 data_i ;
    end
 
    // synopsys translate_off
    initial
    begin:ps2_ram_init
        integer i ;
        reg [255:0] temp_init_val ;
 
        temp_init_val = `PS2_TRANSLATION_TABLE_31_0 ;
 
        for ( i = 0 ; i <= 31 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_63_32 ;
 
        for ( i = 32 ; i <= 63 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_95_64 ;
 
        for ( i = 64 ; i <= 95 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_127_96 ;
 
        for ( i = 96 ; i <= 127 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_159_128 ;
 
        for ( i = 128 ; i <= 159 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_191_160 ;
 
        for ( i = 160 ; i <= 191 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_223_192 ;
 
        for ( i = 192 ; i <= 223 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_255_224 ;
 
        for ( i = 224 ; i <= 255 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
    end
 
    // synopsys translate_on
 
`endif
 
assign data_o = ram_out ;
assign code_o = translate_i ? {(rx_released_i | ram_out[7]), ram_out[6:0]} : code_i ;
assign rx_translated_data_ready_o = translate_i ? rx_translated_data_ready : rx_data_ready_i ;
assign rx_read_o = rx_read_i ;
 
`undef PS2_RAM_SELECTED
 
endmodule //ps2_translation_table

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[/] [m1_core/] [trunk/] [hdl/] [rtl/] [wb_ps2_keyboard/] [ps2_translation_table.v] - Blame information for rev 54

Line No.	Rev	Author	Line
1	34	fafa1971	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ps2_translation_table.v ////`
4			`//// ////`
5			`//// This file is part of the "ps2" project ////`
6			`//// http://www.opencores.org/cores/ps2/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.txt ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`// Revision 1.4 2003/07/01 12:34:03 mihad`
47			`// Added an option to use constant values instead of RAM`
48			`// in the translation table.`
49			`//`
50			`// Revision 1.3 2003/06/02 17:13:22 simons`
51			`// resetall keyword removed. ifdef moved to a separated line.`
52			`//`
53			`// Revision 1.2 2002/04/09 13:21:15 mihad`
54			`// Added mouse interface and everything for its handling, cleaned up some unused code`
55			`//`
56			`// Revision 1.1.1.1 2002/02/18 16:16:56 mihad`
57			`// Initial project import - working`
58			`//`
59			`//`
60
61			`include "ps2_defines.v"
62
63			`// synopsys translate_off`
64			`include "timescale.v"
65			`// synopsys translate_on`
66
67			`module ps2_translation_table`
68			`(`
69			`reset_i,`
70			`clock_i,`
71			`translate_i,`
72			`code_i,`
73			`code_o,`
74			`address_i,`
75			`data_i,`
76			`we_i,`
77			`re_i,`
78			`data_o,`
79			`rx_data_ready_i,`
80			`rx_translated_data_ready_o,`
81			`rx_read_i,`
82			`rx_read_o,`
83			`rx_released_i`
84			`) ;`
85
86			`input reset_i,`
87			`clock_i,`
88			`translate_i ;`
89
90			`input [7:0] code_i ;`
91			`output [7:0] code_o ;`
92			`input [7:0] address_i ;`
93			`input [7:0] data_i ;`
94			`input we_i,`
95			`re_i ;`
96
97			`output [7:0] data_o ;`
98
99			`input rx_data_ready_i,`
100			`rx_read_i ;`
101
102			`output rx_translated_data_ready_o ;`
103			`output rx_read_o ;`
104
105			`input rx_released_i ;`
106
107			`wire translation_table_write_enable = we_i && (!translate_i \|\| !rx_data_ready_i) ;`
108			`wire [7:0] translation_table_address = ((we_i \|\| re_i) && (!rx_data_ready_i \|\| !translate_i)) ? address_i : code_i ;`
109			`wire translation_table_enable = we_i \|\| re_i \|\| (translate_i && rx_data_ready_i) ;`
110
111			`reg rx_translated_data_ready ;`
112			`always@(posedge clock_i or posedge reset_i)`
113			`begin`
114			`if ( reset_i )`
115			`rx_translated_data_ready <= #1 1'b0 ;`
116			`else if ( rx_read_i \|\| !translate_i )`
117			`rx_translated_data_ready <= #1 1'b0 ;`
118			`else`
119			`rx_translated_data_ready <= #1 rx_data_ready_i ;`
120			`end`
121
122			`ifdef PS2_RAMB4
123			`define PS2_RAM_SELECTED
124
125			`wire [7:0] ram_out ;`
126			`RAMB4_S8`
127			`ifdef SIM
128			`#("ignore",`
129			`PS2_TRANSLATION_TABLE_31_0,
130			`PS2_TRANSLATION_TABLE_63_32,
131			`PS2_TRANSLATION_TABLE_95_64,
132			`PS2_TRANSLATION_TABLE_127_96,
133			`PS2_TRANSLATION_TABLE_159_128,
134			`PS2_TRANSLATION_TABLE_191_160,
135			`PS2_TRANSLATION_TABLE_223_192,
136			`PS2_TRANSLATION_TABLE_255_224)
137			`endif
138			`ps2_ram`
139			`(`
140			`.DO (ram_out),`
141			`.ADDR ({1'b0, translation_table_address}),`
142			`.DI (data_i),`
143			`.EN (translation_table_enable),`
144			`.CLK (clock_i),`
145			`.WE (translation_table_write_enable),`
146			`.RST (reset_i)`
147			`) ;`
148
149			`endif
150
151			`ifdef PS2_CONSTANTS_ROM
152			`define PS2_RAM_SELECTED
153
154			`reg [32 * 8 - 1:0] ps2_32byte_constant ;`
155			`reg [7:0] ram_out ;`
156
157			`always@(translation_table_address)`
158			`begin`
159			`case (translation_table_address[7:5])`
160			3'b000:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_31_0 ;
161			3'b001:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_63_32 ;
162			3'b010:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_95_64 ;
163			3'b011:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_127_96 ;
164			3'b100:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_159_128 ;
165			3'b101:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_191_160 ;
166			3'b110:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_223_192 ;
167			3'b111:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_255_224 ;
168			`endcase`
169			`end`
170
171			`always@(posedge clock_i or posedge reset_i)`
172			`begin`
173			`if ( reset_i )`
174			`ram_out <= #1 8'h0 ;`
175			`else if ( translation_table_enable )`
176			`begin:get_dat_out`
177			`reg [7:0] bit_num ;`
178
179			`bit_num = translation_table_address[4:0] << 3 ;`
180
181			`repeat(8)`
182			`begin`
183			`ram_out[bit_num % 8] <= #1 ps2_32byte_constant[bit_num] ;`
184			`bit_num = bit_num + 1'b1 ;`
185			`end`
186			`end`
187			`end`
188
189			`endif
190
191			`ifdef PS2_RAM_SELECTED
192			`else
193			`define PS2_RAM_SELECTED
194
195			`reg [7:0] ps2_ram [0:255] ;`
196			`reg [7:0] ram_out ;`
197
198			`always@(posedge clock_i or posedge reset_i)`
199			`begin`
200			`if ( reset_i )`
201			`ram_out <= #1 8'h0 ;`
202			`else if ( translation_table_enable )`
203			`ram_out <= #1 ps2_ram[translation_table_address] ;`
204			`end`
205
206			`always@(posedge clock_i)`
207			`begin`
208			`if ( translation_table_write_enable )`
209			`ps2_ram[translation_table_address] <= #1 data_i ;`
210			`end`
211
212			`// synopsys translate_off`
213			`initial`
214			`begin:ps2_ram_init`
215			`integer i ;`
216			`reg [255:0] temp_init_val ;`
217
218			temp_init_val = `PS2_TRANSLATION_TABLE_31_0 ;
219
220			`for ( i = 0 ; i <= 31 ; i = i + 1 )`
221			`begin`
222			`ps2_ram[i] = temp_init_val[7:0] ;`
223			`temp_init_val = temp_init_val >> 8 ;`
224			`end`
225
226			temp_init_val = `PS2_TRANSLATION_TABLE_63_32 ;
227
228			`for ( i = 32 ; i <= 63 ; i = i + 1 )`
229			`begin`
230			`ps2_ram[i] = temp_init_val[7:0] ;`
231			`temp_init_val = temp_init_val >> 8 ;`
232			`end`
233
234			temp_init_val = `PS2_TRANSLATION_TABLE_95_64 ;
235
236			`for ( i = 64 ; i <= 95 ; i = i + 1 )`
237			`begin`
238			`ps2_ram[i] = temp_init_val[7:0] ;`
239			`temp_init_val = temp_init_val >> 8 ;`
240			`end`
241
242			temp_init_val = `PS2_TRANSLATION_TABLE_127_96 ;
243
244			`for ( i = 96 ; i <= 127 ; i = i + 1 )`
245			`begin`
246			`ps2_ram[i] = temp_init_val[7:0] ;`
247			`temp_init_val = temp_init_val >> 8 ;`
248			`end`
249
250			temp_init_val = `PS2_TRANSLATION_TABLE_159_128 ;
251
252			`for ( i = 128 ; i <= 159 ; i = i + 1 )`
253			`begin`
254			`ps2_ram[i] = temp_init_val[7:0] ;`
255			`temp_init_val = temp_init_val >> 8 ;`
256			`end`
257
258			temp_init_val = `PS2_TRANSLATION_TABLE_191_160 ;
259
260			`for ( i = 160 ; i <= 191 ; i = i + 1 )`
261			`begin`
262			`ps2_ram[i] = temp_init_val[7:0] ;`
263			`temp_init_val = temp_init_val >> 8 ;`
264			`end`
265
266			temp_init_val = `PS2_TRANSLATION_TABLE_223_192 ;
267
268			`for ( i = 192 ; i <= 223 ; i = i + 1 )`
269			`begin`
270			`ps2_ram[i] = temp_init_val[7:0] ;`
271			`temp_init_val = temp_init_val >> 8 ;`
272			`end`
273
274			temp_init_val = `PS2_TRANSLATION_TABLE_255_224 ;
275
276			`for ( i = 224 ; i <= 255 ; i = i + 1 )`
277			`begin`
278			`ps2_ram[i] = temp_init_val[7:0] ;`
279			`temp_init_val = temp_init_val >> 8 ;`
280			`end`
281			`end`
282
283			`// synopsys translate_on`
284
285			`endif
286
287			`assign data_o = ram_out ;`
288			`assign code_o = translate_i ? {(rx_released_i \| ram_out[7]), ram_out[6:0]} : code_i ;`
289			`assign rx_translated_data_ready_o = translate_i ? rx_translated_data_ready : rx_data_ready_i ;`
290			`assign rx_read_o = rx_read_i ;`
291
292			`undef PS2_RAM_SELECTED
293
294			`endmodule //ps2_translation_table`