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1 9 ns32kum
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6
// Filename: ADDR_UNIT.v
7 16 ns32kum
// Version:  1.2 bug fix
8
// History:  1.1 bug fix release of 7 October 2015
9
//           1.0 first release of 30 Mai 2015
10
// Date:     8 March 2016
11 9 ns32kum
//
12
// Copyright (C) 2015 Udo Moeller
13
// 
14
// This source file may be used and distributed without 
15
// restriction provided that this copyright statement is not 
16
// removed from the file and that any derivative work contains 
17
// the original copyright notice and the associated disclaimer.
18
// 
19
// This source file is free software; you can redistribute it 
20
// and/or modify it under the terms of the GNU Lesser General 
21
// Public License as published by the Free Software Foundation;
22
// either version 2.1 of the License, or (at your option) any 
23
// later version. 
24
// 
25
// This source is distributed in the hope that it will be 
26
// useful, but WITHOUT ANY WARRANTY; without even the implied 
27
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
28
// PURPOSE. See the GNU Lesser General Public License for more 
29
// details. 
30
// 
31
// You should have received a copy of the GNU Lesser General 
32
// Public License along with this source; if not, download it 
33
// from http://www.opencores.org/lgpl.shtml 
34
// 
35
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
36
//
37
//      Modules contained in this file:
38
//      ADDR_UNIT       generates data access addresses and controls data cache operation
39
//
40 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
41 9 ns32kum
 
42 11 ns32kum
module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
43
                                   DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
44 12 ns32kum
                                   NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL,
45
                                   QWATWO );
46 9 ns32kum
 
47
        input                   BCLK,BRESET;
48
        input                   READ,WRITE,LDEA;
49
        input                   NEWACC;
50
        input                   CLRMSW,POST,FULLACC;
51
        input    [1:0]   SRC2SEL;
52
        input    [3:0]   INDEX;
53
        input    [1:0]   ASIZE;
54
        input   [31:0]   SRC1,SRC2;
55
        input    [1:0]   BWD;
56
        input   [31:0]   DISP;
57
        input   [31:0]   PC_ARCHI,PC_ICACHE;
58
        input                   DISP_OK;
59
        input                   IO_READY;
60
        input    [5:0]   ACC_STAT;       // Feedback from data cache about the running access
61
        input    [1:0]   MMU_UPDATE;
62
        input    [2:0]   IC_TEX;
63
        input    [1:0]   ABO_STAT;
64
        input                   ADIVAR;
65
        input                   RWVAL_1;        // special access for RDVAL + WRVAL
66
        input                   OP_RMW;
67
        input                   PHASE_17;
68
        input                   NO_TRAP;
69
        input                   FPU_TRAP;
70
 
71
        output                  READ_OUT,WRITE_OUT,ZTEST,RMW;
72
        output  [31:0]   VADR;
73
        output  [31:0]   ADDR;
74
        output   [1:0]   SIZE;
75
        output   [3:0]   PACKET;
76
        output                  ACC_DONE;
77
        output                  ABORT;
78
        output                  REG_OUT;
79
        output   [2:0]   BITSEL;
80 12 ns32kum
        output  reg             QWATWO;
81 9 ns32kum
 
82
        reg             [31:0]   VADR;
83
        reg                             READ_OUT,write_reg,ZTEST,RMW;
84
        reg              [1:0]   SIZE;
85
        reg              [3:0]   PACKET;
86
        reg              [2:0]   BITSEL;
87
        reg             [31:0]   source2;
88
        reg             [31:0]   index_val;
89
        reg             [31:0]   vadr_reg;
90
        reg             [31:0]   ea_reg;
91
        reg             [31:0]   tos_offset;
92
        reg             [31:0]   icache_adr;
93
        reg             [31:0]   sign_ext_src1;
94
        reg        [31:12]      pg_areg;
95
        reg                             reg_out_i,next_reg;
96
        reg                             ld_ea_reg;
97
        reg                             acc_run,acc_ende,acc_step;
98
        reg                             qwa_flag;
99
        reg                             no_done;
100
        reg                             frueh_ok;
101
        reg                             io_rdy;
102
        reg                             ABORT;
103
        reg              [1:0]   tex_feld;
104
        reg              [2:0]   u_ddt;
105
        reg                             pg_op;
106
        reg                             do_wr;
107
 
108
        wire                    acc_ok,acc_err,io_acc;
109
        wire                    acc_pass;
110
        wire                    ca_hit;
111
        wire    [31:0]   reg_adder;
112
        wire    [31:0]   next_vadr;
113
        wire    [31:0]   final_addr;
114
        wire    [31:0]   pg_addr;
115
        wire     [1:0]   inc_pack;
116
        wire     [3:0]   index_sel;
117
        wire                    ld_ea_i;
118
        wire                    ea_ok;
119
        wire                    qw_align;
120
        wire                    init_acc;
121
        wire                    in_page;
122
        wire                    all_ok;
123
        wire                    fa_out;
124
        wire                    pg_test;
125
 
126
        // ++++++++++++++++++++  Decoding ACC_STAT from data cache  ++++++++++++++++++++++++++++
127
 
128
        // ACC_STAT[5:0] : CA_HIT, IO_ACC, PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK
129
 
130
        assign ca_hit   = ACC_STAT[5];
131
        assign io_acc   = ACC_STAT[4];
132
        assign acc_err  = ACC_STAT[3] | ACC_STAT[1];    // Abort or Protection Error
133
        assign acc_ok   = ACC_STAT[0] & ~pg_op;
134
        assign acc_pass = ACC_STAT[0] & ZTEST;
135
 
136
        always @(posedge BCLK) ABORT <= acc_err;        // Signal to Steuerung - only a pulse
137
 
138 11 ns32kum
        always @(posedge BCLK) if (acc_err) tex_feld <= ACC_STAT[3] ? 2'b11 : {~ACC_STAT[2],ACC_STAT[2]};       // for MSR
139 9 ns32kum
        always @(posedge BCLK) if (acc_err) u_ddt        <= {RMW,ABO_STAT[1],(WRITE_OUT | ZTEST)};
140
 
141
        // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
142
 
143
        always @(SRC2SEL or CLRMSW or SRC2 or PC_ARCHI or ea_reg)
144
                case (SRC2SEL)
145 11 ns32kum
                  2'b00 : source2 = {(CLRMSW ? 16'h0000 : SRC2[31:16]),SRC2[15:0]};      // base reg, External Addressing with MOD 
146 9 ns32kum
                  2'b01 : source2 = PC_ARCHI;           // PC relative
147
                  2'b10 : source2 = 32'h0;                      // Absolute Addressing
148
                  2'b11 : source2 = ea_reg;                     // REUSE : 2. TOS
149
                endcase
150
 
151 11 ns32kum
        assign index_sel = POST ? 4'h0 : INDEX; // Alternative application of Index for POST Adder : POP from Stack
152 9 ns32kum
 
153
        always @(BWD or SRC1)
154
                casex (BWD)
155
                        2'b00 : sign_ext_src1 = {{24{SRC1[7]}}, SRC1[7:0]};              // Byte
156
                        2'b01 : sign_ext_src1 = {{16{SRC1[15]}},SRC1[15:0]};     // Word
157
                  default : sign_ext_src1 = SRC1;
158
                endcase
159
 
160
        always @(index_sel or sign_ext_src1 or SRC1)
161
                casex (index_sel)
162 16 ns32kum
                  4'b1_0xx : index_val = sign_ext_src1; // f�r CASE
163 9 ns32kum
                  4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
164
                  4'b0_100 : index_val = SRC1;
165
                  4'b0_101 : index_val = {SRC1[30:0],1'b0};
166
                  4'b0_110 : index_val = {SRC1[29:0],2'b00};
167
                  4'b0_111 : index_val = {SRC1[28:0],3'b000};
168
                  default  : index_val = 32'h0;
169
                endcase
170
 
171
        assign reg_adder = source2 + index_val; // SRC2 allows simple MOV with SRC1
172
 
173
        assign final_addr = reg_adder + DISP;   // That's the final access address
174
 
175 11 ns32kum
        always @(posedge BCLK) if (LDEA && (index_sel[3:2] == 2'b11)) BITSEL <= SRC1[2:0];       // for Bit Opcodes in I_PFAD
176 9 ns32kum
 
177
        always @(INDEX) // SP POP Operation & String Backward
178
                case (INDEX[2:0])
179
                  3'b000 : tos_offset = 32'h0000_0001;
180
                  3'b001 : tos_offset = 32'h0000_0002;
181
                  3'b010 : tos_offset = 32'h0000_0004;
182
                  3'b011 : tos_offset = 32'h0000_0008;
183
                  3'b100 : tos_offset = 32'hFFFF_FFFF;
184
                  3'b101 : tos_offset = 32'hFFFF_FFFE;
185
                  3'b110 : tos_offset = 32'hFFFF_FFFC;
186
                  3'b111 : tos_offset = 32'hFFFF_FFF8;
187
                endcase
188
 
189
        always @(posedge BCLK or negedge BRESET)
190
                if (!BRESET) ld_ea_reg <= 1'b0;
191
                  else ld_ea_reg <= (LDEA | ld_ea_reg) & ~DISP_OK;
192
 
193
        assign ld_ea_i = (LDEA | ld_ea_reg) & DISP_OK;
194
 
195
        assign ea_ok = (READ | WRITE | LDEA | ld_ea_reg) & ~FULLACC & DISP_OK;
196
 
197
        always @(posedge BCLK) icache_adr <= PC_ICACHE;
198
 
199
        // Memory for the calculated address for reuse and Register for POST modified addresses : 
200
        always @(posedge BCLK)
201
                if (ld_ea_i)
202
                  begin
203
                        casex ({MMU_UPDATE[1],INDEX[0],POST})
204
                          3'b10x : ea_reg <= MMU_UPDATE[0] ? vadr_reg : icache_adr;              // TEAR
205
                          3'b11x : ea_reg <= MMU_UPDATE[0] ?
206
                                                                  {24'h0000_00,3'b101,          u_ddt,                   tex_feld}              // MSR
207
                                                                : {24'h0000_00,3'b100,IC_TEX[2],ABO_STAT[0],1'b0,IC_TEX[1:0]};    // only READ from ICACHE
208
                          3'b0x1 : ea_reg <= source2 + tos_offset ;
209
                          3'b0x0 : ea_reg <= final_addr;
210
                        endcase
211
                  end
212
 
213
        assign ADDR = ea_reg;   // used for ADDR opcode and TOS Addressing
214
 
215
        // This pulse stores all parameters of access
216 11 ns32kum
        assign init_acc = ((FULLACC ? (NEWACC & acc_ende) : acc_ende) | ~acc_run) & DISP_OK & (READ | WRITE) & ~ABORT & NO_TRAP;
217 9 ns32kum
 
218
        assign fa_out = init_acc | ADIVAR;      // special case for LMR IVAR,...
219
 
220
        always @(fa_out or acc_ok or final_addr or qw_align or pg_op or pg_areg or vadr_reg or next_vadr)
221
                casex ({fa_out,acc_ok})
222
                  2'b1x : VADR = {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};
223
                  2'b00 : VADR = pg_op ? {pg_areg,12'h0} : vadr_reg;
224
                  2'b01 : VADR = next_vadr;
225
                endcase
226
 
227
        always @(posedge BCLK)
228
                if (init_acc) vadr_reg <= {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};
229
                  else
230
                        if (pg_op && ZTEST && acc_err) vadr_reg <= {pg_areg,12'h0};     // for TEAR !
231
                          else
232
                                if (acc_ok) vadr_reg <= next_vadr;
233
 
234
        assign next_vadr = qwa_flag ? {vadr_reg[31:3],3'b000} : ({vadr_reg[31:2],2'b00} + 32'h0000_0004);
235
 
236
        // Logic for Page border WRITE Test
237
        assign pg_addr = final_addr + {29'h0,(ASIZE[1] & ASIZE[0]),ASIZE[1],(ASIZE[1] | ASIZE[0])};
238
        always @(posedge BCLK) if (init_acc) pg_areg <= pg_addr[31:12];
239
        assign pg_test = (final_addr[12] != pg_addr[12]) & ~OP_RMW;     // At RMW no Test necessary
240
 
241
        always @(posedge BCLK or negedge BRESET)
242
                if (!BRESET) pg_op <= 1'b0;
243
                  else
244
                        pg_op <= init_acc ? (WRITE & ~RWVAL_1 & pg_test) : (pg_op & ~acc_pass & ~acc_err);
245
 
246
        always @(posedge BCLK) do_wr <= pg_op & ZTEST & acc_pass;       // All ok, Page exists => continue
247
 
248
        always @(posedge BCLK or negedge BRESET)
249
                if (!BRESET) READ_OUT <= 1'b0;
250
                  else
251
                        READ_OUT  <= init_acc ? (READ & ~RWVAL_1) : (READ_OUT  & ~acc_ende & ~acc_err);
252
 
253
        always @(posedge BCLK or negedge BRESET)
254
                if (!BRESET) write_reg <= 1'b0;
255
                  else
256 11 ns32kum
                        write_reg <= (init_acc ? (WRITE & ~RWVAL_1 & ~pg_test) : (write_reg & ~acc_ende & ~acc_err & ~FPU_TRAP)) | do_wr;
257 9 ns32kum
 
258
        assign WRITE_OUT = write_reg & ~FPU_TRAP;
259
 
260
        // Special case for RDVAL and WRVAL
261
        always @(posedge BCLK or negedge BRESET)
262
                if (!BRESET) ZTEST <= 1'b0;
263
                  else
264 11 ns32kum
                        ZTEST <= pg_op ? (~ZTEST | (~acc_pass & ~acc_err)) : (init_acc ? RWVAL_1  : (ZTEST  & ~acc_ende & ~acc_err));
265 9 ns32kum
 
266
        always @(posedge BCLK or negedge BRESET)
267
                if (!BRESET) RMW <= 1'b0;
268
                  else
269
                        RMW <= init_acc ? (OP_RMW & PHASE_17) : (RMW  & ~acc_ende & ~acc_err);
270
 
271
        // Special case : first MSD access by aligned QWORD READ
272
        assign qw_align = (final_addr[2:0] == 3'b000) & READ & (ASIZE == 2'b11);
273
 
274
        always @(posedge BCLK) if (init_acc) qwa_flag <= qw_align;
275
 
276
        always @(posedge BCLK or negedge BRESET)        // central flag that shows the ADDR_UNIT is busy
277
                if (!BRESET) acc_run <= 1'b0;
278
                  else
279
                        acc_run <= init_acc | (acc_run & ~acc_ende & ~acc_err & ~FPU_TRAP);
280
 
281
        always @(posedge BCLK) if (init_acc) SIZE <= ASIZE;
282
 
283
        assign inc_pack = (PACKET[1:0] == 2'b00) ? 2'b10 : {(SIZE[1] ^ SIZE[0]),(SIZE[1] & SIZE[0])};
284
 
285 11 ns32kum
        // Counter for data packets 1 to 3 : special case aligned QWORD : only 2 packets. Additionally start address in bits 1 und 0.
286 9 ns32kum
        // special coding (00) -> [01] -> (10) , [01] optional by QWORD and (10) shows always the end
287
        always @(posedge BCLK)
288
                if (init_acc) PACKET <= {2'b00,final_addr[1:0]};
289
                  else
290
                        if (acc_ok) PACKET <= PACKET + {inc_pack,2'b00};
291
 
292
        // This signal is the End signal for the ADDR_UNIT internally.
293
        always @(SIZE or PACKET or acc_ok)
294
                casex ({SIZE,PACKET[3],PACKET[1:0]})
295
                  5'b00_x_xx : acc_ende = acc_ok;       // Byte
296
                  5'b01_0_0x : acc_ende = acc_ok;       // Word         1 packet
297
                  5'b01_0_10 : acc_ende = acc_ok;       //                      1 packet
298
                  5'b01_1_xx : acc_ende = acc_ok;       //                      2 packets
299
                  5'b10_0_00 : acc_ende = acc_ok;       // DWord        1 packet
300
                  5'b10_1_xx : acc_ende = acc_ok;       //                      2 packets
301
                  5'b11_1_xx : acc_ende = acc_ok;       // QWord        at least 2 packets
302
                  default    : acc_ende = 1'b0;
303
                endcase
304
 
305 11 ns32kum
        assign in_page = (vadr_reg[11:3] != 9'h1FF);    // Access inside a page ? During WRITE address is increasing : 1. LSD 2. MSD
306 9 ns32kum
 
307
        always @(SIZE or vadr_reg or in_page or PACKET)
308
                casex (SIZE)
309
                  2'b01 : frueh_ok = (vadr_reg[3:2] != 2'b11);  //Word
310
                  2'b10 : frueh_ok = (vadr_reg[3:2] != 2'b11);  //DWord
311 11 ns32kum
                  2'b11 : frueh_ok = (PACKET[1:0] == 2'b00) ? (~vadr_reg[3] | ~vadr_reg[2]) : ((PACKET[3:2] == 2'b01) & (vadr_reg[3:2] != 2'b11));
312 9 ns32kum
                default : frueh_ok = 1'b1;                                              // Byte don't case
313
                endcase
314
 
315
        assign all_ok = SIZE[1] ? (PACKET[1:0] == 2'b00) : (PACKET[1:0] != 2'b11);        // for DWord : Word
316
 
317 11 ns32kum
        always @(SIZE or READ_OUT or frueh_ok or PACKET or all_ok or io_acc or acc_ok or qwa_flag or io_rdy or ca_hit)
318 9 ns32kum
                casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
319
                  7'b00_xxxx_x : acc_step = acc_ok;     // Byte, all ok
320
                //
321
                  7'b01_xxxx_1 : acc_step = acc_ok;     // Word :       aligned access , only 1 packet
322
                  7'b01_1x1x_0 : acc_step = acc_ok;     //                      READ must wait for all data
323 16 ns32kum
                  7'b01_0x1x_0 : acc_step = acc_ok;     //                      WRITE Adr. is not perfect and waits for last packet
324
                  7'b01_0100_0 : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet if not io_acc
325 9 ns32kum
                //
326
                  7'b10_xxxx_1 : acc_step = acc_ok;     // DWord :      aligned access , only 1 packet
327
                  7'b10_1x1x_0 : acc_step = acc_ok;     //                      READ must wait for all data
328 16 ns32kum
                  7'b10_0x1x_0 : acc_step = acc_ok;     //                      WRITE Adr. is not perfect and waits for last packet
329
                  7'b10_0100_0 : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet if not io_acc
330 9 ns32kum
                // fast QWord READ : there would be a 2. acc_step if not ~PACK... 
331
                  7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
332
                  7'b11_0x1x_x : acc_step = acc_ok;
333 11 ns32kum
                  7'b11_0100_x : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet if not io_acc
334 9 ns32kum
                  default      : acc_step = 1'b0;
335
                endcase
336
 
337
        // There is a 2. acc_step if packet (10) - this must be suppressed
338
        always @(posedge BCLK or negedge BRESET)
339
                if (!BRESET) no_done <= 1'b0;
340
                  else no_done <= (~acc_ende & acc_step) | (no_done & ~(acc_run & acc_ende));
341
 
342
        // The final DONE Multiplexer
343
        assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
344
 
345 12 ns32kum
        // Bugfix of 7.October 2015
346
        always @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done;
347
 
348 11 ns32kum
        always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);
349 9 ns32kum
 
350
        always @(posedge BCLK) io_rdy  <= IO_READY & (WRITE_OUT | READ_OUT);
351
 
352
        always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
353
        assign REG_OUT = reg_out_i | next_reg;
354
 
355
endmodule

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