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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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//
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// Filename: ADDR_UNIT.v
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// Version:  1.0
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// Date:     30 May 2015
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//
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// Copyright (C) 2015 Udo Moeller
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// 
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// This source file may be used and distributed without 
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// restriction provided that this copyright statement is not 
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// removed from the file and that any derivative work contains 
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// the original copyright notice and the associated disclaimer.
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// 
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// This source file is free software; you can redistribute it 
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// and/or modify it under the terms of the GNU Lesser General 
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any 
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// later version. 
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// 
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// This source is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied 
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
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// PURPOSE. See the GNU Lesser General Public License for more 
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// details. 
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// 
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// You should have received a copy of the GNU Lesser General 
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// Public License along with this source; if not, download it 
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// from http://www.opencores.org/lgpl.shtml 
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// 
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//      Modules contained in this file:
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//      ADDR_UNIT       generates data access addresses and controls data cache operation
37
//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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40
module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL,
41
                                   DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1,
42
                                   NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT
43
 
44
        input                   BCLK,BRESET;
45
        input                   READ,WRITE,LDEA;
46
        input                   NEWACC;
47
        input                   CLRMSW,POST,FULLACC;
48
        input    [1:0]   SRC2SEL;
49
        input    [3:0]   INDEX;
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        input    [1:0]   ASIZE;
51
        input   [31:0]   SRC1,SRC2;
52
        input    [1:0]   BWD;
53
        input   [31:0]   DISP;
54
        input   [31:0]   PC_ARCHI,PC_ICACHE;
55
        input                   DISP_OK;
56
        input                   IO_READY;
57
        input    [5:0]   ACC_STAT;       // Feedback from data cache about the running access
58
        input    [1:0]   MMU_UPDATE;
59
        input    [2:0]   IC_TEX;
60
        input    [1:0]   ABO_STAT;
61
        input                   ADIVAR;
62
        input                   RWVAL_1;        // special access for RDVAL + WRVAL
63
        input                   OP_RMW;
64
        input                   PHASE_17;
65
        input                   NO_TRAP;
66
        input                   FPU_TRAP;
67
 
68
        output                  READ_OUT,WRITE_OUT,ZTEST,RMW;
69
        output  [31:0]   VADR;
70
        output  [31:0]   ADDR;
71
        output   [1:0]   SIZE;
72
        output   [3:0]   PACKET;
73
        output                  ACC_DONE;
74
        output                  ABORT;
75
        output                  REG_OUT;
76
        output   [2:0]   BITSEL;
77
 
78
        reg             [31:0]   VADR;
79
        reg                             READ_OUT,write_reg,ZTEST,RMW;
80
        reg              [1:0]   SIZE;
81
        reg              [3:0]   PACKET;
82
        reg              [2:0]   BITSEL;
83
        reg             [31:0]   source2;
84
        reg             [31:0]   index_val;
85
        reg             [31:0]   vadr_reg;
86
        reg             [31:0]   ea_reg;
87
        reg             [31:0]   tos_offset;
88
        reg             [31:0]   icache_adr;
89
        reg             [31:0]   sign_ext_src1;
90
        reg        [31:12]      pg_areg;
91
        reg                             reg_out_i,next_reg;
92
        reg                             ld_ea_reg;
93
        reg                             acc_run,acc_ende,acc_step;
94
        reg                             qwa_flag;
95
        reg                             no_done;
96
        reg                             frueh_ok;
97
        reg                             io_rdy;
98
        reg                             ABORT;
99
        reg              [1:0]   tex_feld;
100
        reg              [2:0]   u_ddt;
101
        reg                             pg_op;
102
        reg                             do_wr;
103
 
104
        wire                    acc_ok,acc_err,io_acc;
105
        wire                    acc_pass;
106
        wire                    ca_hit;
107
        wire    [31:0]   reg_adder;
108
        wire    [31:0]   next_vadr;
109
        wire    [31:0]   final_addr;
110
        wire    [31:0]   pg_addr;
111
        wire     [1:0]   inc_pack;
112
        wire     [3:0]   index_sel;
113
        wire                    ld_ea_i;
114
        wire                    ea_ok;
115
        wire                    qw_align;
116
        wire                    init_acc;
117
        wire                    in_page;
118
        wire                    all_ok;
119
        wire                    fa_out;
120
        wire                    pg_test;
121
 
122
        // ++++++++++++++++++++  Decoding ACC_STAT from data cache  ++++++++++++++++++++++++++++
123
 
124
        // ACC_STAT[5:0] : CA_HIT, IO_ACC, PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK
125
 
126
        assign ca_hit   = ACC_STAT[5];
127
        assign io_acc   = ACC_STAT[4];
128
        assign acc_err  = ACC_STAT[3] | ACC_STAT[1];    // Abort or Protection Error
129
        assign acc_ok   = ACC_STAT[0] & ~pg_op;
130
        assign acc_pass = ACC_STAT[0] & ZTEST;
131
 
132
        always @(posedge BCLK) ABORT <= acc_err;        // Signal to Steuerung - only a pulse
133
 
134
        always @(posedge BCLK) if (acc_err) tex_feld <= ACC_STAT[3] ? 2'b11 : {~ACC_STAT[2],ACC_STAT[2]};       /
135
        always @(posedge BCLK) if (acc_err) u_ddt        <= {RMW,ABO_STAT[1],(WRITE_OUT | ZTEST)};
136
 
137
        // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
138
 
139
        always @(SRC2SEL or CLRMSW or SRC2 or PC_ARCHI or ea_reg)
140
                case (SRC2SEL)
141
                  2'b00 : source2 = {(CLRMSW ? 16'h0000 : SRC2[31:16]),SRC2[15:0]};      // base reg, External Addressi
142
                  2'b01 : source2 = PC_ARCHI;           // PC relative
143
                  2'b10 : source2 = 32'h0;                      // Absolute Addressing
144
                  2'b11 : source2 = ea_reg;                     // REUSE : 2. TOS
145
                endcase
146
 
147
        assign index_sel = POST ? 4'h0 : INDEX; // Alternative application of Index for POST Adder : POP fr
148
 
149
        always @(BWD or SRC1)
150
                casex (BWD)
151
                        2'b00 : sign_ext_src1 = {{24{SRC1[7]}}, SRC1[7:0]};              // Byte
152
                        2'b01 : sign_ext_src1 = {{16{SRC1[15]}},SRC1[15:0]};     // Word
153
                  default : sign_ext_src1 = SRC1;
154
                endcase
155
 
156
        always @(index_sel or sign_ext_src1 or SRC1)
157
                casex (index_sel)
158
                  4'b1_0xx : index_val = sign_ext_src1; // für CASE
159
                  4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
160
                  4'b0_100 : index_val = SRC1;
161
                  4'b0_101 : index_val = {SRC1[30:0],1'b0};
162
                  4'b0_110 : index_val = {SRC1[29:0],2'b00};
163
                  4'b0_111 : index_val = {SRC1[28:0],3'b000};
164
                  default  : index_val = 32'h0;
165
                endcase
166
 
167
        assign reg_adder = source2 + index_val; // SRC2 allows simple MOV with SRC1
168
 
169
        assign final_addr = reg_adder + DISP;   // That's the final access address
170
 
171
        always @(posedge BCLK) if (LDEA && (index_sel[3:2] == 2'b11)) BITSEL <= SRC1[2:0];       // for Bit Opcod
172
 
173
        always @(INDEX) // SP POP Operation & String Backward
174
                case (INDEX[2:0])
175
                  3'b000 : tos_offset = 32'h0000_0001;
176
                  3'b001 : tos_offset = 32'h0000_0002;
177
                  3'b010 : tos_offset = 32'h0000_0004;
178
                  3'b011 : tos_offset = 32'h0000_0008;
179
                  3'b100 : tos_offset = 32'hFFFF_FFFF;
180
                  3'b101 : tos_offset = 32'hFFFF_FFFE;
181
                  3'b110 : tos_offset = 32'hFFFF_FFFC;
182
                  3'b111 : tos_offset = 32'hFFFF_FFF8;
183
                endcase
184
 
185
        always @(posedge BCLK or negedge BRESET)
186
                if (!BRESET) ld_ea_reg <= 1'b0;
187
                  else ld_ea_reg <= (LDEA | ld_ea_reg) & ~DISP_OK;
188
 
189
        assign ld_ea_i = (LDEA | ld_ea_reg) & DISP_OK;
190
 
191
        assign ea_ok = (READ | WRITE | LDEA | ld_ea_reg) & ~FULLACC & DISP_OK;
192
 
193
        always @(posedge BCLK) icache_adr <= PC_ICACHE;
194
 
195
        // Memory for the calculated address for reuse and Register for POST modified addresses : 
196
        always @(posedge BCLK)
197
                if (ld_ea_i)
198
                  begin
199
                        casex ({MMU_UPDATE[1],INDEX[0],POST})
200
                          3'b10x : ea_reg <= MMU_UPDATE[0] ? vadr_reg : icache_adr;              // TEAR
201
                          3'b11x : ea_reg <= MMU_UPDATE[0] ?
202
                                                                  {24'h0000_00,3'b101,          u_ddt,                   tex_feld}              // MSR
203
                                                                : {24'h0000_00,3'b100,IC_TEX[2],ABO_STAT[0],1'b0,IC_TEX[1:0]};    // only READ from ICACHE
204
                          3'b0x1 : ea_reg <= source2 + tos_offset ;
205
                          3'b0x0 : ea_reg <= final_addr;
206
                        endcase
207
                  end
208
 
209
        assign ADDR = ea_reg;   // used for ADDR opcode and TOS Addressing
210
 
211
        // This pulse stores all parameters of access
212
        assign init_acc = ((FULLACC ? (NEWACC & acc_ende) : acc_ende) | ~acc_run) & DISP_OK & (READ | WRITE
213
 
214
        assign fa_out = init_acc | ADIVAR;      // special case for LMR IVAR,...
215
 
216
        always @(fa_out or acc_ok or final_addr or qw_align or pg_op or pg_areg or vadr_reg or next_vadr)
217
                casex ({fa_out,acc_ok})
218
                  2'b1x : VADR = {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};
219
                  2'b00 : VADR = pg_op ? {pg_areg,12'h0} : vadr_reg;
220
                  2'b01 : VADR = next_vadr;
221
                endcase
222
 
223
        always @(posedge BCLK)
224
                if (init_acc) vadr_reg <= {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};
225
                  else
226
                        if (pg_op && ZTEST && acc_err) vadr_reg <= {pg_areg,12'h0};     // for TEAR !
227
                          else
228
                                if (acc_ok) vadr_reg <= next_vadr;
229
 
230
        assign next_vadr = qwa_flag ? {vadr_reg[31:3],3'b000} : ({vadr_reg[31:2],2'b00} + 32'h0000_0004);
231
 
232
        // Logic for Page border WRITE Test
233
        assign pg_addr = final_addr + {29'h0,(ASIZE[1] & ASIZE[0]),ASIZE[1],(ASIZE[1] | ASIZE[0])};
234
        always @(posedge BCLK) if (init_acc) pg_areg <= pg_addr[31:12];
235
        assign pg_test = (final_addr[12] != pg_addr[12]) & ~OP_RMW;     // At RMW no Test necessary
236
 
237
        always @(posedge BCLK or negedge BRESET)
238
                if (!BRESET) pg_op <= 1'b0;
239
                  else
240
                        pg_op <= init_acc ? (WRITE & ~RWVAL_1 & pg_test) : (pg_op & ~acc_pass & ~acc_err);
241
 
242
        always @(posedge BCLK) do_wr <= pg_op & ZTEST & acc_pass;       // All ok, Page exists => continue
243
 
244
        always @(posedge BCLK or negedge BRESET)
245
                if (!BRESET) READ_OUT <= 1'b0;
246
                  else
247
                        READ_OUT  <= init_acc ? (READ & ~RWVAL_1) : (READ_OUT  & ~acc_ende & ~acc_err);
248
 
249
        always @(posedge BCLK or negedge BRESET)
250
                if (!BRESET) write_reg <= 1'b0;
251
                  else
252
                        write_reg <= (init_acc ? (WRITE & ~RWVAL_1 & ~pg_test) : (write_reg & ~acc_ende & ~acc_err & ~FPU
253
 
254
        assign WRITE_OUT = write_reg & ~FPU_TRAP;
255
 
256
        // Special case for RDVAL and WRVAL
257
        always @(posedge BCLK or negedge BRESET)
258
                if (!BRESET) ZTEST <= 1'b0;
259
                  else
260
                        ZTEST <= pg_op ? (~ZTEST | (~acc_pass & ~acc_err)) : (init_acc ? RWVAL_1  : (ZTEST  & ~acc_ende &
261
 
262
        always @(posedge BCLK or negedge BRESET)
263
                if (!BRESET) RMW <= 1'b0;
264
                  else
265
                        RMW <= init_acc ? (OP_RMW & PHASE_17) : (RMW  & ~acc_ende & ~acc_err);
266
 
267
        // Special case : first MSD access by aligned QWORD READ
268
        assign qw_align = (final_addr[2:0] == 3'b000) & READ & (ASIZE == 2'b11);
269
 
270
        always @(posedge BCLK) if (init_acc) qwa_flag <= qw_align;
271
 
272
        always @(posedge BCLK or negedge BRESET)        // central flag that shows the ADDR_UNIT is busy
273
                if (!BRESET) acc_run <= 1'b0;
274
                  else
275
                        acc_run <= init_acc | (acc_run & ~acc_ende & ~acc_err & ~FPU_TRAP);
276
 
277
        always @(posedge BCLK) if (init_acc) SIZE <= ASIZE;
278
 
279
        assign inc_pack = (PACKET[1:0] == 2'b00) ? 2'b10 : {(SIZE[1] ^ SIZE[0]),(SIZE[1] & SIZE[0])};
280
 
281
        // Counter for data packets 1 to 3 : special case aligned QWORD : only 2 packets. Additionally star
282
        // special coding (00) -> [01] -> (10) , [01] optional by QWORD and (10) shows always the end
283
        always @(posedge BCLK)
284
                if (init_acc) PACKET <= {2'b00,final_addr[1:0]};
285
                  else
286
                        if (acc_ok) PACKET <= PACKET + {inc_pack,2'b00};
287
 
288
        // This signal is the End signal for the ADDR_UNIT internally.
289
        always @(SIZE or PACKET or acc_ok)
290
                casex ({SIZE,PACKET[3],PACKET[1:0]})
291
                  5'b00_x_xx : acc_ende = acc_ok;       // Byte
292
                  5'b01_0_0x : acc_ende = acc_ok;       // Word         1 packet
293
                  5'b01_0_10 : acc_ende = acc_ok;       //                      1 packet
294
                  5'b01_1_xx : acc_ende = acc_ok;       //                      2 packets
295
                  5'b10_0_00 : acc_ende = acc_ok;       // DWord        1 packet
296
                  5'b10_1_xx : acc_ende = acc_ok;       //                      2 packets
297
                  5'b11_1_xx : acc_ende = acc_ok;       // QWord        at least 2 packets
298
                  default    : acc_ende = 1'b0;
299
                endcase
300
 
301
        assign in_page = (vadr_reg[11:3] != 9'h1FF);    // Access inside a page ? During WRITE address is incr
302
 
303
        always @(SIZE or vadr_reg or in_page or PACKET)
304
                casex (SIZE)
305
                  2'b01 : frueh_ok = (vadr_reg[3:2] != 2'b11);  //Word
306
                  2'b10 : frueh_ok = (vadr_reg[3:2] != 2'b11);  //DWord
307
                  2'b11 : frueh_ok = (PACKET[1:0] == 2'b00) ? (~vadr_reg[3] | ~vadr_reg[2]) : ((PACKET[3:2] == 2'b
308
                default : frueh_ok = 1'b1;                                              // Byte don't case
309
                endcase
310
 
311
        assign all_ok = SIZE[1] ? (PACKET[1:0] == 2'b00) : (PACKET[1:0] != 2'b11);        // for DWord : Word
312
 
313
        always @(SIZE or READ_OUT or frueh_ok or PACKET or all_ok or io_acc or acc_ok or qwa_flag or io_rdy
314
                casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
315
                  7'b00_xxxx_x : acc_step = acc_ok;     // Byte, all ok
316
                //
317
                  7'b01_xxxx_1 : acc_step = acc_ok;     // Word :       aligned access , only 1 packet
318
                  7'b01_1x1x_0 : acc_step = acc_ok;     //                      READ must wait for all data
319
                  7'b01_001x_0 : acc_step = acc_ok;     //                      WRITE Adr. ist not perfect and waits for last packet
320
                  7'b01_01xx_0 : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet
321
                //
322
                  7'b10_xxxx_1 : acc_step = acc_ok;     // DWord :      aligned access , only 1 packet
323
                  7'b10_1x1x_0 : acc_step = acc_ok;     //                      READ must wait for all data
324
                  7'b10_001x_0 : acc_step = acc_ok;     //                      WRITE Adr. ist not perfect and waits for last packet
325
                  7'b10_01xx_0 : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet
326
                // fast QWord READ : there would be a 2. acc_step if not ~PACK... 
327
                  7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
328
                  7'b11_0x1x_x : acc_step = acc_ok;
329
                  7'b11_0100_x : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet if not io_a
330
                  default      : acc_step = 1'b0;
331
                endcase
332
 
333
        // There is a 2. acc_step if packet (10) - this must be suppressed
334
        always @(posedge BCLK or negedge BRESET)
335
                if (!BRESET) no_done <= 1'b0;
336
                  else no_done <= (~acc_ende & acc_step) | (no_done & ~(acc_run & acc_ende));
337
 
338
        // The final DONE Multiplexer
339
        assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
340
 
341
        always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok)
342
 
343
        always @(posedge BCLK) io_rdy  <= IO_READY & (WRITE_OUT | READ_OUT);
344
 
345
        always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
346
        assign REG_OUT = reg_out_i | next_reg;
347
 
348
endmodule

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