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1 9 ns32kum
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6
// Filename: ALIGNER.v
7
// Version:  1.0
8
// Date:     30 May 2015
9
//
10
// Copyright (C) 2015 Udo Moeller
11
// 
12
// This source file may be used and distributed without 
13
// restriction provided that this copyright statement is not 
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// removed from the file and that any derivative work contains 
15
// the original copyright notice and the associated disclaimer.
16
// 
17
// This source file is free software; you can redistribute it 
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// and/or modify it under the terms of the GNU Lesser General 
19
// Public License as published by the Free Software Foundation;
20
// either version 2.1 of the License, or (at your option) any 
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// later version. 
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// 
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// This source is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied 
25
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
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// PURPOSE. See the GNU Lesser General Public License for more 
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// details. 
28
// 
29
// You should have received a copy of the GNU Lesser General 
30
// Public License along with this source; if not, download it 
31
// from http://www.opencores.org/lgpl.shtml 
32
// 
33
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
34
//
35
//      Modules contained in this file:
36
//      1. WR_ALINGER   alignes write data to cache and external devices
37
//      2. RD_ALINGER   alignes read data for the data path
38
//
39 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
40 9 ns32kum
 
41 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
42 9 ns32kum
//
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//      1. WR_ALINGER   alignes write data to cache and external devices
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//
45 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
46 9 ns32kum
module WR_ALIGNER ( PACKET, DP_Q, SIZE, WRDATA, ENBYTE );
47
 
48
        input    [3:0]   PACKET; // [3:2] Paketnumber , [1:0] Startaddress
49
        input   [63:0]   DP_Q;
50
        input    [1:0]   SIZE;
51
        output  [31:0]   WRDATA;
52
        output   [3:0]   ENBYTE;
53
 
54
        reg              [3:0]   ENBYTE;
55
        reg              [7:0]   dbyte0,dbyte1,dbyte2,dbyte3;
56
        wire                    switch;
57
 
58
// Data packet  [ B7 ],[ B6 ],[ B5 ],[ B4 ],[ B3 ],[ B2 ],[ B1 ],[ B0 ]
59
// Address , i.e. 001 : one DWORD
60
// gives  2 packets : 1. packet             [-B6-----B5-----B4-]
61
// 2. packet, Address + 4                                                                [-B7-]
62
// Addresse , i.e. 010 : one QWORD
63
// gives  3 packets : 1. packet             [-B1-----B0-]
64
// 2. packet, Address + 4                                       [-B5-----B4-----B3-----B2-]
65
// 3. packet, Address + 8                                                                 [-B7-----B6-]
66
 
67
//      SIZE PACKET ADR : Outputbus 
68
//              00      00      00               x  x  x B4
69
//              00      00      01               x  x B4  x
70
//              00      00      10               x B4  x  x
71
//              00      00      11              B4  x  x  x
72
 
73
//              01      00      00               x  x B5 B4
74
//              01      00      01               x B5 B4  x
75
//              01      00      10              B5 B4  x  x
76
//              01      00      11              B4  x  x  x
77
//              01      10      11               x  x  x B5
78
 
79
//              10      00      00              B7 B6 B5 B4
80
//              10      00      01              B6 B5 B4  x
81
//              10      10      01               x  x  x B7
82
//              10      00      10              B5 B4  x  x
83
//              10      10      10               x  x B7 B6
84
//              10      00      11              B4  x  x  x
85
//              10      10      11               x B7 B6 B5
86
 
87
//              11      00      00              B3 B2 B1 B0
88
//              11      10      00              B7 B6 B5 B4
89
//              11      00      01              B2 B1 B0  x
90
//              11      01      01              B6 B5 B4 B3
91
//              11      10      01               x  x  x B7
92
//              11      00      10              B1 B0  x  x
93
//              11      01      10              B5 B4 B3 B2
94
//              11      10      10               x  x B7 B6
95
//              11      00      11              B0  x  x  x
96
//              11      01      11              B4 B3 B2 B1
97
//              11      10      11               x B7 B6 B5
98
 
99
        assign switch = (SIZE == 2'b11) & (PACKET[3:2] == 2'b00);
100
 
101
        always @(DP_Q or switch or PACKET)
102
                case (PACKET[1:0])
103
                  2'b00 : dbyte0 =    switch ?   DP_Q[7:0] : DP_Q[39:32];
104
                  2'b01 : dbyte0 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
105
                  2'b10 : dbyte0 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];
106
                  2'b11 : dbyte0 = PACKET[3] ? DP_Q[47:40] :  DP_Q[15:8];
107
                endcase
108
 
109
        always @(DP_Q or switch or PACKET)
110
                case (PACKET[1:0])
111
                  2'b00 : dbyte1 =    switch ?  DP_Q[15:8] : DP_Q[47:40];
112
                  2'b01 : dbyte1 =    switch ?   DP_Q[7:0] : DP_Q[39:32];
113
                  2'b10 : dbyte1 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
114
                  2'b11 : dbyte1 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];
115
                endcase
116
 
117
        always @(DP_Q or switch or PACKET)
118
                case (PACKET[1:0])
119
                  2'b00 : dbyte2 =    switch ? DP_Q[23:16] : DP_Q[55:48];
120
                  2'b01 : dbyte2 =    switch ?  DP_Q[15:8] : DP_Q[47:40];
121
                  2'b10 : dbyte2 =    switch ?   DP_Q[7:0] : DP_Q[39:32];
122
                  2'b11 : dbyte2 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
123
                endcase
124
 
125
        always @(DP_Q or switch or PACKET)
126
                case (PACKET[1:0])
127
                  2'b00 : dbyte3 =    switch ? DP_Q[31:24] : DP_Q[63:56];
128
                  2'b01 : dbyte3 =    switch ? DP_Q[23:16] : DP_Q[55:48];
129
                  2'b10 : dbyte3 =    switch ?  DP_Q[15:8] : DP_Q[47:40];
130
                  2'b11 : dbyte3 =    switch ?   DP_Q[7:0] : DP_Q[39:32];
131
                endcase
132
 
133
        assign WRDATA = {dbyte3,dbyte2,dbyte1,dbyte0};
134
 
135
        always @(SIZE or PACKET)
136
                casex ({SIZE,PACKET})
137
                  6'b00_xx_00 : ENBYTE = 4'b0001;       // BYTE
138
                  6'b00_xx_01 : ENBYTE = 4'b0010;
139
                  6'b00_xx_10 : ENBYTE = 4'b0100;
140
                  6'b00_xx_11 : ENBYTE = 4'b1000;
141
                 //
142
                  6'b01_xx_00 : ENBYTE = 4'b0011;       // WORD
143
                  6'b01_xx_01 : ENBYTE = 4'b0110;
144
                  6'b01_xx_10 : ENBYTE = 4'b1100;
145
                  6'b01_0x_11 : ENBYTE = 4'b1000;
146
                  6'b01_1x_11 : ENBYTE = 4'b0001;
147
                 //
148
                  6'b11_xx_00 : ENBYTE = 4'b1111;       // QWORD
149
                  6'b11_00_01 : ENBYTE = 4'b1110;
150
                  6'b11_01_01 : ENBYTE = 4'b1111;
151
                  6'b11_1x_01 : ENBYTE = 4'b0001;
152
                  6'b11_00_10 : ENBYTE = 4'b1100;
153
                  6'b11_01_10 : ENBYTE = 4'b1111;
154
                  6'b11_1x_10 : ENBYTE = 4'b0011;
155
                  6'b11_00_11 : ENBYTE = 4'b1000;
156
                  6'b11_01_11 : ENBYTE = 4'b1111;
157
                  6'b11_1x_11 : ENBYTE = 4'b0111;
158
                 //     
159
                  6'b10_xx_00 : ENBYTE = 4'b1111;       // DWORD
160
                  6'b10_0x_01 : ENBYTE = 4'b1110;
161
                  6'b10_1x_01 : ENBYTE = 4'b0001;
162
                  6'b10_0x_10 : ENBYTE = 4'b1100;
163
                  6'b10_1x_10 : ENBYTE = 4'b0011;
164
                  6'b10_0x_11 : ENBYTE = 4'b1000;
165
                  6'b10_1x_11 : ENBYTE = 4'b0111;
166
                endcase
167
 
168
endmodule
169
 
170 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
171 9 ns32kum
//
172
//      2. RD_ALINGER   alignes read data for the data path
173
//
174 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
175 9 ns32kum
module RD_ALIGNER ( BCLK, ACC_OK, PACKET, SIZE, REG_OUT, RDDATA, CA_HIT, DP_DI, AUX_QW );
176
 
177
        input                   BCLK;
178
        input                   ACC_OK;
179
        input    [3:0]   PACKET; // [3:2] Paketnumber , [1:0] Startaddress
180
        input    [1:0]   SIZE;
181
        input                   REG_OUT;
182
        input   [31:0]   RDDATA;
183
        input                   CA_HIT;
184
 
185
        output  [31:0]   DP_DI;
186
        output  reg             AUX_QW;
187
 
188
        reg              [6:0]   enable;
189
        reg              [7:0]   dreg_0,dreg_1,dreg_2,dreg_3,dreg_4,dreg_5,dreg_6;
190
        reg              [7:0]   out_0,out_1,out_2,out_3;
191
 
192
// RD_ALIGNER principal working : 10 is last packet , 01 is packet in between
193
 
194
// Not aligned QWORD  : ADR[1:0] = 3 i.e.
195
// Bytes to datapath  : . - . - 4 - 4
196
// Bytes from memory  : 1 - 4 - 3 - .
197
// ACC_DONE                       :     _______/----\__
198
//      + 1 cycle                                       ____/--
199 11 ns32kum
// at the end 2 cycles lost. ACC_DONE informs the Op-Dec that data is available and sent one clock cycle later
200 9 ns32kum
// the LSD of QWORD access. (ACC_DONE -> REG_OUT is happening in ADDR_UNIT.)
201
//
202
// SIZE PACKET ADR :    Output data                                      ACC_OK
203
//              00      --      00               x  x  x B0             Byte                            1
204
//              00      --      01               x  x  x B1                                                     1
205
//              00      --      10               x  x  x B2                                                     1
206
//              00      --      11               x  x  x B3                                                     1
207
 
208
//              01      00      00               x  x B1 B0             Word                            1
209
//              01      00      01               x  x B2 B1                                                     1
210
//              01      00      10               x  x B3 B2                                                     1
211
//              01      00      11              B3  x  x  x     -> Reg : R4  -  -  -    0
212
//              01      10      11               x  x B0 R4                                                     1
213
 
214
//              10      00      00              B3 B2 B1 B0             DWORD                           1
215
//              10      00      01              B3 B2 B1  x     -> Reg : R6 R5 R4  -    0
216
//              10      10      01              B0 R6 R5 R4                                                     1
217
//              10      00      10              B3 B2  x  x -> Reg : R5 R4  -  -        0
218
//              10      10      10              B1 B0 R5 R4                                                     1
219
//              10      00      11              B3  x  x  x -> Reg : R4  -  -  -        0
220
//              10      10      11              B2 B1 B0 R4                                                     1
221
 
222
//              11      00      00              B3 B2 B1 B0             QWORD                           1       MSD
223
//              11      01      00              B3 B2 B1 B0             not out of Reg!         0        LSD
224
//              11      00      01              B3 B2 B1  x -> Reg : R2 R1 R0  -        0
225
//              11      01      01              B3 B2 B1 B0 -> Reg : R6 R5 R4 R3        0
226
//              11      10      01              B0 R6 R5 R4                                                     1       MSD
227
//      next cycle:                     R3 R2 R1 R0                                                             LSD
228
//              11      00      10              B3 B2  x  x -> Reg : R1 R0  -  -        0
229
//              11      01      10              B3 B2 B1 B0 -> Reg : R5 R4 R3 R2        0
230
//              11      10      10              B1 B0 R5 R4                                                     1       MSD
231
//      next cycle:                     R3 R2 R1 R0                                                             LSD
232
//              11      00      11              B3  x  x  x -> Reg : R0  -  -  -        0
233
//              11      01      11              B3 B2 B1 B0 -> Reg : R4 R3 R2 R1        0
234
//              11      10      11              B2 B1 B0 R4                                                     1       MSD
235
//      next cycle:                     R3 R2 R1 R0                                                             LSD
236
 
237
// IO_ACCESS QWORD :
238
//              11      00      00              B3 B2 B1 B0 -> Reg : R3 R2 R1 R0        0
239
//              11      01      00              R3 R2 R1 R0 -> Reg : R3 R2 R1 R0        1       MSD
240
//      next cycle:                     R3 R2 R1 R0                                                             LSD
241
 
242
        always @(ACC_OK or SIZE or PACKET)
243
                casex ({ACC_OK,SIZE,PACKET})
244
                  7'b1_xx_0x_00 : enable = 7'b000_1111;
245
                  7'b1_01_0x_11 : enable = 7'b001_0000;
246
                  7'b1_10_0x_01 : enable = 7'b111_0000;
247
                  7'b1_10_0x_10 : enable = 7'b011_0000;
248
                  7'b1_10_0x_11 : enable = 7'b001_0000;
249
                  7'b1_11_00_01 : enable = 7'b000_0111; // QWORD
250
                  7'b1_11_01_01 : enable = 7'b111_1000;
251
                  7'b1_11_00_10 : enable = 7'b000_0011;
252
                  7'b1_11_01_10 : enable = 7'b011_1100;
253
                  7'b1_11_00_11 : enable = 7'b000_0001;
254
                  7'b1_11_01_11 : enable = 7'b001_1110;
255
                  default               : enable = 7'b000_0000;
256
                endcase
257
 
258
// Register for inbetween data: simple multiplexer
259
 
260
        always @(posedge BCLK)
261
                if (enable[0])
262
                        case (PACKET[1:0])
263
                          2'b01 : dreg_0 <= RDDATA[15:8];
264
                          2'b10 : dreg_0 <= RDDATA[23:16];
265
                          2'b11 : dreg_0 <= RDDATA[31:24];
266
                        default : dreg_0 <= RDDATA[7:0];
267
                        endcase
268
 
269
        always @(posedge BCLK)
270
                if (enable[1])
271
                        case (PACKET[1:0])
272
                          2'b01 : dreg_1 <= RDDATA[23:16];
273
                          2'b10 : dreg_1 <= RDDATA[31:24];
274
                          2'b11 : dreg_1 <= RDDATA[7:0];
275
                        default : dreg_1 <= RDDATA[15:8];
276
                        endcase
277
 
278
        always @(posedge BCLK)
279
                if (enable[2])
280
                        case (PACKET[1:0])
281
                          2'b01 : dreg_2 <= RDDATA[31:24];
282
                          2'b10 : dreg_2 <= RDDATA[7:0];
283
                          2'b11 : dreg_2 <= RDDATA[15:8];
284
                        default : dreg_2 <= RDDATA[23:16];
285
                        endcase
286
 
287
        always @(posedge BCLK)
288
                if (enable[3])
289
                        case (PACKET[1:0])
290
                          2'b01 : dreg_3 <= RDDATA[7:0];
291
                          2'b10 : dreg_3 <= RDDATA[15:8];
292
                          2'b11 : dreg_3 <= RDDATA[23:16];
293
                        default : dreg_3 <= RDDATA[31:24];
294
                        endcase
295
 
296
        always @(posedge BCLK)
297
                if (enable[4])
298
                        case (PACKET[1:0])
299
                          2'b01 : dreg_4 <= RDDATA[15:8];
300
                          2'b10 : dreg_4 <= RDDATA[23:16];
301
                          2'b11 : dreg_4 <= RDDATA[31:24];
302
                        default : dreg_4 <= dreg_4;
303
                        endcase
304
 
305
        always @(posedge BCLK) if (enable[5]) dreg_5 <= PACKET[1] ? RDDATA[31:24] : RDDATA[23:16];
306
 
307
        always @(posedge BCLK) if (enable[6]) dreg_6 <= RDDATA[31:24];
308
 
309
        // +++++++++++++++++++++++
310
 
311
        always @(SIZE or PACKET or RDDATA or dreg_0 or dreg_4)
312
                casex ({SIZE,PACKET[3],PACKET[1:0]})
313
                  5'b0x_0_01 : out_0 = RDDATA[15:8];
314
                  5'b0x_0_10 : out_0 = RDDATA[23:16];
315
                  5'b00_0_11 : out_0 = RDDATA[31:24];
316
                  5'b01_1_11 : out_0 = dreg_4;
317
                  5'b1x_1_01 : out_0 = dreg_4;
318
                  5'b1x_1_1x : out_0 = dreg_4;
319
                  default        : out_0 = RDDATA[7:0];
320
                endcase
321
 
322
        always @(SIZE or PACKET or RDDATA or dreg_1 or dreg_5)
323
                casex ({SIZE,PACKET[3],PACKET[1:0]})
324
                  5'b01_0_01 : out_1 = RDDATA[23:16];
325
                  5'b01_0_10 : out_1 = RDDATA[31:24];
326
                  5'bxx_x_11 : out_1 = RDDATA[7:0];
327
                  5'b1x_1_01 : out_1 = dreg_5;
328
                  5'b1x_1_10 : out_1 = dreg_5;
329
                  default        : out_1 = RDDATA[15:8];
330
                endcase
331
 
332
        always @(SIZE or PACKET or RDDATA or dreg_2 or dreg_6)
333
                case ({SIZE[1],PACKET[3],PACKET[1:0]})
334
                  4'b1_1_01 : out_2 = dreg_6;
335
                  4'b1_1_10 : out_2 = RDDATA[7:0];
336
                  4'b1_1_11 : out_2 = RDDATA[15:8];
337
                  default       : out_2 = RDDATA[23:16];
338
                endcase
339
 
340
        always @(SIZE or PACKET or RDDATA or dreg_3)
341
                case ({SIZE[1],PACKET[3],PACKET[1:0]})
342
                  4'b1_1_01 : out_3 = RDDATA[7:0];
343
                  4'b1_1_10 : out_3 = RDDATA[15:8];
344
                  4'b1_1_11 : out_3 = RDDATA[23:16];
345
                  default       : out_3 = RDDATA[31:24];
346
                endcase
347
 
348
        assign DP_DI = REG_OUT ? {dreg_3,dreg_2,dreg_1,dreg_0} : {out_3,out_2,out_1,out_0};
349
 
350
        // ++++++++++++++++ Special case QWord if cache switched off +++++++++++++++++++
351
 
352
        always @(posedge BCLK) AUX_QW <= ACC_OK & ~CA_HIT & (SIZE == 2'b11) & PACKET[3];
353
 
354
endmodule

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