| 1 |
29 |
ns32kum |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 2 |
9 |
ns32kum |
//
|
| 3 |
|
|
// This file is part of the M32632 project
|
| 4 |
|
|
// http://opencores.org/project,m32632
|
| 5 |
|
|
//
|
| 6 |
23 |
ns32kum |
// Filename: ALIGNER.v
|
| 7 |
29 |
ns32kum |
// Version: 3.0
|
| 8 |
23 |
ns32kum |
// History: 1.0 first release of 30 Mai 2015
|
| 9 |
29 |
ns32kum |
// Date: 2 December 2018
|
| 10 |
9 |
ns32kum |
//
|
| 11 |
29 |
ns32kum |
// Copyright (C) 2018 Udo Moeller
|
| 12 |
9 |
ns32kum |
//
|
| 13 |
|
|
// This source file may be used and distributed without
|
| 14 |
|
|
// restriction provided that this copyright statement is not
|
| 15 |
|
|
// removed from the file and that any derivative work contains
|
| 16 |
|
|
// the original copyright notice and the associated disclaimer.
|
| 17 |
|
|
//
|
| 18 |
|
|
// This source file is free software; you can redistribute it
|
| 19 |
|
|
// and/or modify it under the terms of the GNU Lesser General
|
| 20 |
|
|
// Public License as published by the Free Software Foundation;
|
| 21 |
|
|
// either version 2.1 of the License, or (at your option) any
|
| 22 |
|
|
// later version.
|
| 23 |
|
|
//
|
| 24 |
|
|
// This source is distributed in the hope that it will be
|
| 25 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
| 26 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
| 27 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more
|
| 28 |
|
|
// details.
|
| 29 |
|
|
//
|
| 30 |
|
|
// You should have received a copy of the GNU Lesser General
|
| 31 |
|
|
// Public License along with this source; if not, download it
|
| 32 |
|
|
// from http://www.opencores.org/lgpl.shtml
|
| 33 |
|
|
//
|
| 34 |
29 |
ns32kum |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 35 |
9 |
ns32kum |
//
|
| 36 |
|
|
// Modules contained in this file:
|
| 37 |
|
|
// 1. WR_ALINGER alignes write data to cache and external devices
|
| 38 |
|
|
// 2. RD_ALINGER alignes read data for the data path
|
| 39 |
|
|
//
|
| 40 |
11 |
ns32kum |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 41 |
9 |
ns32kum |
|
| 42 |
11 |
ns32kum |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 43 |
9 |
ns32kum |
//
|
| 44 |
|
|
// 1. WR_ALINGER alignes write data to cache and external devices
|
| 45 |
|
|
//
|
| 46 |
11 |
ns32kum |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 47 |
9 |
ns32kum |
module WR_ALIGNER ( PACKET, DP_Q, SIZE, WRDATA, ENBYTE );
|
| 48 |
|
|
|
| 49 |
|
|
input [3:0] PACKET; // [3:2] Paketnumber , [1:0] Startaddress
|
| 50 |
|
|
input [63:0] DP_Q;
|
| 51 |
|
|
input [1:0] SIZE;
|
| 52 |
|
|
output [31:0] WRDATA;
|
| 53 |
|
|
output [3:0] ENBYTE;
|
| 54 |
|
|
|
| 55 |
|
|
reg [3:0] ENBYTE;
|
| 56 |
|
|
reg [7:0] dbyte0,dbyte1,dbyte2,dbyte3;
|
| 57 |
|
|
wire switch;
|
| 58 |
|
|
|
| 59 |
|
|
// Data packet [ B7 ],[ B6 ],[ B5 ],[ B4 ],[ B3 ],[ B2 ],[ B1 ],[ B0 ]
|
| 60 |
|
|
// Address , i.e. 001 : one DWORD
|
| 61 |
|
|
// gives 2 packets : 1. packet [-B6-----B5-----B4-]
|
| 62 |
|
|
// 2. packet, Address + 4 [-B7-]
|
| 63 |
|
|
// Addresse , i.e. 010 : one QWORD
|
| 64 |
|
|
// gives 3 packets : 1. packet [-B1-----B0-]
|
| 65 |
|
|
// 2. packet, Address + 4 [-B5-----B4-----B3-----B2-]
|
| 66 |
|
|
// 3. packet, Address + 8 [-B7-----B6-]
|
| 67 |
|
|
|
| 68 |
|
|
// SIZE PACKET ADR : Outputbus
|
| 69 |
|
|
// 00 00 00 x x x B4
|
| 70 |
|
|
// 00 00 01 x x B4 x
|
| 71 |
|
|
// 00 00 10 x B4 x x
|
| 72 |
|
|
// 00 00 11 B4 x x x
|
| 73 |
|
|
|
| 74 |
|
|
// 01 00 00 x x B5 B4
|
| 75 |
|
|
// 01 00 01 x B5 B4 x
|
| 76 |
|
|
// 01 00 10 B5 B4 x x
|
| 77 |
|
|
// 01 00 11 B4 x x x
|
| 78 |
|
|
// 01 10 11 x x x B5
|
| 79 |
|
|
|
| 80 |
|
|
// 10 00 00 B7 B6 B5 B4
|
| 81 |
|
|
// 10 00 01 B6 B5 B4 x
|
| 82 |
|
|
// 10 10 01 x x x B7
|
| 83 |
|
|
// 10 00 10 B5 B4 x x
|
| 84 |
|
|
// 10 10 10 x x B7 B6
|
| 85 |
|
|
// 10 00 11 B4 x x x
|
| 86 |
|
|
// 10 10 11 x B7 B6 B5
|
| 87 |
|
|
|
| 88 |
|
|
// 11 00 00 B3 B2 B1 B0
|
| 89 |
|
|
// 11 10 00 B7 B6 B5 B4
|
| 90 |
|
|
// 11 00 01 B2 B1 B0 x
|
| 91 |
|
|
// 11 01 01 B6 B5 B4 B3
|
| 92 |
|
|
// 11 10 01 x x x B7
|
| 93 |
|
|
// 11 00 10 B1 B0 x x
|
| 94 |
|
|
// 11 01 10 B5 B4 B3 B2
|
| 95 |
|
|
// 11 10 10 x x B7 B6
|
| 96 |
|
|
// 11 00 11 B0 x x x
|
| 97 |
|
|
// 11 01 11 B4 B3 B2 B1
|
| 98 |
|
|
// 11 10 11 x B7 B6 B5
|
| 99 |
|
|
|
| 100 |
|
|
assign switch = (SIZE == 2'b11) & (PACKET[3:2] == 2'b00);
|
| 101 |
|
|
|
| 102 |
|
|
always @(DP_Q or switch or PACKET)
|
| 103 |
|
|
case (PACKET[1:0])
|
| 104 |
|
|
2'b00 : dbyte0 = switch ? DP_Q[7:0] : DP_Q[39:32];
|
| 105 |
|
|
2'b01 : dbyte0 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
|
| 106 |
|
|
2'b10 : dbyte0 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];
|
| 107 |
|
|
2'b11 : dbyte0 = PACKET[3] ? DP_Q[47:40] : DP_Q[15:8];
|
| 108 |
|
|
endcase
|
| 109 |
|
|
|
| 110 |
|
|
always @(DP_Q or switch or PACKET)
|
| 111 |
|
|
case (PACKET[1:0])
|
| 112 |
|
|
2'b00 : dbyte1 = switch ? DP_Q[15:8] : DP_Q[47:40];
|
| 113 |
|
|
2'b01 : dbyte1 = switch ? DP_Q[7:0] : DP_Q[39:32];
|
| 114 |
|
|
2'b10 : dbyte1 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
|
| 115 |
|
|
2'b11 : dbyte1 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];
|
| 116 |
|
|
endcase
|
| 117 |
|
|
|
| 118 |
|
|
always @(DP_Q or switch or PACKET)
|
| 119 |
|
|
case (PACKET[1:0])
|
| 120 |
|
|
2'b00 : dbyte2 = switch ? DP_Q[23:16] : DP_Q[55:48];
|
| 121 |
|
|
2'b01 : dbyte2 = switch ? DP_Q[15:8] : DP_Q[47:40];
|
| 122 |
|
|
2'b10 : dbyte2 = switch ? DP_Q[7:0] : DP_Q[39:32];
|
| 123 |
|
|
2'b11 : dbyte2 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
|
| 124 |
|
|
endcase
|
| 125 |
|
|
|
| 126 |
|
|
always @(DP_Q or switch or PACKET)
|
| 127 |
|
|
case (PACKET[1:0])
|
| 128 |
|
|
2'b00 : dbyte3 = switch ? DP_Q[31:24] : DP_Q[63:56];
|
| 129 |
|
|
2'b01 : dbyte3 = switch ? DP_Q[23:16] : DP_Q[55:48];
|
| 130 |
|
|
2'b10 : dbyte3 = switch ? DP_Q[15:8] : DP_Q[47:40];
|
| 131 |
|
|
2'b11 : dbyte3 = switch ? DP_Q[7:0] : DP_Q[39:32];
|
| 132 |
|
|
endcase
|
| 133 |
|
|
|
| 134 |
|
|
assign WRDATA = {dbyte3,dbyte2,dbyte1,dbyte0};
|
| 135 |
|
|
|
| 136 |
|
|
always @(SIZE or PACKET)
|
| 137 |
|
|
casex ({SIZE,PACKET})
|
| 138 |
|
|
6'b00_xx_00 : ENBYTE = 4'b0001; // BYTE
|
| 139 |
|
|
6'b00_xx_01 : ENBYTE = 4'b0010;
|
| 140 |
|
|
6'b00_xx_10 : ENBYTE = 4'b0100;
|
| 141 |
|
|
6'b00_xx_11 : ENBYTE = 4'b1000;
|
| 142 |
|
|
//
|
| 143 |
|
|
6'b01_xx_00 : ENBYTE = 4'b0011; // WORD
|
| 144 |
|
|
6'b01_xx_01 : ENBYTE = 4'b0110;
|
| 145 |
|
|
6'b01_xx_10 : ENBYTE = 4'b1100;
|
| 146 |
|
|
6'b01_0x_11 : ENBYTE = 4'b1000;
|
| 147 |
|
|
6'b01_1x_11 : ENBYTE = 4'b0001;
|
| 148 |
|
|
//
|
| 149 |
|
|
6'b11_xx_00 : ENBYTE = 4'b1111; // QWORD
|
| 150 |
|
|
6'b11_00_01 : ENBYTE = 4'b1110;
|
| 151 |
|
|
6'b11_01_01 : ENBYTE = 4'b1111;
|
| 152 |
|
|
6'b11_1x_01 : ENBYTE = 4'b0001;
|
| 153 |
|
|
6'b11_00_10 : ENBYTE = 4'b1100;
|
| 154 |
|
|
6'b11_01_10 : ENBYTE = 4'b1111;
|
| 155 |
|
|
6'b11_1x_10 : ENBYTE = 4'b0011;
|
| 156 |
|
|
6'b11_00_11 : ENBYTE = 4'b1000;
|
| 157 |
|
|
6'b11_01_11 : ENBYTE = 4'b1111;
|
| 158 |
|
|
6'b11_1x_11 : ENBYTE = 4'b0111;
|
| 159 |
|
|
//
|
| 160 |
|
|
6'b10_xx_00 : ENBYTE = 4'b1111; // DWORD
|
| 161 |
|
|
6'b10_0x_01 : ENBYTE = 4'b1110;
|
| 162 |
|
|
6'b10_1x_01 : ENBYTE = 4'b0001;
|
| 163 |
|
|
6'b10_0x_10 : ENBYTE = 4'b1100;
|
| 164 |
|
|
6'b10_1x_10 : ENBYTE = 4'b0011;
|
| 165 |
|
|
6'b10_0x_11 : ENBYTE = 4'b1000;
|
| 166 |
|
|
6'b10_1x_11 : ENBYTE = 4'b0111;
|
| 167 |
|
|
endcase
|
| 168 |
|
|
|
| 169 |
|
|
endmodule
|
| 170 |
|
|
|
| 171 |
11 |
ns32kum |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 172 |
9 |
ns32kum |
//
|
| 173 |
|
|
// 2. RD_ALINGER alignes read data for the data path
|
| 174 |
|
|
//
|
| 175 |
11 |
ns32kum |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 176 |
9 |
ns32kum |
module RD_ALIGNER ( BCLK, ACC_OK, PACKET, SIZE, REG_OUT, RDDATA, CA_HIT, DP_DI, AUX_QW );
|
| 177 |
|
|
|
| 178 |
|
|
input BCLK;
|
| 179 |
|
|
input ACC_OK;
|
| 180 |
|
|
input [3:0] PACKET; // [3:2] Paketnumber , [1:0] Startaddress
|
| 181 |
|
|
input [1:0] SIZE;
|
| 182 |
|
|
input REG_OUT;
|
| 183 |
|
|
input [31:0] RDDATA;
|
| 184 |
|
|
input CA_HIT;
|
| 185 |
|
|
|
| 186 |
|
|
output [31:0] DP_DI;
|
| 187 |
|
|
output reg AUX_QW;
|
| 188 |
|
|
|
| 189 |
|
|
reg [6:0] enable;
|
| 190 |
|
|
reg [7:0] dreg_0,dreg_1,dreg_2,dreg_3,dreg_4,dreg_5,dreg_6;
|
| 191 |
|
|
reg [7:0] out_0,out_1,out_2,out_3;
|
| 192 |
|
|
|
| 193 |
|
|
// RD_ALIGNER principal working : 10 is last packet , 01 is packet in between
|
| 194 |
|
|
|
| 195 |
|
|
// Not aligned QWORD : ADR[1:0] = 3 i.e.
|
| 196 |
|
|
// Bytes to datapath : . - . - 4 - 4
|
| 197 |
|
|
// Bytes from memory : 1 - 4 - 3 - .
|
| 198 |
|
|
// ACC_DONE : _______/----\__
|
| 199 |
|
|
// + 1 cycle ____/--
|
| 200 |
11 |
ns32kum |
// at the end 2 cycles lost. ACC_DONE informs the Op-Dec that data is available and sent one clock cycle later
|
| 201 |
9 |
ns32kum |
// the LSD of QWORD access. (ACC_DONE -> REG_OUT is happening in ADDR_UNIT.)
|
| 202 |
|
|
//
|
| 203 |
|
|
// SIZE PACKET ADR : Output data ACC_OK
|
| 204 |
|
|
// 00 -- 00 x x x B0 Byte 1
|
| 205 |
|
|
// 00 -- 01 x x x B1 1
|
| 206 |
|
|
// 00 -- 10 x x x B2 1
|
| 207 |
|
|
// 00 -- 11 x x x B3 1
|
| 208 |
|
|
|
| 209 |
|
|
// 01 00 00 x x B1 B0 Word 1
|
| 210 |
|
|
// 01 00 01 x x B2 B1 1
|
| 211 |
|
|
// 01 00 10 x x B3 B2 1
|
| 212 |
|
|
// 01 00 11 B3 x x x -> Reg : R4 - - - 0
|
| 213 |
|
|
// 01 10 11 x x B0 R4 1
|
| 214 |
|
|
|
| 215 |
|
|
// 10 00 00 B3 B2 B1 B0 DWORD 1
|
| 216 |
|
|
// 10 00 01 B3 B2 B1 x -> Reg : R6 R5 R4 - 0
|
| 217 |
|
|
// 10 10 01 B0 R6 R5 R4 1
|
| 218 |
|
|
// 10 00 10 B3 B2 x x -> Reg : R5 R4 - - 0
|
| 219 |
|
|
// 10 10 10 B1 B0 R5 R4 1
|
| 220 |
|
|
// 10 00 11 B3 x x x -> Reg : R4 - - - 0
|
| 221 |
|
|
// 10 10 11 B2 B1 B0 R4 1
|
| 222 |
|
|
|
| 223 |
|
|
// 11 00 00 B3 B2 B1 B0 QWORD 1 MSD
|
| 224 |
|
|
// 11 01 00 B3 B2 B1 B0 not out of Reg! 0 LSD
|
| 225 |
|
|
// 11 00 01 B3 B2 B1 x -> Reg : R2 R1 R0 - 0
|
| 226 |
|
|
// 11 01 01 B3 B2 B1 B0 -> Reg : R6 R5 R4 R3 0
|
| 227 |
|
|
// 11 10 01 B0 R6 R5 R4 1 MSD
|
| 228 |
|
|
// next cycle: R3 R2 R1 R0 LSD
|
| 229 |
|
|
// 11 00 10 B3 B2 x x -> Reg : R1 R0 - - 0
|
| 230 |
|
|
// 11 01 10 B3 B2 B1 B0 -> Reg : R5 R4 R3 R2 0
|
| 231 |
|
|
// 11 10 10 B1 B0 R5 R4 1 MSD
|
| 232 |
|
|
// next cycle: R3 R2 R1 R0 LSD
|
| 233 |
|
|
// 11 00 11 B3 x x x -> Reg : R0 - - - 0
|
| 234 |
|
|
// 11 01 11 B3 B2 B1 B0 -> Reg : R4 R3 R2 R1 0
|
| 235 |
|
|
// 11 10 11 B2 B1 B0 R4 1 MSD
|
| 236 |
|
|
// next cycle: R3 R2 R1 R0 LSD
|
| 237 |
|
|
|
| 238 |
|
|
// IO_ACCESS QWORD :
|
| 239 |
|
|
// 11 00 00 B3 B2 B1 B0 -> Reg : R3 R2 R1 R0 0
|
| 240 |
|
|
// 11 01 00 R3 R2 R1 R0 -> Reg : R3 R2 R1 R0 1 MSD
|
| 241 |
|
|
// next cycle: R3 R2 R1 R0 LSD
|
| 242 |
|
|
|
| 243 |
|
|
always @(ACC_OK or SIZE or PACKET)
|
| 244 |
|
|
casex ({ACC_OK,SIZE,PACKET})
|
| 245 |
|
|
7'b1_xx_0x_00 : enable = 7'b000_1111;
|
| 246 |
|
|
7'b1_01_0x_11 : enable = 7'b001_0000;
|
| 247 |
|
|
7'b1_10_0x_01 : enable = 7'b111_0000;
|
| 248 |
|
|
7'b1_10_0x_10 : enable = 7'b011_0000;
|
| 249 |
|
|
7'b1_10_0x_11 : enable = 7'b001_0000;
|
| 250 |
|
|
7'b1_11_00_01 : enable = 7'b000_0111; // QWORD
|
| 251 |
|
|
7'b1_11_01_01 : enable = 7'b111_1000;
|
| 252 |
|
|
7'b1_11_00_10 : enable = 7'b000_0011;
|
| 253 |
|
|
7'b1_11_01_10 : enable = 7'b011_1100;
|
| 254 |
|
|
7'b1_11_00_11 : enable = 7'b000_0001;
|
| 255 |
|
|
7'b1_11_01_11 : enable = 7'b001_1110;
|
| 256 |
|
|
default : enable = 7'b000_0000;
|
| 257 |
|
|
endcase
|
| 258 |
|
|
|
| 259 |
|
|
// Register for inbetween data: simple multiplexer
|
| 260 |
|
|
|
| 261 |
|
|
always @(posedge BCLK)
|
| 262 |
|
|
if (enable[0])
|
| 263 |
|
|
case (PACKET[1:0])
|
| 264 |
|
|
2'b01 : dreg_0 <= RDDATA[15:8];
|
| 265 |
|
|
2'b10 : dreg_0 <= RDDATA[23:16];
|
| 266 |
|
|
2'b11 : dreg_0 <= RDDATA[31:24];
|
| 267 |
|
|
default : dreg_0 <= RDDATA[7:0];
|
| 268 |
|
|
endcase
|
| 269 |
|
|
|
| 270 |
|
|
always @(posedge BCLK)
|
| 271 |
|
|
if (enable[1])
|
| 272 |
|
|
case (PACKET[1:0])
|
| 273 |
|
|
2'b01 : dreg_1 <= RDDATA[23:16];
|
| 274 |
|
|
2'b10 : dreg_1 <= RDDATA[31:24];
|
| 275 |
|
|
2'b11 : dreg_1 <= RDDATA[7:0];
|
| 276 |
|
|
default : dreg_1 <= RDDATA[15:8];
|
| 277 |
|
|
endcase
|
| 278 |
|
|
|
| 279 |
|
|
always @(posedge BCLK)
|
| 280 |
|
|
if (enable[2])
|
| 281 |
|
|
case (PACKET[1:0])
|
| 282 |
|
|
2'b01 : dreg_2 <= RDDATA[31:24];
|
| 283 |
|
|
2'b10 : dreg_2 <= RDDATA[7:0];
|
| 284 |
|
|
2'b11 : dreg_2 <= RDDATA[15:8];
|
| 285 |
|
|
default : dreg_2 <= RDDATA[23:16];
|
| 286 |
|
|
endcase
|
| 287 |
|
|
|
| 288 |
|
|
always @(posedge BCLK)
|
| 289 |
|
|
if (enable[3])
|
| 290 |
|
|
case (PACKET[1:0])
|
| 291 |
|
|
2'b01 : dreg_3 <= RDDATA[7:0];
|
| 292 |
|
|
2'b10 : dreg_3 <= RDDATA[15:8];
|
| 293 |
|
|
2'b11 : dreg_3 <= RDDATA[23:16];
|
| 294 |
|
|
default : dreg_3 <= RDDATA[31:24];
|
| 295 |
|
|
endcase
|
| 296 |
|
|
|
| 297 |
|
|
always @(posedge BCLK)
|
| 298 |
|
|
if (enable[4])
|
| 299 |
|
|
case (PACKET[1:0])
|
| 300 |
|
|
2'b01 : dreg_4 <= RDDATA[15:8];
|
| 301 |
|
|
2'b10 : dreg_4 <= RDDATA[23:16];
|
| 302 |
|
|
2'b11 : dreg_4 <= RDDATA[31:24];
|
| 303 |
|
|
default : dreg_4 <= dreg_4;
|
| 304 |
|
|
endcase
|
| 305 |
|
|
|
| 306 |
|
|
always @(posedge BCLK) if (enable[5]) dreg_5 <= PACKET[1] ? RDDATA[31:24] : RDDATA[23:16];
|
| 307 |
|
|
|
| 308 |
|
|
always @(posedge BCLK) if (enable[6]) dreg_6 <= RDDATA[31:24];
|
| 309 |
|
|
|
| 310 |
|
|
// +++++++++++++++++++++++
|
| 311 |
|
|
|
| 312 |
|
|
always @(SIZE or PACKET or RDDATA or dreg_0 or dreg_4)
|
| 313 |
|
|
casex ({SIZE,PACKET[3],PACKET[1:0]})
|
| 314 |
|
|
5'b0x_0_01 : out_0 = RDDATA[15:8];
|
| 315 |
|
|
5'b0x_0_10 : out_0 = RDDATA[23:16];
|
| 316 |
|
|
5'b00_0_11 : out_0 = RDDATA[31:24];
|
| 317 |
|
|
5'b01_1_11 : out_0 = dreg_4;
|
| 318 |
|
|
5'b1x_1_01 : out_0 = dreg_4;
|
| 319 |
|
|
5'b1x_1_1x : out_0 = dreg_4;
|
| 320 |
|
|
default : out_0 = RDDATA[7:0];
|
| 321 |
|
|
endcase
|
| 322 |
|
|
|
| 323 |
|
|
always @(SIZE or PACKET or RDDATA or dreg_1 or dreg_5)
|
| 324 |
|
|
casex ({SIZE,PACKET[3],PACKET[1:0]})
|
| 325 |
|
|
5'b01_0_01 : out_1 = RDDATA[23:16];
|
| 326 |
|
|
5'b01_0_10 : out_1 = RDDATA[31:24];
|
| 327 |
|
|
5'bxx_x_11 : out_1 = RDDATA[7:0];
|
| 328 |
|
|
5'b1x_1_01 : out_1 = dreg_5;
|
| 329 |
|
|
5'b1x_1_10 : out_1 = dreg_5;
|
| 330 |
|
|
default : out_1 = RDDATA[15:8];
|
| 331 |
|
|
endcase
|
| 332 |
|
|
|
| 333 |
|
|
always @(SIZE or PACKET or RDDATA or dreg_2 or dreg_6)
|
| 334 |
|
|
case ({SIZE[1],PACKET[3],PACKET[1:0]})
|
| 335 |
|
|
4'b1_1_01 : out_2 = dreg_6;
|
| 336 |
|
|
4'b1_1_10 : out_2 = RDDATA[7:0];
|
| 337 |
|
|
4'b1_1_11 : out_2 = RDDATA[15:8];
|
| 338 |
|
|
default : out_2 = RDDATA[23:16];
|
| 339 |
|
|
endcase
|
| 340 |
|
|
|
| 341 |
|
|
always @(SIZE or PACKET or RDDATA or dreg_3)
|
| 342 |
|
|
case ({SIZE[1],PACKET[3],PACKET[1:0]})
|
| 343 |
|
|
4'b1_1_01 : out_3 = RDDATA[7:0];
|
| 344 |
|
|
4'b1_1_10 : out_3 = RDDATA[15:8];
|
| 345 |
|
|
4'b1_1_11 : out_3 = RDDATA[23:16];
|
| 346 |
|
|
default : out_3 = RDDATA[31:24];
|
| 347 |
|
|
endcase
|
| 348 |
|
|
|
| 349 |
|
|
assign DP_DI = REG_OUT ? {dreg_3,dreg_2,dreg_1,dreg_0} : {out_3,out_2,out_1,out_0};
|
| 350 |
|
|
|
| 351 |
|
|
// ++++++++++++++++ Special case QWord if cache switched off +++++++++++++++++++
|
| 352 |
|
|
|
| 353 |
|
|
always @(posedge BCLK) AUX_QW <= ACC_OK & ~CA_HIT & (SIZE == 2'b11) & PACKET[3];
|
| 354 |
|
|
|
| 355 |
|
|
endmodule
|
