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ns32kum |
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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//
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// Filename: ALIGNER.v
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// Version: 1.0
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// Date: 30 May 2015
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//
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// Copyright (C) 2015 Udo Moeller
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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// Modules contained in this file:
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// 1. WR_ALINGER alignes write data to cache and external devices
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// 2. RD_ALINGER alignes read data for the data path
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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// 1. WR_ALINGER alignes write data to cache and external devices
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module WR_ALIGNER ( PACKET, DP_Q, SIZE, WRDATA, ENBYTE );
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input [3:0] PACKET; // [3:2] Paketnumber , [1:0] Startaddress
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input [63:0] DP_Q;
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input [1:0] SIZE;
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output [31:0] WRDATA;
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output [3:0] ENBYTE;
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reg [3:0] ENBYTE;
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reg [7:0] dbyte0,dbyte1,dbyte2,dbyte3;
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wire switch;
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// Data packet [ B7 ],[ B6 ],[ B5 ],[ B4 ],[ B3 ],[ B2 ],[ B1 ],[ B0 ]
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// Address , i.e. 001 : one DWORD
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// gives 2 packets : 1. packet [-B6-----B5-----B4-]
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// 2. packet, Address + 4 [-B7-]
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// Addresse , i.e. 010 : one QWORD
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// gives 3 packets : 1. packet [-B1-----B0-]
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// 2. packet, Address + 4 [-B5-----B4-----B3-----B2-]
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// 3. packet, Address + 8 [-B7-----B6-]
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// SIZE PACKET ADR : Outputbus
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// 00 00 00 x x x B4
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// 00 00 01 x x B4 x
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// 00 00 10 x B4 x x
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// 00 00 11 B4 x x x
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// 01 00 00 x x B5 B4
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// 01 00 01 x B5 B4 x
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// 01 00 10 B5 B4 x x
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// 01 00 11 B4 x x x
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// 01 10 11 x x x B5
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// 10 00 00 B7 B6 B5 B4
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// 10 00 01 B6 B5 B4 x
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// 10 10 01 x x x B7
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// 10 00 10 B5 B4 x x
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// 10 10 10 x x B7 B6
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// 10 00 11 B4 x x x
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// 10 10 11 x B7 B6 B5
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// 11 00 00 B3 B2 B1 B0
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// 11 10 00 B7 B6 B5 B4
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// 11 00 01 B2 B1 B0 x
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// 11 01 01 B6 B5 B4 B3
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// 11 10 01 x x x B7
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// 11 00 10 B1 B0 x x
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// 11 01 10 B5 B4 B3 B2
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// 11 10 10 x x B7 B6
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// 11 00 11 B0 x x x
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// 11 01 11 B4 B3 B2 B1
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// 11 10 11 x B7 B6 B5
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assign switch = (SIZE == 2'b11) & (PACKET[3:2] == 2'b00);
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always @(DP_Q or switch or PACKET)
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case (PACKET[1:0])
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2'b00 : dbyte0 = switch ? DP_Q[7:0] : DP_Q[39:32];
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2'b01 : dbyte0 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
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2'b10 : dbyte0 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];
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2'b11 : dbyte0 = PACKET[3] ? DP_Q[47:40] : DP_Q[15:8];
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endcase
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always @(DP_Q or switch or PACKET)
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case (PACKET[1:0])
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2'b00 : dbyte1 = switch ? DP_Q[15:8] : DP_Q[47:40];
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2'b01 : dbyte1 = switch ? DP_Q[7:0] : DP_Q[39:32];
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2'b10 : dbyte1 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
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2'b11 : dbyte1 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];
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endcase
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always @(DP_Q or switch or PACKET)
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case (PACKET[1:0])
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2'b00 : dbyte2 = switch ? DP_Q[23:16] : DP_Q[55:48];
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2'b01 : dbyte2 = switch ? DP_Q[15:8] : DP_Q[47:40];
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2'b10 : dbyte2 = switch ? DP_Q[7:0] : DP_Q[39:32];
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2'b11 : dbyte2 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
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endcase
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always @(DP_Q or switch or PACKET)
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case (PACKET[1:0])
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2'b00 : dbyte3 = switch ? DP_Q[31:24] : DP_Q[63:56];
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2'b01 : dbyte3 = switch ? DP_Q[23:16] : DP_Q[55:48];
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2'b10 : dbyte3 = switch ? DP_Q[15:8] : DP_Q[47:40];
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2'b11 : dbyte3 = switch ? DP_Q[7:0] : DP_Q[39:32];
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endcase
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assign WRDATA = {dbyte3,dbyte2,dbyte1,dbyte0};
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always @(SIZE or PACKET)
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casex ({SIZE,PACKET})
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6'b00_xx_00 : ENBYTE = 4'b0001; // BYTE
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6'b00_xx_01 : ENBYTE = 4'b0010;
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6'b00_xx_10 : ENBYTE = 4'b0100;
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6'b00_xx_11 : ENBYTE = 4'b1000;
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//
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6'b01_xx_00 : ENBYTE = 4'b0011; // WORD
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6'b01_xx_01 : ENBYTE = 4'b0110;
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6'b01_xx_10 : ENBYTE = 4'b1100;
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6'b01_0x_11 : ENBYTE = 4'b1000;
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6'b01_1x_11 : ENBYTE = 4'b0001;
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//
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6'b11_xx_00 : ENBYTE = 4'b1111; // QWORD
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6'b11_00_01 : ENBYTE = 4'b1110;
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6'b11_01_01 : ENBYTE = 4'b1111;
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6'b11_1x_01 : ENBYTE = 4'b0001;
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6'b11_00_10 : ENBYTE = 4'b1100;
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6'b11_01_10 : ENBYTE = 4'b1111;
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6'b11_1x_10 : ENBYTE = 4'b0011;
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6'b11_00_11 : ENBYTE = 4'b1000;
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6'b11_01_11 : ENBYTE = 4'b1111;
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6'b11_1x_11 : ENBYTE = 4'b0111;
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//
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6'b10_xx_00 : ENBYTE = 4'b1111; // DWORD
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6'b10_0x_01 : ENBYTE = 4'b1110;
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6'b10_1x_01 : ENBYTE = 4'b0001;
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6'b10_0x_10 : ENBYTE = 4'b1100;
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6'b10_1x_10 : ENBYTE = 4'b0011;
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6'b10_0x_11 : ENBYTE = 4'b1000;
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6'b10_1x_11 : ENBYTE = 4'b0111;
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endcase
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endmodule
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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// 2. RD_ALINGER alignes read data for the data path
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module RD_ALIGNER ( BCLK, ACC_OK, PACKET, SIZE, REG_OUT, RDDATA, CA_HIT, DP_DI, AUX_QW );
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input BCLK;
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input ACC_OK;
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input [3:0] PACKET; // [3:2] Paketnumber , [1:0] Startaddress
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input [1:0] SIZE;
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input REG_OUT;
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input [31:0] RDDATA;
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input CA_HIT;
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output [31:0] DP_DI;
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output reg AUX_QW;
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reg [6:0] enable;
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reg [7:0] dreg_0,dreg_1,dreg_2,dreg_3,dreg_4,dreg_5,dreg_6;
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reg [7:0] out_0,out_1,out_2,out_3;
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// RD_ALIGNER principal working : 10 is last packet , 01 is packet in between
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// Not aligned QWORD : ADR[1:0] = 3 i.e.
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// Bytes to datapath : . - . - 4 - 4
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// Bytes from memory : 1 - 4 - 3 - .
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// ACC_DONE : _______/----\__
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// + 1 cycle ____/--
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// at the end 2 cycles lost. ACC_DONE informs the Op-Dec that data is available and sent one clock c
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// the LSD of QWORD access. (ACC_DONE -> REG_OUT is happening in ADDR_UNIT.)
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//
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// SIZE PACKET ADR : Output data ACC_OK
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// 00 -- 00 x x x B0 Byte 1
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// 00 -- 01 x x x B1 1
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// 00 -- 10 x x x B2 1
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// 00 -- 11 x x x B3 1
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// 01 00 00 x x B1 B0 Word 1
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// 01 00 01 x x B2 B1 1
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// 01 00 10 x x B3 B2 1
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// 01 00 11 B3 x x x -> Reg : R4 - - - 0
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// 01 10 11 x x B0 R4 1
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// 10 00 00 B3 B2 B1 B0 DWORD 1
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// 10 00 01 B3 B2 B1 x -> Reg : R6 R5 R4 - 0
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// 10 10 01 B0 R6 R5 R4 1
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// 10 00 10 B3 B2 x x -> Reg : R5 R4 - - 0
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// 10 10 10 B1 B0 R5 R4 1
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// 10 00 11 B3 x x x -> Reg : R4 - - - 0
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// 10 10 11 B2 B1 B0 R4 1
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// 11 00 00 B3 B2 B1 B0 QWORD 1 MSD
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// 11 01 00 B3 B2 B1 B0 not out of Reg! 0 LSD
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// 11 00 01 B3 B2 B1 x -> Reg : R2 R1 R0 - 0
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// 11 01 01 B3 B2 B1 B0 -> Reg : R6 R5 R4 R3 0
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// 11 10 01 B0 R6 R5 R4 1 MSD
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// next cycle: R3 R2 R1 R0 LSD
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// 11 00 10 B3 B2 x x -> Reg : R1 R0 - - 0
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// 11 01 10 B3 B2 B1 B0 -> Reg : R5 R4 R3 R2 0
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// 11 10 10 B1 B0 R5 R4 1 MSD
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// next cycle: R3 R2 R1 R0 LSD
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// 11 00 11 B3 x x x -> Reg : R0 - - - 0
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// 11 01 11 B3 B2 B1 B0 -> Reg : R4 R3 R2 R1 0
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// 11 10 11 B2 B1 B0 R4 1 MSD
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// next cycle: R3 R2 R1 R0 LSD
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// IO_ACCESS QWORD :
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// 11 00 00 B3 B2 B1 B0 -> Reg : R3 R2 R1 R0 0
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// 11 01 00 R3 R2 R1 R0 -> Reg : R3 R2 R1 R0 1 MSD
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// next cycle: R3 R2 R1 R0 LSD
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always @(ACC_OK or SIZE or PACKET)
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casex ({ACC_OK,SIZE,PACKET})
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7'b1_xx_0x_00 : enable = 7'b000_1111;
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7'b1_01_0x_11 : enable = 7'b001_0000;
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7'b1_10_0x_01 : enable = 7'b111_0000;
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7'b1_10_0x_10 : enable = 7'b011_0000;
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7'b1_10_0x_11 : enable = 7'b001_0000;
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7'b1_11_00_01 : enable = 7'b000_0111; // QWORD
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| 250 |
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7'b1_11_01_01 : enable = 7'b111_1000;
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| 251 |
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7'b1_11_00_10 : enable = 7'b000_0011;
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| 252 |
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7'b1_11_01_10 : enable = 7'b011_1100;
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| 253 |
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7'b1_11_00_11 : enable = 7'b000_0001;
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| 254 |
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7'b1_11_01_11 : enable = 7'b001_1110;
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| 255 |
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default : enable = 7'b000_0000;
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| 256 |
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endcase
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| 257 |
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| 258 |
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// Register for inbetween data: simple multiplexer
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| 259 |
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| 260 |
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always @(posedge BCLK)
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| 261 |
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if (enable[0])
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| 262 |
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case (PACKET[1:0])
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2'b01 : dreg_0 <= RDDATA[15:8];
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2'b10 : dreg_0 <= RDDATA[23:16];
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2'b11 : dreg_0 <= RDDATA[31:24];
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default : dreg_0 <= RDDATA[7:0];
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| 267 |
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endcase
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| 268 |
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| 269 |
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always @(posedge BCLK)
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if (enable[1])
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case (PACKET[1:0])
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2'b01 : dreg_1 <= RDDATA[23:16];
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2'b10 : dreg_1 <= RDDATA[31:24];
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2'b11 : dreg_1 <= RDDATA[7:0];
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| 275 |
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default : dreg_1 <= RDDATA[15:8];
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endcase
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| 277 |
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| 278 |
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always @(posedge BCLK)
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| 279 |
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if (enable[2])
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| 280 |
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case (PACKET[1:0])
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| 281 |
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2'b01 : dreg_2 <= RDDATA[31:24];
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| 282 |
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2'b10 : dreg_2 <= RDDATA[7:0];
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| 283 |
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2'b11 : dreg_2 <= RDDATA[15:8];
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| 284 |
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default : dreg_2 <= RDDATA[23:16];
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| 285 |
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endcase
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| 286 |
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| 287 |
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always @(posedge BCLK)
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| 288 |
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if (enable[3])
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| 289 |
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case (PACKET[1:0])
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| 290 |
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2'b01 : dreg_3 <= RDDATA[7:0];
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| 291 |
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2'b10 : dreg_3 <= RDDATA[15:8];
|
| 292 |
|
|
2'b11 : dreg_3 <= RDDATA[23:16];
|
| 293 |
|
|
default : dreg_3 <= RDDATA[31:24];
|
| 294 |
|
|
endcase
|
| 295 |
|
|
|
| 296 |
|
|
always @(posedge BCLK)
|
| 297 |
|
|
if (enable[4])
|
| 298 |
|
|
case (PACKET[1:0])
|
| 299 |
|
|
2'b01 : dreg_4 <= RDDATA[15:8];
|
| 300 |
|
|
2'b10 : dreg_4 <= RDDATA[23:16];
|
| 301 |
|
|
2'b11 : dreg_4 <= RDDATA[31:24];
|
| 302 |
|
|
default : dreg_4 <= dreg_4;
|
| 303 |
|
|
endcase
|
| 304 |
|
|
|
| 305 |
|
|
always @(posedge BCLK) if (enable[5]) dreg_5 <= PACKET[1] ? RDDATA[31:24] : RDDATA[23:16];
|
| 306 |
|
|
|
| 307 |
|
|
always @(posedge BCLK) if (enable[6]) dreg_6 <= RDDATA[31:24];
|
| 308 |
|
|
|
| 309 |
|
|
// +++++++++++++++++++++++
|
| 310 |
|
|
|
| 311 |
|
|
always @(SIZE or PACKET or RDDATA or dreg_0 or dreg_4)
|
| 312 |
|
|
casex ({SIZE,PACKET[3],PACKET[1:0]})
|
| 313 |
|
|
5'b0x_0_01 : out_0 = RDDATA[15:8];
|
| 314 |
|
|
5'b0x_0_10 : out_0 = RDDATA[23:16];
|
| 315 |
|
|
5'b00_0_11 : out_0 = RDDATA[31:24];
|
| 316 |
|
|
5'b01_1_11 : out_0 = dreg_4;
|
| 317 |
|
|
5'b1x_1_01 : out_0 = dreg_4;
|
| 318 |
|
|
5'b1x_1_1x : out_0 = dreg_4;
|
| 319 |
|
|
default : out_0 = RDDATA[7:0];
|
| 320 |
|
|
endcase
|
| 321 |
|
|
|
| 322 |
|
|
always @(SIZE or PACKET or RDDATA or dreg_1 or dreg_5)
|
| 323 |
|
|
casex ({SIZE,PACKET[3],PACKET[1:0]})
|
| 324 |
|
|
5'b01_0_01 : out_1 = RDDATA[23:16];
|
| 325 |
|
|
5'b01_0_10 : out_1 = RDDATA[31:24];
|
| 326 |
|
|
5'bxx_x_11 : out_1 = RDDATA[7:0];
|
| 327 |
|
|
5'b1x_1_01 : out_1 = dreg_5;
|
| 328 |
|
|
5'b1x_1_10 : out_1 = dreg_5;
|
| 329 |
|
|
default : out_1 = RDDATA[15:8];
|
| 330 |
|
|
endcase
|
| 331 |
|
|
|
| 332 |
|
|
always @(SIZE or PACKET or RDDATA or dreg_2 or dreg_6)
|
| 333 |
|
|
case ({SIZE[1],PACKET[3],PACKET[1:0]})
|
| 334 |
|
|
4'b1_1_01 : out_2 = dreg_6;
|
| 335 |
|
|
4'b1_1_10 : out_2 = RDDATA[7:0];
|
| 336 |
|
|
4'b1_1_11 : out_2 = RDDATA[15:8];
|
| 337 |
|
|
default : out_2 = RDDATA[23:16];
|
| 338 |
|
|
endcase
|
| 339 |
|
|
|
| 340 |
|
|
always @(SIZE or PACKET or RDDATA or dreg_3)
|
| 341 |
|
|
case ({SIZE[1],PACKET[3],PACKET[1:0]})
|
| 342 |
|
|
4'b1_1_01 : out_3 = RDDATA[7:0];
|
| 343 |
|
|
4'b1_1_10 : out_3 = RDDATA[15:8];
|
| 344 |
|
|
4'b1_1_11 : out_3 = RDDATA[23:16];
|
| 345 |
|
|
default : out_3 = RDDATA[31:24];
|
| 346 |
|
|
endcase
|
| 347 |
|
|
|
| 348 |
|
|
assign DP_DI = REG_OUT ? {dreg_3,dreg_2,dreg_1,dreg_0} : {out_3,out_2,out_1,out_0};
|
| 349 |
|
|
|
| 350 |
|
|
// ++++++++++++++++ Special case QWord if cache switched off +++++++++++++++++++
|
| 351 |
|
|
|
| 352 |
|
|
always @(posedge BCLK) AUX_QW <= ACC_OK & ~CA_HIT & (SIZE == 2'b11) & PACKET[3];
|
| 353 |
|
|
|
| 354 |
|
|
endmodule
|
