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[/] [m32632/] [trunk/] [rtl/] [CACHE_LOGIK.v] - Blame information for rev 28

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1 9 ns32kum
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6 23 ns32kum
//      Filename:       CACHE_LOGIK.v
7
//      Version:        2.0
8
//      History:        1.1 bug fix of 7 October 2015
9
//                              1.0 first release of 30 Mai 2015
10
//      Date:           14 August 2016
11 9 ns32kum
//
12 23 ns32kum
// Copyright (C) 2016 Udo Moeller
13 9 ns32kum
// 
14
// This source file may be used and distributed without 
15
// restriction provided that this copyright statement is not 
16
// removed from the file and that any derivative work contains 
17
// the original copyright notice and the associated disclaimer.
18
// 
19
// This source file is free software; you can redistribute it 
20
// and/or modify it under the terms of the GNU Lesser General 
21
// Public License as published by the Free Software Foundation;
22
// either version 2.1 of the License, or (at your option) any 
23
// later version. 
24
// 
25
// This source is distributed in the hope that it will be 
26
// useful, but WITHOUT ANY WARRANTY; without even the implied 
27
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
28
// PURPOSE. See the GNU Lesser General Public License for more 
29
// details. 
30
// 
31
// You should have received a copy of the GNU Lesser General 
32
// Public License along with this source; if not, download it 
33
// from http://www.opencores.org/lgpl.shtml 
34
// 
35
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
36
//
37
//      Modules contained in this file:
38 23 ns32kum
//      1. NEU_VALID    Cache Valid RAM
39
//      2. DEBUG_AE     Debug unit for address compare in data cache
40
//      3. MMU_UP               MMU memory update and initalization controller
41
//      4. DCA_CONTROL  Data cache valid memory update and initalization controller
42
//      5. MMU_MATCH    MMU virtual address match detector
43
//      6. CA_MATCH             Cache tag match detector
44
//      7. FILTCMP              Address Filter and Comparator
45
//      8. DCACHE_SM    Data cache state machine
46 9 ns32kum
//
47 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
48 9 ns32kum
 
49 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
50 9 ns32kum
//
51 23 ns32kum
//      1. NEU_VALID    Cache Valid RAM
52 9 ns32kum
//
53 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
54 23 ns32kum
module NEU_VALID ( BCLK, VALIN, WADR, WREN, RADR, VALOUT );
55
 
56
        input                   BCLK;
57
        input   [23:0]   VALIN;
58
        input    [4:0]   WADR;
59
        input                   WREN;
60
        input    [4:0]   RADR;
61
 
62
        output  [23:0]   VALOUT;
63
 
64
        reg             [23:0]   cvalid [0:31];   // Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
65
        reg             [23:0]   ramout;
66
        reg             [23:0]   valhold;
67
        reg                             gleich;
68
 
69
        always @(posedge BCLK) ramout <= cvalid[RADR];
70
        always @(posedge BCLK) if (WREN) cvalid[WADR] <= VALIN;
71
 
72
        always @(posedge BCLK) valhold <= VALIN;
73
        always @(posedge BCLK) gleich  <= WREN & (RADR == WADR);
74
 
75
        assign VALOUT = gleich ? valhold : ramout;
76
 
77
endmodule
78
 
79
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
80
//
81
//      2. DEBUG_AE     Debug unit for address compare in data cache
82
//
83
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
84 9 ns32kum
module DEBUG_AE ( DBG_IN, READ, WRITE, USER, VIRTUELL, ACC_OK, VADR_R, MMU_Q, ENBYTE, DBG_HIT );
85
 
86
        input   [40:2]  DBG_IN;
87
 
88
        input                   READ,WRITE;
89
        input                   USER;
90
        input                   VIRTUELL;
91
        input                   ACC_OK;
92
        input   [31:2]  VADR_R;
93
        input   [19:0]   MMU_Q;
94
        input    [3:0]   ENBYTE;
95
 
96
        output                  DBG_HIT;
97
 
98
        wire                    sd,ud,crd,cwr,vnp;
99
        wire                    make;
100
        wire                    virt_adr,real_adr,page_adr;
101
        wire                    byte_en;
102
 
103
        assign sd  = DBG_IN[40];
104
        assign ud  = DBG_IN[39];
105
        assign crd = DBG_IN[38];
106
        assign cwr = DBG_IN[37];
107
        assign vnp = DBG_IN[36];
108
 
109
        assign make =  ((ud & USER) | (sd & ~USER))             // compare USER or SUPERVISOR
110
                                 & (VIRTUELL == vnp)                            // compare real or virtual address
111
                                 & ((cwr & WRITE) | (crd & READ));      // compare READ or WRITE
112
 
113
        assign virt_adr = (MMU_Q                 == DBG_IN[31:12]);
114
        assign real_adr = (VADR_R[31:12] == DBG_IN[31:12]);
115
        assign page_adr = (VADR_R[11:2]  == DBG_IN[11:2]);
116
 
117
        assign byte_en  = |(ENBYTE & DBG_IN[35:32]);
118
 
119
        assign DBG_HIT  =  ACC_OK               // all valid
120
                                         & make                 // selection is valid
121
                                         & (VIRTUELL ? virt_adr : real_adr)     & page_adr      // address
122
                                         & byte_en;             // Byte Enable
123
 
124
endmodule
125
 
126 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
127 9 ns32kum
//
128 23 ns32kum
//      3. MMU_UP               MMU memory update and initalization controller
129 9 ns32kum
//
130 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
131 9 ns32kum
module MMU_UP ( BCLK, BRESET, NEW_PTB, PTB1, IVAR, WR_MRAM, VADR, VADR_R, MVALID, UPDATE,
132
                                WE_MV, WADR_MV, RADR_MV, DAT_MV, NEW_PTB_RUN );
133
 
134
        input                   BCLK;
135
        input                   BRESET;
136
        input                   NEW_PTB;        // the MMU memory is cleared. Pulse of one BCLK cycle, Op-Dec is waiting
137
        input                   PTB1;           // which one
138
        input                   IVAR;
139
        input                   WR_MRAM;        // BCLK : update MRAM and MMU_VAL
140
        input  [19:16]  VADR,VADR_R;    // For update
141
        input   [31:0]   MVALID,UPDATE;
142
 
143
        output                  WE_MV;          // Write Enable MMU Valid
144
        output   [3:0]   WADR_MV,RADR_MV;
145
        output  [31:0]   DAT_MV;
146
        output                  NEW_PTB_RUN;
147
 
148
        reg                             neue_ptb,wr_flag,old_rst,run_over;
149
        reg              [3:0]   count;
150
 
151
        wire    [15:0]   new_val;
152
 
153
        assign WE_MV   = wr_flag | WR_MRAM | IVAR;      // write on falling edge BCLK
154
        assign RADR_MV = run_over ? count : VADR;
155
        assign WADR_MV = wr_flag ? (count - 4'b0001) : VADR_R;
156 11 ns32kum
        assign DAT_MV  = wr_flag ? {MVALID[31:16],new_val} : UPDATE;    // Only the matching entries are cleared : PTB0/PTB1
157 9 ns32kum
 
158
        // [31:16] Address-Space memory, [15:0] Valid memory
159 11 ns32kum
        assign new_val = neue_ptb ? (PTB1 ? (MVALID[15:0] & ~MVALID[31:16]) : (MVALID[15:0] & MVALID[31:16])) : 16'h0;
160 9 ns32kum
 
161
        always @(posedge BCLK or negedge BRESET)
162
                if (!BRESET) neue_ptb <= 1'b0;
163
                        else neue_ptb <= NEW_PTB | (neue_ptb & run_over);
164
 
165
        always @(posedge BCLK) old_rst <= BRESET;       // after Reset all will be set to 0 
166
 
167
        always @(posedge BCLK) run_over <= ((~old_rst | NEW_PTB) | (run_over & (count != 4'hF))) & BRESET;
168
 
169
        always @(posedge BCLK) count <= run_over ? count + 4'h1 : 4'h0;
170
 
171
        always @(posedge BCLK) wr_flag <= run_over;
172
 
173
        assign NEW_PTB_RUN = wr_flag;   // Info to Op-Dec
174
 
175
endmodule
176
 
177 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
178 9 ns32kum
//
179 23 ns32kum
//      4. DCA_CONTROL  Data cache valid memory update and initalization controller
180 9 ns32kum
//
181 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
182
module DCA_CONTROL ( BCLK, MCLK, BRESET, CUPDATE, DRAM_ACC, CA_SET, HIT_ALL, WRCFG, VADR_R, UPDATE, INVAL_A, WRITE,
183 9 ns32kum
                                         WCTRL, KILL, WRCRAM0, WRCRAM1, WE_CV, WADR_CV, DAT_CV, INIT_CA_RUN, WRSET0, WRSET1 );
184
 
185
        input                   BCLK;
186
        input                   MCLK;
187
        input                   BRESET;
188
        input                   CUPDATE;        // State CUPDATE : Cache is filled from DRAM
189
        input                   DRAM_ACC;
190
        input                   CA_SET;
191
        input                   HIT_ALL;        // a complete cache hit !
192
        input                   WRCFG;          // static signal : GND or VDD
193
        input   [11:7]  VADR_R;
194
        input   [23:0]   UPDATE;
195
        input                   INVAL_A;
196
        input                   WRITE;
197 11 ns32kum
        input    [1:0]   WCTRL;          // [1] : Read Burst Signal from DRAM controller, MCLK aligned. [0] : Cache inhibit
198 9 ns32kum
        input                   KILL;           // valid Ram must be updated because of collision ... or CINV
199
 
200
        output                  WRCRAM0,WRCRAM1;
201
        output                  WE_CV;
202
        output   [4:0]   WADR_CV;
203
        output  [23:0]   DAT_CV;
204
        output                  INIT_CA_RUN;
205
        output                  WRSET0,WRSET1;
206
 
207
        reg              [1:0]   state;
208
        reg              [4:0]   acount;
209
        reg                             ca_set_d;
210
 
211
        reg                             dly_bclk,zero,wr_puls;
212
        reg              [2:0]   count,refer;
213
 
214
        wire                    countf;
215
 
216 23 ns32kum
        always @(posedge BCLK) if (DRAM_ACC) ca_set_d <= CA_SET;        // Store for whole access
217
 
218 9 ns32kum
        // physical address is stored in TAG-RAM
219
 
220 23 ns32kum
        assign WRCRAM0 = (CUPDATE & ~WCTRL[0]) & ~ca_set_d;
221
        assign WRCRAM1 = (CUPDATE & ~WCTRL[0]) &  ca_set_d;
222 9 ns32kum
 
223
        // Load Valid RAM :
224
 
225
        assign WE_CV   = state[1] | HIT_ALL | (CUPDATE & ~WCTRL[0]) | KILL; // Hit All for "Last" Update
226
        assign WADR_CV = state[1] ? acount : VADR_R;
227
        assign DAT_CV  = state[1] ? 24'h0 : UPDATE;
228
 
229
        // Clear of Cache-Valid RAMs : 32 clocks of BCLK
230
 
231
        assign countf = (acount == 5'h1F);
232
 
233
        always @(posedge BCLK)
234
                casex ({BRESET,INVAL_A,countf,state[1:0]})
235
                  5'b0xx_xx : state <= 2'b01;
236
                  5'b1xx_01 : state <= 2'b10;           // start counter
237
                  5'b10x_00 : state <= 2'b00;           // wait ...
238
                  5'b11x_00 : state <= 2'b10;
239
                  5'b1x0_10 : state <= 2'b10;
240
                  5'b1x1_10 : state <= 2'b00;
241
                  default   : state <= 2'b0;
242
                endcase
243
 
244
        always @(posedge BCLK) if (!state[1]) acount <= 5'h0; else acount <= acount + 5'h01;
245
 
246
        assign INIT_CA_RUN = state[1];
247
 
248
        // WRITE Control in data RAMs
249
        assign WRSET0 = ( ~CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] & ~ca_set_d);
250
        assign WRSET1 = (  CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] &  ca_set_d);
251
 
252
        // ++++++++++++ Special circuit for Timing of write pulse for data RAM of data cache +++++++++
253
 
254
        always @(negedge MCLK) dly_bclk <= BCLK;
255
 
256
        always @(negedge MCLK) zero <= BCLK & ~dly_bclk;
257
 
258
        always @(posedge MCLK) if (zero) count <= 3'd0; else count <= count + 3'd1;
259
 
260
        //    count at zero , ref Wert
261
        // 1 : --- always on    5 : 100  001
262
        // 2 : 001  000                 6 : 101  010
263
        // 3 : 010  010                 7 : 110  011
264
        // 4 : 011  000                 8 : 111  100
265 11 ns32kum
        always @(posedge MCLK) if (zero) refer <= {(count == 3'd7),((count == 3'd5) | (count[1:0] == 2'b10)),(count[2] & ~count[0])};
266 9 ns32kum
 
267
        always @(posedge MCLK) wr_puls <= (count == refer) | WRCFG;
268
 
269
endmodule
270
 
271 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
272 9 ns32kum
//
273 23 ns32kum
//      5. MMU_MATCH    MMU virtual address match detector
274 9 ns32kum
//
275 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
276 9 ns32kum
module MMU_MATCH ( USER, READ, WRITE, RMW, MCR_FLAGS, MVALID, VADR_R, MMU_VA, IVAR,
277
                                   VIRTUELL, MMU_HIT , UPDATE, PROT_ERROR, CI, SEL_PTB1 );
278
 
279
        input                   USER;
280
        input                   READ;
281
        input                   WRITE;
282
        input                   RMW;
283
        input    [2:0]   MCR_FLAGS;
284
        input   [31:0]   MVALID;
285
        input  [31:12]  VADR_R;
286
        input  [31:16]  MMU_VA;
287
        input    [1:0]   IVAR;   // Invalidate Entry
288
 
289
        output                  VIRTUELL;       // only for Adress-Mux
290
        output                  MMU_HIT;
291
        output  [31:0]   UPDATE;
292
        output  reg             PROT_ERROR;     // if valid must suppress write in Write Buffer and cache
293
        output                  CI,SEL_PTB1;
294
 
295
        reg             [15:0]   maske;
296
 
297
        wire                    adr_space,as_sorte,match,alles_ok;
298
        wire    [15:0]   val_bits,as_bits;
299
        wire                    ena_prot;
300
        wire                    zugriff;
301
 
302
        assign zugriff = READ | WRITE;
303
 
304
        always @(VADR_R)
305
                case (VADR_R[15:12])
306
                  4'h0 : maske = 16'h0001;
307
                  4'h1 : maske = 16'h0002;
308
                  4'h2 : maske = 16'h0004;
309
                  4'h3 : maske = 16'h0008;
310
                  4'h4 : maske = 16'h0010;
311
                  4'h5 : maske = 16'h0020;
312
                  4'h6 : maske = 16'h0040;
313
                  4'h7 : maske = 16'h0080;
314
                  4'h8 : maske = 16'h0100;
315
                  4'h9 : maske = 16'h0200;
316
                  4'hA : maske = 16'h0400;
317
                  4'hB : maske = 16'h0800;
318
                  4'hC : maske = 16'h1000;
319
                  4'hD : maske = 16'h2000;
320
                  4'hE : maske = 16'h4000;
321
                  4'hF : maske = 16'h8000;
322
                endcase
323
 
324
        assign VIRTUELL = USER ? MCR_FLAGS[0] : MCR_FLAGS[1];
325
 
326 11 ns32kum
        assign adr_space = IVAR[1] ? IVAR[0] : (MCR_FLAGS[2] & USER);    // adr_space = IVARx ? 1 or 0 : DualSpace & TU
327 9 ns32kum
 
328
        assign as_sorte = ((MVALID[31:16] & maske) != 16'h0);
329
 
330 11 ns32kum
        assign match = (VADR_R[31:20] == MMU_VA[31:20]) & (adr_space == as_sorte) & ((MVALID[15:0] & maske) != 16'h0000);
331 9 ns32kum
 
332 11 ns32kum
        assign alles_ok = match & ( ~WRITE | MMU_VA[17] ) & ~PROT_ERROR;        // Modified - Flag : reload the PTE
333 9 ns32kum
 
334 23 ns32kum
        // if MMU_HIT = 0 then there is no Write-Buffer access and no update of cache !
335 9 ns32kum
        assign MMU_HIT = zugriff ? ( VIRTUELL ? alles_ok : 1'b1 ) : 1'b0 ;      // MMU off : then always HIT
336
 
337
        assign val_bits = IVAR[1] ? (MVALID[15:0] & (match ? ~maske : 16'hFFFF)) : (MVALID[15:0] | maske);
338 11 ns32kum
        assign as_bits  = IVAR[1] ? MVALID[31:16] : (adr_space ? (MVALID[31:16] | maske) : (MVALID[31:16] & ~maske));
339 9 ns32kum
 
340
        assign UPDATE = {as_bits,val_bits};
341
 
342
        assign ena_prot = zugriff & VIRTUELL & match;
343
 
344
        // A Protection error must suppress write in WB and cache
345
        always @(ena_prot or MMU_VA or USER or WRITE or RMW)
346
                case ({ena_prot,MMU_VA[19:18]})
347
                   3'b100 : PROT_ERROR = USER | WRITE | RMW;    // Only Supervisor READ
348
                   3'b101 : PROT_ERROR = USER;                                  // no USER access
349
                   3'b110 : PROT_ERROR = USER & (WRITE | RMW);  // USER only READ
350
                  default : PROT_ERROR = 1'b0;
351
                endcase
352
 
353
        assign CI = VIRTUELL & MMU_VA[16];
354
        assign SEL_PTB1 = adr_space;            // For PTE update
355
 
356
endmodule
357
 
358 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
359 9 ns32kum
//
360 23 ns32kum
//      6. CA_MATCH             Cache tag match detector
361 9 ns32kum
//
362 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
363 23 ns32kum
module CA_MATCH ( CVALID, DRAMSZ, ADDR, TAG0, TAG1, CFG, WRITE, MMU_HIT, CI, INVAL_L, KDET, ENDRAM, DC_ILO,
364 9 ns32kum
                                  CA_HIT, CA_SET, UPDATE, IO_SPACE, USE_CA, WB_ACC, KILL );
365
 
366
        input   [23:0]   CVALID;
367 23 ns32kum
        input    [2:0]   DRAMSZ;
368
        input   [31:4]  ADDR;
369 9 ns32kum
        input  [27:12]  TAG0,TAG1;
370
        input    [1:0]   CFG;    // LDC , DC
371
        input                   WRITE;
372
        input                   MMU_HIT;
373
        input                   CI;
374
        input                   INVAL_L;        // invalid cache line
375
        input                   KDET;
376
        input                   ENDRAM;
377
        input                   DC_ILO;         // CBITI/SBITI special case
378
 
379
        output                  CA_HIT;
380
        output                  CA_SET; // if no Hit then says SET where to store
381
        output  [23:0]   UPDATE; // Update Information for CVALID memory 
382
        output                  IO_SPACE;
383
        output                  USE_CA;
384
        output                  WB_ACC;
385
        output                  KILL;
386
 
387
        reg              [7:0]   maske;
388 23 ns32kum
        reg              [4:0]   szmaske;
389 9 ns32kum
 
390
        wire                    match_0,match_1;
391
        wire                    valid_0,valid_1;
392
        wire                    select;
393
        wire                    clear;
394
        wire     [7:0]   update_0,update_1,lastinfo;
395 23 ns32kum
        wire                    sel_dram,filter;
396 9 ns32kum
 
397
        always @(ADDR)
398
                case (ADDR[6:4])
399
                  3'h0 : maske = 8'h01;
400
                  3'h1 : maske = 8'h02;
401
                  3'h2 : maske = 8'h04;
402
                  3'h3 : maske = 8'h08;
403
                  3'h4 : maske = 8'h10;
404
                  3'h5 : maske = 8'h20;
405
                  3'h6 : maske = 8'h40;
406
                  3'h7 : maske = 8'h80;
407
                endcase
408
 
409
        assign valid_0 = (( CVALID[7:0] & maske) != 8'h00);
410
        assign valid_1 = ((CVALID[15:8] & maske) != 8'h00);
411
 
412
        assign match_0 = ( TAG0 == ADDR[27:12] );       // 4KB
413
        assign match_1 = ( TAG1 == ADDR[27:12] );       // 4KB
414
 
415
        assign CA_HIT = ((valid_0 & match_0) | (valid_1 & match_1)) & ~DC_ILO & CFG[0];
416
 
417
        // which SET is written in cache miss ? If both are valid the last used is not taken
418 11 ns32kum
        assign select = (valid_1 & valid_0) ? ~((CVALID[23:16] & maske) != 8'h00) : valid_0;    // Last-used field = CVALID[23:16]
419 9 ns32kum
 
420
        assign CA_SET = CA_HIT ? (valid_1 & match_1) : select;
421
 
422
        assign clear = INVAL_L | KDET;  // INVAL_L is from CINV
423
 
424
        assign update_0 = CA_SET ? CVALID[7:0] : (clear ? (CVALID[7:0] & ~maske) : (CVALID[7:0] | maske));
425 11 ns32kum
        assign update_1 = CA_SET ? (clear ? (CVALID[15:8] & ~maske) : (CVALID[15:8] | maske)) : CVALID[15:8];
426 9 ns32kum
 
427 11 ns32kum
        assign lastinfo = CA_HIT ? (CA_SET ? (CVALID[23:16] | maske) : (CVALID[23:16] & ~maske)) : CVALID[23:16];
428 9 ns32kum
 
429
        assign UPDATE = {lastinfo,update_1,update_0};
430
 
431
        assign KILL = clear & CA_HIT & ~CFG[1];         // only if cache is not locked
432
 
433 23 ns32kum
        always @(DRAMSZ)        // Size of DRAM
434
                casex (DRAMSZ)
435
                   3'b00x : szmaske = 5'h1F;    //   8 MB 32016 Second Processor
436
        //         3'b001 reserved for Ceres III
437
                   3'b01x : szmaske = 5'h10;    // 128 MB MCUBE
438
                default   : szmaske = 5'h00;    // 256 MB NetBSD
439
                endcase
440
 
441
        assign filter   = ((ADDR[27:23] & szmaske) == 5'd0);
442
        assign sel_dram =  (ADDR[31:28] == 4'd0) & filter & ENDRAM;
443 9 ns32kum
        assign IO_SPACE = ~sel_dram;                                    // not DRAM or DRAM ist off
444 23 ns32kum
 
445 9 ns32kum
        assign USE_CA   = ~CI & ~DC_ILO & CFG[0] & ~CFG[1];      // CI ? ILO ? Cache on ? Locked Cache ? 
446
        assign WB_ACC   = WRITE & MMU_HIT & sel_dram;
447
 
448
endmodule
449
 
450 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
451 9 ns32kum
//
452 23 ns32kum
//      7. FILTCMP              Address Filter and Comparator
453 9 ns32kum
//
454 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
455 23 ns32kum
module FILTCMP ( DRAMSZ, RADR, DRAM_A, ADR_EQU, TAGDAT );
456
 
457
        input    [2:0]   DRAMSZ;
458
        input   [27:4]  RADR,DRAM_A;
459
 
460
        output                  ADR_EQU;
461
        output reg      [27:12] TAGDAT;
462
 
463
        reg        [27:23]      adram;
464
 
465
        always @(DRAMSZ or RADR)
466
                casex (DRAMSZ)
467
                  3'b00x : TAGDAT = {5'd0,RADR[22:12]}; //   8 MB
468
                  3'bx10 : TAGDAT = {3'd0,RADR[24:12]}; //  32 MB
469
                  3'bx11 : TAGDAT = {2'd0,RADR[25:12]}; //  64 MB
470
                  3'b100 : TAGDAT = {1'd0,RADR[26:12]}; // 128 MB
471
                  3'b101 : TAGDAT =       RADR[27:12] ; // 256 MB
472
                endcase
473
 
474
        always @(DRAMSZ or DRAM_A)      // The address comparator is only used in the data cache.
475
                casex (DRAMSZ)
476
                  3'b00x : adram =  5'd0;                                       //   8 MB
477
                  3'bx10 : adram = {3'd0,DRAM_A[24:23]};        //  32 MB
478
                  3'bx11 : adram = {2'd0,DRAM_A[25:23]};        //  64 MB
479
                  3'b100 : adram = {1'd0,DRAM_A[26:23]};        // 128 MB
480
                  3'b101 : adram =       DRAM_A[27:23] ;        // 256 MB
481
                endcase
482
 
483
        assign ADR_EQU = {TAGDAT,RADR[11:4]} == {adram,DRAM_A[22:4]};
484
 
485
endmodule
486
 
487
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
488
//
489
//      8. DCACHE_SM    Data cache state machine
490
//
491
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
492 11 ns32kum
module DCACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, WRITE, ZTEST, RMW, CAPDAT, VADR_R, IC_VA,
493 23 ns32kum
                                   USE_CA, PTB_WR, PTB_SEL, SEL_PTB1, CPU_OUT, USER, PROT_ERROR, WB_ACC, ENWR, ADR_EQU, IC_PREQ, DMA_CHK, ICTODC,
494 12 ns32kum
                                   RWVAL, VIRTUELL, QWATWO,
495 11 ns32kum
                                   DRAM_ACC, DRAM_WR, IO_ACC, IO_RD, IO_WR, PTE_MUX, PD_MUX, PKEEP, PTE_ADR, PTE_DAT, HIT_ALL, ACC_OK,
496
                                   ABORT, PROTECT, IACC_STAT, ABO_LEVEL1, WR_MRAM, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE, MMU_DIN, IC_SIGS, KOMUX,
497 9 ns32kum
                                   KDET, DMA_MUX, HLDA, RWVFLAG, PTE_STAT );
498
 
499
        input                   BCLK;
500
        input                   BRESET;
501
        input                   IO_SPACE;
502
        input                   MDONE;          // Memory Done : feedback from DRAM Controller, BCLK aligned !
503
        input                   IO_READY;
504
        input                   MMU_HIT,CA_HIT;
505
        input                   READ,WRITE,ZTEST,RMW;
506
        input   [31:0]   CAPDAT;
507
        input  [31:12]  VADR_R,IC_VA;
508
        input                   USE_CA;
509
        input                   PTB_WR,PTB_SEL;
510
        input                   SEL_PTB1;
511
        input  [27:12]  CPU_OUT;        // used for PTB0/1
512
        input                   USER;
513
        input                   PROT_ERROR;
514
        input                   WB_ACC;
515
        input                   ENWR;           // Enable WRITE from DRAM
516
        input                   ADR_EQU;
517
        input                   IC_PREQ;
518 23 ns32kum
        input                   DMA_CHK;
519 9 ns32kum
        input    [3:0]   ICTODC;         // multiple signals from ICACHE, especially DMA
520
        input    [1:0]   RWVAL;          // RDVAL+WRVAL Operation
521
        input                   VIRTUELL;       // for RDVAL/WRVAL
522 12 ns32kum
        input                   QWATWO;
523 9 ns32kum
 
524
        output  reg             DRAM_ACC,DRAM_WR;
525
        output                  IO_ACC,IO_RD,IO_WR;
526
        output                  PTE_MUX,PD_MUX,PKEEP;
527
        output  [27:0]   PTE_ADR;
528
        output  [19:0]   PTE_DAT;
529
        output                  HIT_ALL;
530
        output                  ACC_OK;
531
        output                  ABORT,PROTECT;
532
        output   [3:1]  IACC_STAT;
533
        output                  ABO_LEVEL1;
534
        output                  WR_MRAM;
535
        output                  CUPDATE;
536
        output                  AUX_DAT;
537
        output  reg             NEW_PTB;
538
        output  reg             PTB_ONE;
539
        output  [23:0]   MMU_DIN;
540
        output   [1:0]   IC_SIGS;
541
        output                  KOMUX;
542
        output                  KDET;           // Signal for detection of collision
543
        output                  DMA_MUX;
544
        output                  HLDA;           // active low
545
        output                  RWVFLAG;        // RDVAL/WRVAL result
546
        output   [1:0]   PTE_STAT;
547
 
548
        reg                             IO_WR,IO_RD;
549
        reg              [1:0]   pl_dat;
550
        reg              [6:0]   new_state;
551
        reg              [2:0]   cap_dat;        // only for analyse of timing
552
        reg                             mem_done;
553
        reg                             rd_done;
554
        reg              [2:0]   pstate;
555
        reg                             pte_run_wr;
556
        reg              [1:0]   prot_level1;
557
        reg                             card_flag;
558
        reg        [27:12]      ptb0,ptb1;
559
        reg                             write_ok;
560
        reg                             icp_acc;
561
        reg                             pte_modi;
562
        reg              [2:0]   ko_state;
563
        reg                             dma_run;
564
        reg                             dma_kdet;
565
        reg                             rwv_bit;
566
        reg                             prot_i;
567
        reg                             rd_rdy;
568
 
569
        wire   [27:12]  ptb10;
570
        wire   [31:12]  virtual_adr;
571
        wire                    io_busy;
572
        wire                    dram_go;
573
        wire                    pte_sel;
574
        wire                    pte_acc;
575
        wire                    do_ca_rd,pte_go,do_ic_p;
576
        wire                    valid,valid_a,refer,modi;
577
        wire                    level1,level2;
578
        wire                    rd_level2;
579
        wire                    wr_req;
580
        wire                    wr_dram;
581
        wire                    wr_icmram;
582
        wire                    rd_ende;
583
        wire                    pte_dat_8;
584
        wire                    pte_wr_sig;
585
        wire                    run_dc;
586
        wire                    kostart;
587
        wire                    dma;
588
        wire                    dma_go;
589
        wire                    zugriff;
590
        wire                    mmu_hit_i;
591
        wire                    do_zt;
592
        wire                    zt_ok;
593
        wire     [1:0]   acc_level;
594
        wire                    user_ptw,wr_ptw;
595
        wire                    pte_puls;
596
 
597
        always @(posedge BCLK) cap_dat <= CAPDAT[2:0];
598
 
599
        // if USER not virtual then ZTEST is quickly done
600
        assign zugriff = READ | WRITE | (ZTEST & VIRTUELL);
601
        assign mmu_hit_i = MMU_HIT & ~ZTEST;
602
 
603
        // WB_ACC is a successful WRITE access, ICTODC[0] is coherent Logik release : >=3 entries in FIFO
604 11 ns32kum
        assign wr_req = WB_ACC & ((ENWR & ICTODC[0]) | (DRAM_WR & ADR_EQU));     // release done by DRAM signal ENWR
605 9 ns32kum
 
606
        assign rd_ende = CA_HIT | rd_rdy;       // CA_HIT only when Cache activ !
607
 
608
        always @(        zugriff        // READ or WRITE or ZTEST , global control
609
                          or PROT_ERROR // must not be
610
                        //
611
                          or IO_SPACE   // access of IO world
612
                          or io_busy    // is access already running ?
613
                        //
614
                          or mmu_hit_i  // Hit in MMU , now only a READ can happen
615
                          or READ
616
                          or wr_req
617
                          or rd_ende    // Cache Hit
618
                        //
619
                          or DRAM_ACC   // DRAM Access : shows an active state
620
                          or pte_acc    // PTE access is running
621
                        //
622
                          or IC_PREQ    // PTE Request from ICACHE
623
                        //
624
                          or dma                // DMA Request
625
                          or dma_run )  // DMA running
626
                        //                                       #_#                      #_#                                               #_#                                     #_#
627 11 ns32kum
                casex ({zugriff,PROT_ERROR,IO_SPACE,io_busy,mmu_hit_i,READ,wr_req,rd_ende,DRAM_ACC,pte_acc,IC_PREQ,dma,dma_run})
628 9 ns32kum
                // MMU Miss : PTE load from memory , valid too if WRITE and M=0
629
                  13'b10_xx_0xxx_x0_x_x0 : new_state = 7'b0001010;      // start PTE access
630
                // IO-Address selected : external access starts if not busy because of WRITE
631
                  13'b10_10_1xxx_x0_x_x0 : new_state = 7'b0000001;
632
                // DRAM access : Cache Miss at READ : 
633
                  13'b10_0x_1100_00_x_x0 : new_state = 7'b0010010;
634
                // DRAM access : WRITE
635
                  13'b10_0x_101x_x0_x_x0 : new_state = 7'b0000100;
636
                // PTE Request ICACHE , IO access with WRITE is stored - parallel DRAM access possible
637 23 ns32kum
                  13'b0x_xx_xxxx_x0_1_x0 : new_state = 7'b0101010;      // no access
638 11 ns32kum
                  13'b10_0x_1101_x0_1_x0 : new_state = 7'b0101010;      // if successful READ a PTE access can happen in parallel
639 9 ns32kum
                // DMA access. Attention : no IO-Write access in background and no ICACHE PTE access !
640 23 ns32kum
                  13'b0x_x0_xxxx_x0_0_10 : new_state = 7'b1000000;      // DMA access is started
641 9 ns32kum
                  default                                : new_state = 7'b0;
642
                endcase
643
 
644
        assign IO_ACC   = new_state[0];  // to load registers for data, addr und BE, signal one pulse
645
        assign dram_go  = new_state[1] | rd_level2 ;
646
        assign wr_dram  = new_state[2]; // pulse only
647
        assign pte_go   = new_state[3];
648
        assign do_ca_rd = new_state[4];
649
        assign do_ic_p  = new_state[5];
650
        assign dma_go   = new_state[6];
651
 
652
        // ZTEST logic is for the special case when a write access is crossing page boundaries
653
 
654
        assign do_zt = ZTEST & ~icp_acc;
655
 
656 11 ns32kum
        // 0 is pass , 1 is blocked. RWVAL[0] is 1 if WRVAL. Level 1 can only be blocked, otherwise ABORT or Level 2 is following.
657
        always @(posedge BCLK) if (mem_done) rwv_bit <= level2 ? ~(cap_dat[2] & (~RWVAL[0] | cap_dat[1])) : 1'b1;
658 9 ns32kum
 
659
        assign RWVFLAG = VIRTUELL & rwv_bit;
660
 
661 11 ns32kum
        assign zt_ok = mem_done & (RWVAL[1] ? (~cap_dat[2] | (RWVAL[0] & ~cap_dat[1]) | level2)  // Level 2 always ok
662 9 ns32kum
                                                                                : (cap_dat[0] & ~prot_i & level2) );     // "normal" access
663
 
664
        // PTE access logic, normal state machine
665
        // Updates to the PTEs are normal WRITE request to DRAM, therefore no MDONE at Write
666
 
667
        assign modi  = ~CAPDAT[8] & WRITE & write_ok & ~icp_acc;        // is "1" if the Modified Bit must be set
668
        assign refer = CAPDAT[7] | do_zt;       // Assumption "R" Bit is set if RDVAL/WRVAL and page border test
669
        assign valid = (do_zt & RWVAL[1]) ? (cap_dat[2] & (cap_dat[1] | ~RWVAL[0]) & cap_dat[0] & level1)
670
                                                                          : (cap_dat[0] & ~prot_i);
671
 
672
        always @(posedge BCLK) mem_done <= MDONE & pte_acc;
673
 
674
        always @(posedge BCLK or negedge BRESET)
675
                if (!BRESET) pstate <= 3'h0;
676
                  else
677
                        casex ({pte_go,mem_done,valid,refer,modi,pte_run_wr,pstate})
678
                          9'b0x_xxxx_000 : pstate <= 3'd0;      // nothing to do
679
                          9'b1x_xxxx_000 : pstate <= 3'd4;      // start
680
                          9'bx0_xxxx_100 : pstate <= 3'd4;      // wait for Level 1
681
                          9'bx1_0xxx_100 : pstate <= 3'd0;      // THAT'S ABORT ! 
682
                          9'bx1_11xx_100 : pstate <= 3'd6;      // PTE Level 1 was referenced , next is Level 2
683
                          9'bx1_10xx_100 : pstate <= 3'd5;      // for writing of modified Level 1 : R=1
684
                          9'bxx_xxx0_101 : pstate <= 3'd5;      // write must wait
685
                          9'bxx_xxx1_101 : pstate <= 3'd6;      // one wait cycle
686
                          9'bx0_xxxx_110 : pstate <= 3'd6;      // wait for Level 2
687
                          9'bx1_0xxx_110 : pstate <= 3'd0;      // THAT'S ABORT !
688
                          9'bx1_10xx_110 : pstate <= 3'd7;      // Update neccesary : R=0
689
                          9'bx1_110x_110 : pstate <= 3'd0;      // all ok - end
690
                          9'bx1_111x_110 : pstate <= 3'd7;      // Update neccesary : M=0
691
                          9'bxx_xxx0_111 : pstate <= 3'd7;      // write must wait
692
                          9'bxx_xxx1_111 : pstate <= 3'd0;      // continues to end of DRAM write
693
                          default            : pstate <= 3'd0;
694
                        endcase
695
 
696
        assign pte_acc =  pstate[2];
697
        assign level1  = ~pstate[1];
698
        assign level2  =  pstate[1];
699
 
700 11 ns32kum
        assign valid_a = (ZTEST & RWVAL[1]) ? (cap_dat[2] & (cap_dat[1] | ~RWVAL[0]) & ~cap_dat[0] & level1)
701 9 ns32kum
                                                                                : ~cap_dat[0];   // not do_zt because of icp_acc in ABORT
702
 
703
        assign ABORT   =   mem_done & valid_a & ~icp_acc;
704 11 ns32kum
        assign PROTECT = ((mem_done & prot_i  & ~icp_acc) | PROT_ERROR) & ~(ZTEST & RWVAL[1]);  // no Protection-Error at RDVAL/WRVAL
705 9 ns32kum
 
706
        assign IACC_STAT[1] = mem_done & ~cap_dat[0] & icp_acc;
707
        assign IACC_STAT[2] = level1;
708
        assign IACC_STAT[3] = mem_done & prot_i & icp_acc;
709
 
710
        assign ABO_LEVEL1 = level1;     // is stored in case of ABORT in ADDR_UNIT
711
 
712
        assign rd_level2 = (pstate == 3'd5) | (mem_done & (pstate == 3'd4) & refer & valid);
713
 
714
        assign WR_MRAM   = mem_done &  (pstate == 3'd6) & valid & ~icp_acc & ~ZTEST;
715
        assign wr_icmram = mem_done &  (pstate == 3'd6) & valid &  icp_acc;
716
 
717
        // Signals to the Instruction Cache
718
        // pte_acc combined with icp_acc for STATISTIK.
719
        assign IC_SIGS = {(pte_acc & icp_acc),wr_icmram};
720
 
721
        assign PTE_MUX = pte_go | (pte_acc & ~pstate[1]);
722
 
723
        assign pte_puls = mem_done & pte_acc & ~pstate[1];
724
        assign PTE_STAT = {(pte_puls & icp_acc),(pte_puls & ~icp_acc)}; // only for statistic
725
 
726 11 ns32kum
        assign PD_MUX =  ((pstate == 3'd4) & mem_done & valid & ~refer)         // switch data-MUX, write level 1 too
727 9 ns32kum
                                   | ((pstate == 3'd6) & mem_done & valid & (~refer | modi))    // write level 2
728
                                   | (((pstate == 3'd5) | (pstate == 3'd7)) & ~pte_run_wr);
729
 
730
        assign pte_wr_sig = ENWR & PD_MUX;
731
 
732
        always @(posedge BCLK) pte_run_wr <= pte_wr_sig;        // Ok-Signal for pstate State-machine
733
 
734
        assign PKEEP = (pstate == 3'd6) | ((pstate == 3'd7) & ~pte_run_wr);     // keep the DRAM address
735
 
736 11 ns32kum
        // If there is a PTE still in the data cache it must be deleted. If MMU Bits are set by the pte engine a following
737 9 ns32kum
        // READ would deliver wrong data if cache hit. Therefore access of the Tags.
738
        always @(posedge BCLK or negedge BRESET)
739
                if (!BRESET) ko_state <= 3'b000;
740
                  else
741
                        casex ({kostart,ko_state})
742
                          4'b0_000 : ko_state <= 3'b000;
743
                          4'b1_000 : ko_state <= 3'b110;
744
                          4'bx_110 : ko_state <= 3'b111;
745
                          4'bx_111 : ko_state <= 3'b100;
746
                          4'bx_100 : ko_state <= 3'b000;
747
                          default  : ko_state <= 3'b000;
748
                        endcase
749
 
750
        assign kostart = pte_go | rd_level2;
751
 
752 12 ns32kum
        // ko_state[2] suppresses ACC_OK at READ
753
        assign run_dc = (~ko_state[2] | QWATWO) & ~dma_run;     // Bugfix of 7.10.2015
754
        assign KOMUX  =   ko_state[1]                   |  DMA_MUX;
755
        assign KDET   =   ko_state[0]                    |  dma_kdet;
756 9 ns32kum
 
757 11 ns32kum
        assign HIT_ALL = MMU_HIT & CA_HIT & run_dc & ~pte_acc;  // for Update "Last-Set" , MMU_HIT contains ZUGRIFF
758 9 ns32kum
 
759
        always @(posedge BCLK or negedge BRESET)
760
                if (!BRESET) card_flag <= 1'b0;
761
                        else card_flag <= (do_ca_rd & ~rd_rdy) | (card_flag & ~MDONE);
762
 
763
        assign CUPDATE = card_flag & USE_CA & MDONE;
764
 
765
        always @(posedge BCLK) rd_rdy <= card_flag & MDONE;
766
 
767 11 ns32kum
        // The cache RAM can not provide fast enough the data after an Update. In this case a secondary data path is activated
768 9 ns32kum
        assign AUX_DAT = rd_rdy;
769
 
770
        // DRAM interface :
771
 
772
        always @(posedge BCLK)                          DRAM_WR  <= wr_dram | pte_wr_sig; // pulse
773
        always @(posedge BCLK) if (dram_go) DRAM_ACC <= 1'b1;
774
                                                         else
775
                                                                DRAM_ACC <= DRAM_ACC & ~MDONE & BRESET;
776
        // IO interface :
777
 
778
        always @(posedge BCLK)
779
          begin
780
                if (IO_ACC) IO_RD <= READ;  else IO_RD <= IO_RD & ~IO_READY & BRESET;
781
                if (IO_ACC) IO_WR <= WRITE; else IO_WR <= IO_WR & ~IO_READY & BRESET;
782
          end
783
 
784 11 ns32kum
        assign io_busy = IO_RD | IO_WR | rd_done;       // access is gone in next clock cycle, therefore blocked with "rd_done"
785 9 ns32kum
 
786 11 ns32kum
        always @(posedge BCLK) rd_done <= IO_RD & IO_READY;     // For READ one clock later for data to come through
787 9 ns32kum
 
788
        assign dma = ICTODC[2]; // external request HOLD after FF in ICACHE
789
 
790 11 ns32kum
        always @(posedge BCLK) dma_run <= (dma_go | (dma_run & dma)) & BRESET;  // stops the data access until HOLD becomes inactive
791 9 ns32kum
 
792
        assign HLDA = ~(ICTODC[1] & dma_run);   // Signal for system that the CPU has stopped accesses
793
 
794 23 ns32kum
        always @(posedge BCLK) dma_kdet <= DMA_CHK;
795
        assign DMA_MUX = DMA_CHK | dma_kdet;
796 9 ns32kum
 
797
        // global feedback to ADDR_UNIT, early feedback to Op-Dec : you can continue
798
 
799
        assign ACC_OK = ZTEST ? (~VIRTUELL | zt_ok)
800 11 ns32kum
                                                  : (IO_SPACE ? ((IO_ACC & WRITE) | rd_done) : (wr_dram | (READ & MMU_HIT & rd_ende & run_dc)) );
801 9 ns32kum
 
802
        // PTB1 and PTB0
803
 
804
        always @(posedge BCLK) if (PTB_WR && !PTB_SEL) ptb0 <= CPU_OUT[27:12];
805
        always @(posedge BCLK) if (PTB_WR &&  PTB_SEL) ptb1 <= CPU_OUT[27:12];
806
 
807
        always @(posedge BCLK) NEW_PTB <= PTB_WR;                       // to MMU Update Block
808
        always @(posedge BCLK) if (PTB_WR) PTB_ONE <= PTB_SEL;
809
 
810
        assign ptb10 = SEL_PTB1 ? ptb1 : ptb0;
811
 
812
        // Address multiplex between ICACHE=1 and DCACHE=0 :
813
        always @(posedge BCLK) if (pte_go) icp_acc <= do_ic_p;
814
 
815
        assign pte_sel = pte_go ? do_ic_p : icp_acc;
816
 
817
        assign virtual_adr = pte_sel ? IC_VA : VADR_R;
818
 
819
        // The 2 Address-LSB's : no full access : USE_CA = 0    
820 11 ns32kum
        assign PTE_ADR = rd_level2 ? {CAPDAT[27:12],virtual_adr[21:12],2'b00} : {ptb10,virtual_adr[31:22],2'b00};
821 9 ns32kum
 
822
        // PTE_DAT[8] is used for update of MMU_RAM.
823
        assign pte_dat_8 = (level2 & WRITE & write_ok & ~icp_acc) | CAPDAT[8];
824
        always @(posedge BCLK) pte_modi = pte_dat_8;
825
        assign PTE_DAT = {4'h3,CAPDAT[15:9],pte_modi,1'b1,CAPDAT[6:0]};  // the top 4 bits are Byte-Enable
826
 
827
        // The data for the MMU-RAM : 24 Bits , [6]=Cache Inhibit
828
        assign MMU_DIN = {pl_dat,pte_dat_8,CAPDAT[6],CAPDAT[31:12]};
829
 
830
        // Protection field
831
 
832
        always @(posedge BCLK) if (mem_done && (pstate[2:0] == 3'd4)) prot_level1 <= cap_dat[2:1];
833
 
834
        always @(prot_level1 or cap_dat)
835
                casex ({prot_level1,cap_dat[2]})
836
                  3'b11_x : pl_dat = cap_dat[2:1];
837
                  3'b10_1 : pl_dat = 2'b10;
838
                  3'b10_0 : pl_dat = cap_dat[2:1];
839
                  3'b01_1 : pl_dat = 2'b01;
840
                  3'b01_0 : pl_dat = cap_dat[2:1];
841
                  3'b00_x : pl_dat = 2'b00;
842
                endcase
843
 
844 11 ns32kum
        always @(USER or pl_dat)        // is used if no PTE update is neccesary for M-Bit if writing is not allowed
845 9 ns32kum
                casex ({USER,pl_dat})
846
                  3'b1_11 : write_ok = 1'b1;
847
                  3'b0_1x : write_ok = 1'b1;
848
                  3'b0_01 : write_ok = 1'b1;
849
                  default : write_ok = 1'b0;
850
                endcase
851
 
852
        assign acc_level = level2 ? pl_dat : cap_dat[2:1];
853
        assign user_ptw = icp_acc ? ICTODC[3] : USER;
854
        assign wr_ptw = ~icp_acc & (WRITE | RMW | (ZTEST & ~RWVAL[1])); // only data cache can write
855
 
856
        always @(acc_level or user_ptw or wr_ptw)
857
                case (acc_level)
858
                        2'b00 : prot_i = user_ptw | wr_ptw;
859
                        2'b01 : prot_i = user_ptw;
860
                        2'b10 : prot_i = user_ptw & wr_ptw;
861
                        2'b11 : prot_i = 1'b0;
862
                endcase
863
 
864
endmodule
865
 

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