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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

// This file is part of the M32632 project

// http://opencores.org/project,m32632

//

//      Filename:       CACHE_LOGIK.v

//  Version:    3.0

//      History:        2.0 of 11 August 2016

//                              1.1 bug fix of 7 October 2015

//                              1.0 first release of 30 Mai 2015

//      Date:           2 December 2018

//

// Copyright (C) 2018 Udo Moeller

// 

// This source file may be used and distributed without 

// restriction provided that this copyright statement is not 

// removed from the file and that any derivative work contains 

// the original copyright notice and the associated disclaimer.

// 

// This source file is free software; you can redistribute it 

// and/or modify it under the terms of the GNU Lesser General 

// Public License as published by the Free Software Foundation;

// either version 2.1 of the License, or (at your option) any 

// later version. 

// 

// This source is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied 

// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 

// PURPOSE. See the GNU Lesser General Public License for more 

// details. 

// 

// You should have received a copy of the GNU Lesser General 

// Public License along with this source; if not, download it 

// from http://www.opencores.org/lgpl.shtml 

// 

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      Modules contained in this file:

//      1. WRPORT               Write Port

//      2. NEU_VALID    Cache Valid RAM

//      3. DEBUG_AE     Debug unit for address compare in data cache

//      4. MMU_UP               MMU memory update and initalization controller

//      5. DCA_CONTROL  Data cache valid memory update and initalization controller

//      6. MMU_MATCH    MMU virtual address match detector

//      7. CA_MATCH             Cache tag match detector

//      8. FILTCMP              Address Filter and Comparator

//      9. DCACHE_SM    Data cache state machine

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      1. WRPORT       Write Port

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module WRPORT ( WRITE, DRAM_Q, WRDATA, ENBYTE, VADDR, DADDR, WDAT, CAP_Q, ENB );

        input                   WRITE;

        input  [127:0]   DRAM_Q;

        input   [31:0]   WRDATA;

        input    [3:0]   ENBYTE;

        input    [3:2]  VADDR;

        input    [3:2]  DADDR;

        output [127:0]   WDAT;

        output  reg     [31:0]   CAP_Q;

        output  reg     [15:0]   ENB;

        assign WDAT = WRITE ? {WRDATA,WRDATA,WRDATA,WRDATA} : DRAM_Q;

        always @(DADDR or DRAM_Q)

          case (DADDR)

            2'b00 : CAP_Q = DRAM_Q[31:0];

                2'b01 : CAP_Q = DRAM_Q[63:32];

                2'b10 : CAP_Q = DRAM_Q[95:64];

                2'b11 : CAP_Q = DRAM_Q[127:96];

          endcase

        always @(WRITE or VADDR or ENBYTE)

          case ({WRITE,VADDR})

             3'b100 : ENB = {4'd0  ,4'd0  ,4'd0  ,ENBYTE};

             3'b101 : ENB = {4'd0  ,4'd0  ,ENBYTE,4'd0  };

             3'b110 : ENB = {4'd0  ,ENBYTE,4'd0  ,4'd0  };

             3'b111 : ENB = {ENBYTE,4'd0  ,4'd0  ,4'd0  };

                default : ENB = 16'hFFFF;

          endcase

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      2. NEU_VALID    Cache Valid RAM

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module NEU_VALID ( BCLK, VALIN, WADR, WREN, RADR, VALOUT );

        input                   BCLK;

        input   [23:0]   VALIN;

        input    [4:0]   WADR;

        input                   WREN;

        input    [4:0]   RADR;

        output  [23:0]   VALOUT;

        reg             [23:0]   cvalid [0:31];   // Valid bits for Data Set 0 and 1 : 32 entries of 24 bits

        reg             [23:0]   ramout;

        reg             [23:0]   valhold;

        reg                             gleich;

        always @(posedge BCLK) ramout <= cvalid[RADR];

        always @(posedge BCLK) if (WREN) cvalid[WADR] <= VALIN;

        always @(posedge BCLK) valhold <= VALIN;

        always @(posedge BCLK) gleich  <= WREN & (RADR == WADR);

        assign VALOUT = gleich ? valhold : ramout;

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      3. DEBUG_AE     Debug unit for address compare in data cache

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module DEBUG_AE ( DBG_IN, READ, WRITE, USER, VIRTUELL, ACC_OK, VADR_R, MMU_Q, ENBYTE, DBG_HIT );

        input   [40:2]  DBG_IN;

        input                   READ,WRITE;

        input                   USER;

        input                   VIRTUELL;

        input                   ACC_OK;

        input   [31:2]  VADR_R;

        input   [19:0]   MMU_Q;

        input    [3:0]   ENBYTE;

        output                  DBG_HIT;

        wire                    sd,ud,crd,cwr,vnp;

        wire                    make;

        wire                    virt_adr,real_adr,page_adr;

        wire                    byte_en;

        assign sd  = DBG_IN[40];

        assign ud  = DBG_IN[39];

        assign crd = DBG_IN[38];

        assign cwr = DBG_IN[37];

        assign vnp = DBG_IN[36];

        assign make =  ((ud & USER) | (sd & ~USER))             // compare USER or SUPERVISOR

                                 & (VIRTUELL == vnp)                            // compare real or virtual address

                                 & ((cwr & WRITE) | (crd & READ));      // compare READ or WRITE

        assign virt_adr = (MMU_Q                 == DBG_IN[31:12]);

        assign real_adr = (VADR_R[31:12] == DBG_IN[31:12]);

        assign page_adr = (VADR_R[11:2]  == DBG_IN[11:2]);

        assign byte_en  = |(ENBYTE & DBG_IN[35:32]);

        assign DBG_HIT  =  ACC_OK               // all valid

                                         & make                 // selection is valid

                                         & (VIRTUELL ? virt_adr : real_adr)     & page_adr      // address

                                         & byte_en;             // Byte Enable

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      4. MMU_UP               MMU memory update and initalization controller

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module MMU_UP ( BCLK, BRESET, NEW_PTB, PTB1, IVAR, WR_MRAM, VADR, VADR_R, MVALID, UPDATE,

                                WE_MV, WADR_MV, RADR_MV, DAT_MV, NEW_PTB_RUN );

        input                   BCLK;

        input                   BRESET;

        input                   NEW_PTB;        // the MMU memory is cleared. Pulse of one BCLK cycle, Op-Dec is waiting

        input                   PTB1;           // which one

        input                   IVAR;

        input                   WR_MRAM;        // BCLK : update MRAM and MMU_VAL

        input  [19:16]  VADR,VADR_R;    // For update

        input   [31:0]   MVALID,UPDATE;

        output                  WE_MV;          // Write Enable MMU Valid

        output   [3:0]   WADR_MV,RADR_MV;

        output  [31:0]   DAT_MV;

        output                  NEW_PTB_RUN;

        reg                             neue_ptb,wr_flag,old_rst,run_over;

        reg              [3:0]   count;

        wire    [15:0]   new_val;

        assign WE_MV   = wr_flag | WR_MRAM | IVAR;      // write on falling edge BCLK

        assign RADR_MV = run_over ? count : VADR;

        assign WADR_MV = wr_flag ? (count - 4'b0001) : VADR_R;

        assign DAT_MV  = wr_flag ? {MVALID[31:16],new_val} : UPDATE;    // Only the matching entries are cleared : PTB0/PTB1

        // [31:16] Address-Space memory, [15:0] Valid memory

        assign new_val = neue_ptb ? (PTB1 ? (MVALID[15:0] & ~MVALID[31:16]) : (MVALID[15:0] & MVALID[31:16])) : 16'h0;

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) neue_ptb <= 1'b0;

                        else neue_ptb <= NEW_PTB | (neue_ptb & run_over);

        always @(posedge BCLK) old_rst <= BRESET;       // after Reset all will be set to 0 

        always @(posedge BCLK) run_over <= ((~old_rst | NEW_PTB) | (run_over & (count != 4'hF))) & BRESET;

        always @(posedge BCLK) count <= run_over ? count + 4'h1 : 4'h0;

        always @(posedge BCLK) wr_flag <= run_over;

        assign NEW_PTB_RUN = wr_flag;   // Info to Op-Dec

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      5. DCA_CONTROL  Data cache valid memory update and initalization controller

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module DCA_CONTROL ( BCLK, BRESET, CUPDATE, DRAM_ACC, CA_SET, HIT_ALL, VADR_R, UPDATE, INVAL_A, WRITE, MDONE, USE_CA,

                                         INHIBIT, KILL, WRCRAM0, WRCRAM1, WE_CV, WADR_CV, DAT_CV, INIT_CA_RUN, WRSET0, WRSET1 );

        input                   BCLK;

        input                   BRESET;

        input                   CUPDATE;        // State CUPDATE : Cache is filled from DRAM

        input                   DRAM_ACC;

        input                   CA_SET;

        input                   HIT_ALL;        // a complete cache hit !

        input   [11:7]  VADR_R;

        input   [23:0]   UPDATE;

        input                   INVAL_A;

        input                   WRITE;

        input                   MDONE;          // Signal from DRAM : Access Done

        input                   USE_CA;         // Signal use cache

        input                   INHIBIT;        // Signal cache inhibit  - no write in cache

        input                   KILL;           // valid Ram must be updated because of collision ... or CINV

        output                  WRCRAM0,WRCRAM1;

        output                  WE_CV;

        output   [4:0]   WADR_CV;

        output  [23:0]   DAT_CV;

        output                  INIT_CA_RUN;

        output                  WRSET0,WRSET1;

        reg              [1:0]   state;

        reg              [4:0]   acount;

        reg                             ca_set_d;

        wire                    countf;

        always @(posedge BCLK) if (DRAM_ACC) ca_set_d <= CA_SET;        // Store for whole access

        // physical address is stored in TAG-RAM

        assign WRCRAM0 = (CUPDATE & ~INHIBIT) & ~ca_set_d;

        assign WRCRAM1 = (CUPDATE & ~INHIBIT) &  ca_set_d;

        // Load Valid RAM :

        assign WE_CV   = state[1] | HIT_ALL | (CUPDATE & ~INHIBIT) | KILL; // Hit All for "Last" Update

        assign WADR_CV = state[1] ? acount : VADR_R;

        assign DAT_CV  = state[1] ? 24'h0 : UPDATE;

        // Clear of Cache-Valid RAMs : 32 clocks of BCLK

        assign countf = (acount == 5'h1F);

        always @(posedge BCLK)

                casex ({BRESET,INVAL_A,countf,state[1:0]})

                  5'b0xx_xx : state <= 2'b01;

                  5'b1xx_01 : state <= 2'b10;           // start counter

                  5'b10x_00 : state <= 2'b00;           // wait ...

                  5'b11x_00 : state <= 2'b10;

                  5'b1x0_10 : state <= 2'b10;

                  5'b1x1_10 : state <= 2'b00;

                  default   : state <= 2'b0;

                endcase

        always @(posedge BCLK) if (!state[1]) acount <= 5'h0; else acount <= acount + 5'h01;

        assign INIT_CA_RUN = state[1];

        // WRITE Control in data RAMs

        assign WRSET0 = ( ~CA_SET & WRITE & HIT_ALL) | (MDONE & USE_CA & ~ca_set_d);

        assign WRSET1 = (  CA_SET & WRITE & HIT_ALL) | (MDONE & USE_CA &  ca_set_d);

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      6. MMU_MATCH    MMU virtual address match detector

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module MMU_MATCH ( USER, READ, WRITE, RMW, MCR_FLAGS, MVALID, VADR_R, MMU_VA, IVAR,

                                   VIRTUELL, MMU_HIT , UPDATE, PROT_ERROR, CI, SEL_PTB1 );

        input                   USER;

        input                   READ;

        input                   WRITE;

        input                   RMW;

        input    [2:0]   MCR_FLAGS;

        input   [31:0]   MVALID;

        input  [31:12]  VADR_R;

        input  [31:16]  MMU_VA;

        input    [1:0]   IVAR;   // Invalidate Entry

        output                  VIRTUELL;       // only for Adress-Mux

        output                  MMU_HIT;

        output  [31:0]   UPDATE;

        output  reg             PROT_ERROR;     // if valid must suppress write in Write Buffer and cache

        output                  CI,SEL_PTB1;

        reg             [15:0]   maske;

        wire                    adr_space,as_sorte,match,alles_ok;

        wire    [15:0]   val_bits,as_bits;

        wire                    ena_prot;

        wire                    zugriff;

        assign zugriff = READ | WRITE;

        always @(VADR_R)

                case (VADR_R[15:12])

                  4'h0 : maske = 16'h0001;

                  4'h1 : maske = 16'h0002;

                  4'h2 : maske = 16'h0004;

                  4'h3 : maske = 16'h0008;

                  4'h4 : maske = 16'h0010;

                  4'h5 : maske = 16'h0020;

                  4'h6 : maske = 16'h0040;

                  4'h7 : maske = 16'h0080;

                  4'h8 : maske = 16'h0100;

                  4'h9 : maske = 16'h0200;

                  4'hA : maske = 16'h0400;

                  4'hB : maske = 16'h0800;

                  4'hC : maske = 16'h1000;

                  4'hD : maske = 16'h2000;

                  4'hE : maske = 16'h4000;

                  4'hF : maske = 16'h8000;

                endcase

        assign VIRTUELL = USER ? MCR_FLAGS[0] : MCR_FLAGS[1];

        assign adr_space = IVAR[1] ? IVAR[0] : (MCR_FLAGS[2] & USER);    // adr_space = IVARx ? 1 or 0 : DualSpace & TU

        assign as_sorte = ((MVALID[31:16] & maske) != 16'h0);

        assign match = (VADR_R[31:20] == MMU_VA[31:20]) & (adr_space == as_sorte) & ((MVALID[15:0] & maske) != 16'h0000);

        assign alles_ok = match & ( ~WRITE | MMU_VA[17] ) & ~PROT_ERROR;        // Modified - Flag : reload the PTE

        // if MMU_HIT = 0 then there is no Write-Buffer access and no update of cache !

        assign MMU_HIT = zugriff ? ( VIRTUELL ? alles_ok : 1'b1 ) : 1'b0 ;      // MMU off : then always HIT

        assign val_bits = IVAR[1] ? (MVALID[15:0] & (match ? ~maske : 16'hFFFF)) : (MVALID[15:0] | maske);

        assign as_bits  = IVAR[1] ? MVALID[31:16] : (adr_space ? (MVALID[31:16] | maske) : (MVALID[31:16] & ~maske));

        assign UPDATE = {as_bits,val_bits};

        assign ena_prot = zugriff & VIRTUELL & match;

        // A Protection error must suppress write in WB and cache

        always @(ena_prot or MMU_VA or USER or WRITE or RMW)

                case ({ena_prot,MMU_VA[19:18]})

                   3'b100 : PROT_ERROR = USER | WRITE | RMW;    // Only Supervisor READ

                   3'b101 : PROT_ERROR = USER;                                  // no USER access

                   3'b110 : PROT_ERROR = USER & (WRITE | RMW);  // USER only READ

                  default : PROT_ERROR = 1'b0;

                endcase

        assign CI = VIRTUELL & MMU_VA[16];

        assign SEL_PTB1 = adr_space;            // For PTE update

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      7. CA_MATCH             Cache tag match detector

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module CA_MATCH ( CVALID, DRAMSZ, ADDR, TAG0, TAG1, CFG, WRITE, MMU_HIT, CI, INVAL_L, KDET, ENDRAM, DC_ILO,

                                  CA_HIT, CA_SET, UPDATE, IO_SPACE, USE_CA, WB_ACC, KILL );

        input   [23:0]   CVALID;

        input    [2:0]   DRAMSZ;

        input   [31:4]  ADDR;

        input  [28:12]  TAG0,TAG1;

        input    [1:0]   CFG;    // LDC , DC

        input                   WRITE;

        input                   MMU_HIT;

        input                   CI;

        input                   INVAL_L;        // invalid cache line

        input                   KDET;

        input                   ENDRAM;

        input                   DC_ILO;         // CBITI/SBITI special case

        output                  CA_HIT;

        output                  CA_SET; // if no Hit then says SET where to store

        output  [23:0]   UPDATE; // Update Information for CVALID memory 

        output                  IO_SPACE;

        output                  USE_CA;

        output                  WB_ACC;

        output                  KILL;

        reg              [7:0]   maske;

        reg                             acc_dram;

        wire                    match_0,match_1;

        wire                    valid_0,valid_1;

        wire                    select;

        wire                    clear;

        wire     [7:0]   update_0,update_1,lastinfo;

        wire                    sel_dram;

        always @(ADDR)

                case (ADDR[6:4])

                  3'h0 : maske = 8'h01;

                  3'h1 : maske = 8'h02;

                  3'h2 : maske = 8'h04;

                  3'h3 : maske = 8'h08;

                  3'h4 : maske = 8'h10;

                  3'h5 : maske = 8'h20;

                  3'h6 : maske = 8'h40;

                  3'h7 : maske = 8'h80;

                endcase

        assign valid_0 = (( CVALID[7:0] & maske) != 8'h00);

        assign valid_1 = ((CVALID[15:8] & maske) != 8'h00);

        assign match_0 = ( TAG0 == ADDR[28:12] );       // 4KB

        assign match_1 = ( TAG1 == ADDR[28:12] );       // 4KB

        assign CA_HIT = ((valid_0 & match_0) | (valid_1 & match_1)) & ~DC_ILO & CFG[0] & (sel_dram | KDET);

        // which SET is written in cache miss ? If both are valid the last used is not taken

        assign select = (valid_1 & valid_0) ? ~((CVALID[23:16] & maske) != 8'h00) : valid_0;    // Last-used field = CVALID[23:16]

        assign CA_SET = CA_HIT ? (valid_1 & match_1) : select;

        assign clear = INVAL_L | KDET;  // INVAL_L is from CINV

        assign update_0 = CA_SET ? CVALID[7:0] : (clear ? (CVALID[7:0] & ~maske) : (CVALID[7:0] | maske));

        assign update_1 = CA_SET ? (clear ? (CVALID[15:8] & ~maske) : (CVALID[15:8] | maske)) : CVALID[15:8];

        assign lastinfo = CA_HIT ? (CA_SET ? (CVALID[23:16] | maske) : (CVALID[23:16] & ~maske)) : CVALID[23:16];

        assign UPDATE = {lastinfo,update_1,update_0};

        assign KILL = clear & CA_HIT & ~CFG[1];         // only if cache is not locked

        always @(DRAMSZ or ADDR)        // Size of DRAM

                case (DRAMSZ)

                  3'b000 : acc_dram = (ADDR[28:23] == 6'd0);    //   8 MB 32016 Second Processor

                  3'b001 : acc_dram = (ADDR[28:24] == 5'd0);    //  16 MB

                  3'b010 : acc_dram = (ADDR[28:25] == 4'd0);    //  32 MB

                  3'b011 : acc_dram = (ADDR[28:26] == 3'd0);    //  64 MB

                  3'b100 : acc_dram = (ADDR[28:27] == 2'd0);    // 128 MB

                  3'b101 : acc_dram = ~ADDR[28];                                // 256 MB

                  3'b110 : acc_dram =   1'b1;                                   // 512 MB

                  3'b111 : acc_dram = ~(ADDR[28:27] == 2'b10);  // 256 MB NetBSD + 128 MB

                endcase

        assign sel_dram =  (ADDR[31:29] == 3'd0) & acc_dram & ENDRAM;

        assign IO_SPACE = ~sel_dram;                                    // not DRAM or DRAM ist off

        assign USE_CA   = ~CI & ~DC_ILO & CFG[0] & ~CFG[1];      // CI ? ILO ? Cache on ? Locked Cache ? 

        assign WB_ACC   = WRITE & MMU_HIT & sel_dram;

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      8. FILTCMP              Address Filter and Comparator

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module FILTCMP ( DRAMSZ, RADR, DRAM_A, ADR_EQU, TAGDAT );

        input    [2:0]   DRAMSZ;

        input   [28:4]  RADR,DRAM_A;

        output                  ADR_EQU;

        output reg      [28:12] TAGDAT;

        reg        [28:23]      adram;

        always @(DRAMSZ or RADR)

                casex (DRAMSZ)

                  3'b000 : TAGDAT = {6'd0,RADR[22:12]}; //   8 MB

                  3'b001 : TAGDAT = {5'd0,RADR[23:12]}; //  16 MB

                  3'b010 : TAGDAT = {4'd0,RADR[24:12]}; //  32 MB

                  3'b011 : TAGDAT = {3'd0,RADR[25:12]}; //  64 MB

                  3'b100 : TAGDAT = {2'd0,RADR[26:12]}; // 128 MB

                  3'b101 : TAGDAT = {1'b0,RADR[27:12]}; // 256 MB

                  3'b11x : TAGDAT =       RADR[28:12] ; // 512 MB

                endcase

        always @(DRAMSZ or DRAM_A)      // The address comparator is only used in the data cache.

                casex (DRAMSZ)

                  3'b000 : adram =  6'd0;                                       //   8 MB

                  3'b001 : adram = {5'd0,DRAM_A[23]};           //  16 MB

                  3'b010 : adram = {4'd0,DRAM_A[24:23]};        //  32 MB

                  3'b011 : adram = {3'd0,DRAM_A[25:23]};        //  64 MB

                  3'b100 : adram = {2'd0,DRAM_A[26:23]};        // 128 MB

                  3'b101 : adram = {1'd0,DRAM_A[27:23]};        // 256 MB

                  3'b11x : adram =       DRAM_A[28:23] ;        // 512 MB

                endcase

        assign ADR_EQU = {TAGDAT,RADR[11:4]} == {adram,DRAM_A[22:4]};

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      9. DCACHE_SM    Data cache state machine

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module DCACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, WRITE, ZTEST, RMW, CAPDAT, VADR_R, IC_VA,

                                   USE_CA, PTB_WR, PTB_SEL, SEL_PTB1, CPU_OUT, USER, PROT_ERROR, WB_ACC, ENWR, ADR_EQU, IC_PREQ, DMA_CHK, ICTODC,

                                   RWVAL, VIRTUELL, QWATWO,

                                   DRAM_ACC, DRAM_WR, IO_ACC, IO_RD, IO_WR, PTE_MUX, PD_MUX, PKEEP, PTE_ADR, PTE_DAT, HIT_ALL, ACC_OK,

                                   ABORT, PROTECT, IACC_STAT, ABO_LEVEL1, WR_MRAM, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE, MMU_DIN, IC_SIGS, KOMUX,

                                   KDET, DMA_MUX, HLDA, RWVFLAG, PTE_STAT );

        input                   BCLK;

        input                   BRESET;

        input                   IO_SPACE;

        input                   MDONE;          // Memory Done : feedback from DRAM Controller, BCLK aligned !

        input                   IO_READY;

        input                   MMU_HIT,CA_HIT;

        input                   READ,WRITE,ZTEST,RMW;

        input   [31:0]   CAPDAT;

        input  [31:12]  VADR_R,IC_VA;

        input                   USE_CA;

        input                   PTB_WR,PTB_SEL;

        input                   SEL_PTB1;

        input  [28:12]  CPU_OUT;        // used for PTB0/1

        input                   USER;

        input                   PROT_ERROR;

        input                   WB_ACC;