OpenCores
URL https://opencores.org/ocsvn/m32632/m32632/trunk

Subversion Repositories m32632

[/] [m32632/] [trunk/] [rtl/] [DATENPFAD.v] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 ns32kum
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6
// Filename: DATENPFAD.v
7 12 ns32kum
// Version:  1.1 bug fix
8
// History:  1.0 first release of 30 Mai 2015
9
// Date:     7 October 2015
10 9 ns32kum
//
11
// Copyright (C) 2015 Udo Moeller
12
// 
13
// This source file may be used and distributed without 
14
// restriction provided that this copyright statement is not 
15
// removed from the file and that any derivative work contains 
16
// the original copyright notice and the associated disclaimer.
17
// 
18
// This source file is free software; you can redistribute it 
19
// and/or modify it under the terms of the GNU Lesser General 
20
// Public License as published by the Free Software Foundation;
21
// either version 2.1 of the License, or (at your option) any 
22
// later version. 
23
// 
24
// This source is distributed in the hope that it will be 
25
// useful, but WITHOUT ANY WARRANTY; without even the implied 
26
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
27
// PURPOSE. See the GNU Lesser General Public License for more 
28
// details. 
29
// 
30
// You should have received a copy of the GNU Lesser General 
31
// Public License along with this source; if not, download it 
32
// from http://www.opencores.org/lgpl.shtml 
33
// 
34
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
35
//
36
//      Modules contained in this file:
37
//      DATENPFAD       the data path of M32632
38
//
39 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
40 9 ns32kum
 
41 11 ns32kum
module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
42
                                  IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
43 12 ns32kum
                                  WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, REG_OUT, PTB_SEL, PTB_WR, ACB_ZERO,
44 11 ns32kum
                                  ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
45 9 ns32kum
                                  DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
46
 
47
input                   BCLK;
48
input                   BRESET;
49
input                   WREN;           // write enable of the register file
50
input                   IO_READY;
51
input                   LD_DIN;
52
input                   LD_IMME;
53
input                   WR_REG;         // write signal for the DP_FPU
54
input                   IC_USER;
55
input                   RWVFLAG;
56
input   [14:0]   ACC_FELD;
57
input    [5:0]   ACC_STAT;
58
input   [31:0]   DIN;
59
input   [31:0]   DISP;
60
input    [2:0]   IC_TEX;
61
input   [31:0]   IMME_Q;
62
input    [6:0]   INFO_AU;
63
input    [1:0]   LD_OUT;
64
input   [12:0]   DETOIP;
65
input    [1:0]   MMU_UPDATE;
66
input   [10:0]   OPER;
67
input   [31:0]   PC_ARCHI;
68
input   [31:0]   PC_ICACHE;
69
input    [7:0]   RDAA;
70
input    [7:0]   RDAB;
71
input    [1:0]   START;
72
input    [1:0]   WMASKE;
73
input    [5:0]   WRADR;
74
input                   DBG_HIT;
75
input                   COP_DONE;
76
input   [23:0]   COP_OP;
77
input   [63:0]   COP_IN;
78
 
79
output                  DONE;
80
output                  Y_INIT;
81
output                  WRITE_OUT;
82
output                  READ_OUT;
83
output                  ZTEST;
84
output                  RMW;
85 12 ns32kum
output                  QWATWO;
86 9 ns32kum
output                  ACC_DONE;
87
output                  REG_OUT;
88
output                  PTB_SEL;
89
output                  PTB_WR;
90
output reg              ACB_ZERO;
91
output                  ABORT;
92
output                  SAVE_PC;
93
output  [12:0]   CFG;
94
output   [3:0]   CINV;
95
output  [63:0]   DP_Q;
96
output   [1:0]   IVAR;
97
output   [3:0]   MCR;
98
output   [3:0]   PACKET;
99
output  [31:0]   PC_NEW;
100
output  [11:0]   PSR;
101
output   [1:0]   SIZE;
102
output   [4:0]   STRING;
103
output   [5:0]   TRAPS;
104
output  [31:0]   VADR;
105
output  [40:2]  DBG_IN;
106
output                  COP_GO;
107
output [127:0]   COP_OUT;
108
 
109
reg     [31:0]   high_dq;
110
reg             [31:0]   OUT_I;
111
reg             [31:0]   BYDIN;          // the bypass register
112
 
113
wire     [2:0]   BITSEL;
114
wire     [1:0]   BWD;
115
wire                    CLR_LSB;
116
wire    [31:0]   ERGEBNIS;       // the result bus
117
wire                    FL;
118
wire    [31:0]   FSR;
119
wire    [63:0]   MRESULT;
120
wire     [7:0]   OPCODE;
121
wire                    SELI_A;
122
wire                    SELI_B;
123
wire     [2:0]   SP_CMP;
124
wire    [31:0]   SRC1;           // the bus for the Source 1 operand
125
wire    [31:0]   SRC2;           // the bus for the Source 2 operand
126
wire     [4:0]   TT_DP;
127
wire                    TWREN;          // active if FPU Trap occurs
128
wire                    UP_DP;
129
wire                    WRADR_0;
130
wire                    WREN_L,WREN_LX;
131
wire                    LD_FSR;
132
wire                    UP_SP;
133
wire     [4:0]   TT_SP;
134
wire    [31:0]   addr_i;
135
wire     [2:0]   DP_CMP;
136
wire    [31:0]   DP_OUT;
137
wire    [31:0]   SFP_DAT;
138
wire                    ld_out_l;
139
wire     [6:0]   BMCODE;
140
wire    [31:0]   OUT_A,OUT_B;
141
wire                    SP_MUX;
142
wire    [31:0]   I_OUT;
143
wire    [31:0]   FP_OUT;
144
wire                    DOWR;
145
wire    [31:0]   DEST1,DEST2;
146
wire                    ENWR;
147
wire     [3:0]   OVF_BCD;
148
wire     [3:0]   DSR;
149
wire                    acb_zero_i;
150
wire    [31:0]   BMASKE;
151
 
152
assign  FL         = OPER[10];
153
assign  BWD        = OPER[9:8];
154
assign  OPCODE = OPER[7:0];
155
 
156
assign  ERGEBNIS = SP_MUX ? FP_OUT : I_OUT;
157
 
158
assign  WRADR_0 = WRADR[0] & ~CLR_LSB;
159
assign  ENWR = WREN_L | WREN;
160
assign  DOWR = ENWR & TWREN;
161
 
162
assign  WREN_L = WREN_LX & ~TRAPS[0];
163
 
164
assign  DP_Q[63:32] = high_dq;
165
 
166
assign  PC_NEW = SRC1;
167
 
168
always @(posedge BCLK) if (LD_OUT[1] || WREN)    ACB_ZERO <= acb_zero_i;
169
 
170
always @(posedge BCLK) if (LD_OUT[1] || ld_out_l) high_dq <= ERGEBNIS;
171
 
172
always @(posedge BCLK) if (LD_DIN) OUT_I <= LD_IMME ? IMME_Q : DIN;
173
 
174
always @(posedge BCLK) if (RDAA[7]) BYDIN <= ERGEBNIS;
175
 
176 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
177 9 ns32kum
// Register Set 1 => SRC1
178 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
179 9 ns32kum
REGISTER        REG_SET_A(
180
        .BCLK(BCLK),
181
        .ENWR(ENWR),
182
        .DOWR(DOWR),
183
        .DIN(ERGEBNIS),
184
        .BYDIN(BYDIN),
185
        .RADR(RDAA),
186
        .WADR({WRADR[5:1],WRADR_0}),
187
        .WMASKE(WMASKE),
188
        .SELI(SELI_A),
189
        .DOUT(OUT_A));
190
 
191
assign SRC1 = SELI_A ? OUT_I : OUT_A;
192
 
193 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
194 9 ns32kum
// Register Set 2 => SRC2
195 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
196 9 ns32kum
REGISTER        REG_SET_B(
197
        .BCLK(BCLK),
198
        .ENWR(ENWR),
199
        .DOWR(DOWR),
200
        .DIN(ERGEBNIS),
201
        .BYDIN(BYDIN),
202
        .RADR(RDAB),
203
        .WADR({WRADR[5:1],WRADR_0}),
204
        .WMASKE(WMASKE),
205
        .SELI(SELI_B),
206
        .DOUT(OUT_B));
207
 
208
assign SRC2 = SELI_B ? OUT_I : OUT_B;
209
 
210
MULFILTER       M_FILTER(
211
        .FLOAT(OPCODE[2]),
212
        .BWD(BWD),
213
        .SRC1(SRC1),
214
        .SRC2(SRC2),
215
        .DEST1(DEST1),
216
        .DEST2(DEST2));
217
 
218
SIGNMUL         S_MULTI(                // signed multiplier 32 * 32 bits = 64 bits
219
        .dataa(DEST1),
220
        .datab(DEST2),
221
        .result(MRESULT));
222
 
223
BITMASK  BITM_U(
224
        .AA(BMCODE),
225
        .DOUT(BMASKE));
226
 
227 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
228 9 ns32kum
// The integer data path
229 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
230 9 ns32kum
I_PFAD  GANZ_U(
231
        .FL(FL),
232
        .BRESET(BRESET),
233
        .BCLK(BCLK),
234
        .WREN(WREN),
235
        .LD_OUT(LD_OUT[1]),
236
        .ADDR(addr_i),
237
        .BITSEL(BITSEL),
238
        .BMASKE(BMASKE),
239
        .BWD(BWD),
240
        .DP_CMP(DP_CMP),
241
        .DP_OUT(DP_OUT),
242
        .FSR(FSR),
243
        .DETOIP(DETOIP[11:0]),
244
        .MRESULT(MRESULT),
245
        .OPCODE(OPCODE),
246
        .RDAA(RDAA),
247
        .SFP_DAT(SFP_DAT),
248
        .SP_CMP(SP_CMP),
249
        .SRC1(SRC1),
250
        .SRC2(SRC2),
251
        .WRADR(WRADR),
252
        .DSR(DSR),
253
        .OV_FLAG(TRAPS[2]),
254
        .ACB_ZERO(acb_zero_i),
255
        .BMCODE(BMCODE),
256
        .I_OUT(I_OUT),
257
        .PSR(PSR),
258
        .STRING(STRING),
259
        .OVF_BCD(OVF_BCD),
260
        .DISP(DISP[4:0]),
261
        .RWVFLAG(RWVFLAG));
262
 
263 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
264 9 ns32kum
// The address unit
265 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
266 9 ns32kum
ADDR_UNIT       ADDR_U(
267
        .BCLK(BCLK),
268
        .BRESET(BRESET),
269
        .IO_READY(IO_READY),
270
        .READ(ACC_FELD[11]),
271
        .WRITE(ACC_FELD[10]),
272
        .CLRMSW(ACC_FELD[2]),
273
        .FULLACC(ACC_FELD[8]),
274
        .POST(ACC_FELD[3]),
275
        .DISP_OK(INFO_AU[0]),
276
        .LDEA(ACC_FELD[9]),
277
        .NEWACC(ACC_FELD[14]),
278
        .FPU_TRAP(TRAPS[0]),
279
        .ADIVAR(INFO_AU[2]),
280
        .RWVAL_1(INFO_AU[3]),
281
        .ABO_STAT({INFO_AU[1],IC_USER}),
282
        .ACC_STAT(ACC_STAT),
283
        .ASIZE(ACC_FELD[13:12]),
284
        .BWD(BWD),
285
        .DISP(DISP),
286
        .IC_TEX(IC_TEX),
287
        .INDEX(ACC_FELD[7:4]),
288
        .MMU_UPDATE(MMU_UPDATE),
289
        .PC_ARCHI(PC_ARCHI),
290
        .PC_ICACHE(PC_ICACHE),
291
        .SRC1(SRC1),
292
        .SRC2(SRC2),
293
        .SRC2SEL(ACC_FELD[1:0]),
294
        .REG_OUT(REG_OUT),
295
        .ACC_DONE(ACC_DONE),
296
        .READ_OUT(READ_OUT),
297
        .WRITE_OUT(WRITE_OUT),
298
        .ABORT(ABORT),
299
        .ADDR(addr_i),
300
        .BITSEL(BITSEL),
301
        .PACKET(PACKET),
302
        .SIZE(SIZE),
303
        .VADR(VADR),
304
        .ZTEST(ZTEST),
305
        .RMW(RMW),
306 12 ns32kum
        .QWATWO(QWATWO),
307 9 ns32kum
        .OP_RMW(INFO_AU[4]),
308
        .PHASE_17(INFO_AU[5]),
309
        .NO_TRAP(INFO_AU[6]) );
310
 
311
CONFIG_REGS     CFG_DBG(
312
        .BCLK(BCLK),
313
        .BRESET(BRESET),
314
        .WREN(WREN),
315
        .LD_OUT(LD_OUT[1]),
316
        .OPCODE(OPCODE),
317
        .SRC1(SRC1),
318
        .WRADR(WRADR),
319
        .PTB_WR(PTB_WR),
320
        .PTB_SEL(PTB_SEL),
321
        .CFG(CFG),
322
        .CINV(CINV),
323
        .IVAR(IVAR),
324
        .Y_INIT(Y_INIT),
325
        .MCR(MCR),
326
        .DBG_TRAPS(TRAPS[5:3]),
327
        .PC_ARCHI(PC_ARCHI),
328
        .DSR(DSR),
329
        .USER(PSR[8]),
330
        .PCMATCH(DETOIP[12]),
331
        .DBG_IN(DBG_IN),
332
        .DBG_HIT(DBG_HIT),
333
        .READ(READ_OUT) );
334
 
335 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
336 9 ns32kum
// The long operation unit
337 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
338 9 ns32kum
DP_FPU  DOUBLE_U(
339
        .BCLK(BCLK),
340
        .FL(FL),
341
        .BRESET(BRESET),
342
        .LD_LDQ(LD_OUT[0]),
343
        .WR_REG(WR_REG),
344
        .BWD(BWD),
345
        .FSR(FSR[8:3]),
346
        .OPCODE(OPCODE),
347
        .SRC1(SRC1),
348
        .SRC2(SRC2),
349
        .START(START),
350
        .DONE(DONE),
351
        .UP_DP(UP_DP),
352
        .WREN_L(WREN_LX),
353
        .CLR_LSB(CLR_LSB),
354
        .LD_OUT_L(ld_out_l),
355
        .DVZ_TRAP(TRAPS[1]),
356
        .DP_CMP(DP_CMP),
357
        .DP_OUT(DP_OUT),
358
        .DP_Q(DP_Q[31:0]),
359
        .TT_DP(TT_DP),
360
        .CY_IN(PSR[0]),
361
        .OVF_BCD(OVF_BCD),
362
        .COP_DONE(COP_DONE),
363
        .COP_OP(COP_OP),
364
        .COP_IN(COP_IN),
365
        .COP_GO(COP_GO),
366
        .COP_OUT(COP_OUT));
367
 
368 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
369 9 ns32kum
// The single precision floating point unit
370 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
371 9 ns32kum
SP_FPU  SINGLE_U(
372
        .FL(FL),
373
        .BCLK(BCLK),
374
        .BWD(BWD),
375
        .FSR(FSR[8:3]),
376
        .MRESULT(MRESULT[47:0]),
377
        .OPCODE(OPCODE),
378
        .SRC1(SRC1),
379
        .SRC2(SRC2),
380
        .LD_FSR(LD_FSR),
381
        .SP_MUX(SP_MUX),
382
        .UP_SP(UP_SP),
383
        .FP_OUT(FP_OUT),
384
        .I_OUT(SFP_DAT),
385
        .SP_CMP(SP_CMP),
386
        .TT_SP(TT_SP));
387
 
388
FP_STAT_REG     FPS_REG(
389
        .BCLK(BCLK),
390
        .BRESET(BRESET),
391
        .LFSR(LD_FSR),
392
        .WREN(ENWR),
393
        .WRADR(WRADR[5:4]),
394
        .UP_DP(UP_DP),
395
        .UP_SP(UP_SP & LD_OUT[1]),
396
        .DIN(SRC1[16:0]),
397
        .TT_DP(TT_DP),
398
        .TT_SP(TT_SP),
399
        .FPU_TRAP(TRAPS[0]),
400
        .TWREN(TWREN),
401
        .SAVE_PC(SAVE_PC),
402
        .FSR(FSR));
403
 
404
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.