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[/] [m32632/] [trunk/] [rtl/] [DCACHE.v] - Blame information for rev 20

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1 9 ns32kum
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6
// Filename: DCACHE.v
7 12 ns32kum
// Version:  1.1 bug fix
8
// History:  1.0 first release of 30 Mai 2015
9
// Date:     7 October 2015
10 9 ns32kum
//
11
// Copyright (C) 2015 Udo Moeller
12
// 
13
// This source file may be used and distributed without 
14
// restriction provided that this copyright statement is not 
15
// removed from the file and that any derivative work contains 
16
// the original copyright notice and the associated disclaimer.
17
// 
18
// This source file is free software; you can redistribute it 
19
// and/or modify it under the terms of the GNU Lesser General 
20
// Public License as published by the Free Software Foundation;
21
// either version 2.1 of the License, or (at your option) any 
22
// later version. 
23
// 
24
// This source is distributed in the hope that it will be 
25
// useful, but WITHOUT ANY WARRANTY; without even the implied 
26
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
27
// PURPOSE. See the GNU Lesser General Public License for more 
28
// details. 
29
// 
30
// You should have received a copy of the GNU Lesser General 
31
// Public License along with this source; if not, download it 
32
// from http://www.opencores.org/lgpl.shtml 
33
// 
34
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
35
//
36
//      Modules contained in this file:
37
//      DCACHE          the data cache of M32632
38
//
39 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
40 9 ns32kum
 
41 12 ns32kum
module DCACHE(  BCLK, MCLK,     WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW, QWATWO,
42 11 ns32kum
                                WAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS,
43
                                PACKET, SIZE, VADR,     WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA,
44
                                ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
45 9 ns32kum
                                RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
46
 
47
input                   BCLK;
48
input                   MCLK;
49
input                   WRCFG;
50
input                   MDONE;
51
input                   BRESET;
52
input                   PTB_WR;
53
input                   PTB_SEL;
54
input                   IO_READY;
55
input                   REG_OUT;
56
input                   PSR_USER;
57
input                   WRITE;
58
input                   READ;
59
input                   ZTEST;
60
input                   RMW;
61 12 ns32kum
input                   QWATWO;
62 9 ns32kum
input                   WAMUX;
63
input                   ENWR;
64
input                   IC_PREQ;
65
input                   FILLRAM;
66
input    [1:0]   CFG;
67
input    [1:0]   CINVAL;
68
input   [27:4]  DMA_AA;
69
input   [63:0]   DP_Q;
70
input   [31:0]   DRAM_Q;
71
input  [31:12]  IC_VA;
72
input    [3:0]   ICTODC;
73
input   [31:0]   IO_Q;
74
input    [1:0]   IVAR;
75
input    [3:0]   MCR_FLAGS;
76
input    [3:0]   PACKET;
77
input    [1:0]   SIZE;
78
input   [31:0]   VADR;
79
input   [11:2]  WADDR;
80
input    [2:0]   WCTRL;
81
input    [2:0]   RWVAL;
82
input   [40:2]  DBG_IN;
83
input                   ENDRAM;
84
 
85
output                  IO_RD;
86
output                  IO_WR;
87
output                  DRAM_ACC;
88
output                  DRAM_WR;
89
output                  INIT_RUN;
90
output   [1:0]   PTE_STAT;
91
output                  KDET;
92
output                  HLDA;
93
output                  RWVFLAG;
94
output   [5:0]   ACC_STAT;
95
output  [31:0]   DP_DI;
96
output   [3:1]  IACC_STAT;
97
output   [1:0]   IC_SIGS;
98
output  [27:4]  KOLLI_A;
99
output  [23:0]   MMU_DIN;
100
output reg      [27:0]   DRAM_A;
101
output reg      [35:0]   DRAM_DI;
102
output reg      [31:0]   IO_A;
103
output reg       [3:0]   IO_BE;
104
output reg      [31:0]   IO_DI;
105
output                  DBG_HIT;
106
 
107
reg             [31:0]   DFFE_IOR;
108
reg             [31:0]   CAPDAT;
109
reg             [31:0]   VADR_R;
110
reg                             AUX_ALT;
111
reg                             DFF_QWEXT;
112
 
113
wire    [27:4]  ADDR;
114
wire                    ADR_EQU;
115
wire                    AUX_DAT;
116
wire                    CA_HIT;
117
wire                    CA_SET;
118
wire                    CUPDATE;
119
wire                    DMA_MUX;
120
wire     [3:0]   ENBYTE;
121
wire                    HIT_ALL;
122
wire                    INIT_CA_RUN;
123
wire                    IO_ACC;
124
wire                    IO_SPACE;
125
wire                    KOMUX;
126
wire                    MMU_HIT;
127
wire                    NEW_PTB;
128
wire                    PTB_ONE;
129
wire    [27:0]   PTE_ADR;
130
wire   [31:12]  RADR;
131
wire    [11:4]  TAGA;
132
wire    [23:0]   UPDATE_C;
133
wire    [31:0]   UPDATE_M;
134
wire                    USE_CA;
135
wire                    USER;
136
wire                    WB_ACC;
137
wire                    WEMV;
138
wire                    WR_MRAM;
139
wire    [31:0]   WRDATA;
140
wire                    VIRT_A;
141
wire                    PTE_MUX;
142
wire                    WE_CV;
143
wire    [23:0]   DAT_CV;
144
wire     [4:0]   WADR_CV;
145
wire                    WRSET0;
146
wire     [3:0]   BE_SET;
147
wire    [31:0]   DAT_SET;
148
wire     [9:0]   A_SET;
149
wire                    WRSET1;
150
wire                    SEL_PTB1;
151
wire                    CI;
152
wire    [27:0]   ADR_MX;
153
wire                    LD_DRAM_A;
154
wire                    VIRTUELL;
155
wire                    NEW_PTB_RUN;
156
wire                    KILL;
157
wire                    LAST_MUX;
158
wire    [31:0]   SET_DAT;
159
wire    [31:0]   ALT_DAT;
160
wire    [31:0]   DAT_MV;
161
wire     [3:0]   RADR_MV;
162
wire     [3:0]   WADR_MV;
163
wire    [31:0]   LAST_DAT;
164
wire                    WRCRAM0;
165
wire                    WRCRAM1;
166
wire                    PROT_ERROR;
167
wire                    AUX_QW;
168
wire                    PD_MUX;
169
wire    [19:0]   PTE_DAT;
170
wire                    PKEEP;
171
 
172
// +++++++++++++++++++ Memories ++++++++++++++++++++
173
 
174
reg              [7:0]   DATA0_D [0:1023];        // Data Set 0 : 4 kBytes
175
reg              [7:0]   DATA0_C [0:1023];
176
reg              [7:0]   DATA0_B [0:1023];
177
reg              [7:0]   DATA0_A [0:1023];
178
reg             [31:0]   SET_DAT0;
179
 
180
reg              [7:0]   DATA1_D [0:1023];        // Data Set 1 : 4 kBytes
181
reg              [7:0]   DATA1_C [0:1023];
182
reg              [7:0]   DATA1_B [0:1023];
183
reg              [7:0]   DATA1_A [0:1023];
184
reg             [31:0]   SET_DAT1;
185
 
186
reg             [15:0]   TAGSET_0 [0:255];        // Tag Set for Data Set 0 : 256 entries of 16 bits
187
reg             [15:0]   TAG0;
188
 
189
reg             [15:0]   TAGSET_1 [0:255];        // Tag Set for Data Set 1 : 256 entries of 16 bits
190
reg             [15:0]   TAG1;
191
 
192
reg             [23:0]   CA_VALID [0:31]; // Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
193
reg             [23:0]   CVALID;
194
 
195
reg             [35:0]   MMU_TAGS [0:255];        // Tag Set for MMU : 256 entries of 36 bits
196
reg             [35:0]   MMU_Q;
197
 
198
reg             [31:0]   MMU_VALID [0:15];        // Valid bits for MMU Tag Set : 16 entries of 32 bits
199
reg             [31:0]   MVALID;
200
 
201
assign  ADR_EQU = ({RADR[27:12],VADR_R[11:4]} == DRAM_A[27:4]); // Limited to 256 MB
202
 
203
assign  ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
204
 
205
assign  RADR    = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
206
 
207
assign  ADR_MX  = PTE_MUX ? PTE_ADR : {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET} ;
208
 
209
assign  KOLLI_A = DMA_MUX ? DMA_AA : DRAM_A[27:4] ;
210
 
211
assign  SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
212
 
213
assign  VIRT_A  = ~CINVAL[0] & VIRTUELL;
214
 
215
assign  USER    = ~MCR_FLAGS[3] & PSR_USER;
216
 
217
assign  DAT_SET = WRITE ? WRDATA : DRAM_Q ;
218
 
219
assign  BE_SET  = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};
220
 
221 12 ns32kum
assign  ADDR    = KDET ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;
222 9 ns32kum
 
223
assign  A_SET   = WAMUX ? WADDR : VADR_R[11:2] ;
224
 
225
assign  TAGA    = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
226
 
227
assign  INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
228
 
229
assign  LAST_MUX = AUX_ALT | AUX_DAT | AUX_QW;
230
 
231
assign  LAST_DAT = LAST_MUX ? ALT_DAT : SET_DAT ;
232
 
233
assign  LD_DRAM_A = ~(DRAM_ACC | PKEEP);
234
 
235
assign  ACC_STAT[4] = IO_ACC;
236
assign  ACC_STAT[5] = CA_HIT;
237
 
238
always @(posedge BCLK)
239
        if (IO_ACC)
240
                begin
241
                        IO_BE <= ENBYTE;
242
                        IO_DI <= WRDATA;
243
                        IO_A  <= {RADR[31:12],VADR_R[11:0]};
244
                end
245
 
246
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= ADR_MX[27:0];
247
 
248
always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
249
 
250
always @(posedge BCLK)
251
        begin
252
                DRAM_DI   <= {(PD_MUX ? PTE_DAT[19:16] : ENBYTE),WRDATA[31:16],
253
                                          (PD_MUX ? PTE_DAT[15:0]  : WRDATA[15:0])};
254
                AUX_ALT   <= DFF_QWEXT | IO_RD;
255
                DFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1];
256
                VADR_R    <= VADR;
257
        end
258
 
259
always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
260
 
261
// +++++++++++++++++++++++++  Cache Valid  +++++++++++++++++++
262
 
263
always @(posedge BCLK) CVALID <= CA_VALID[TAGA[11:7]];
264
 
265
always @(negedge BCLK) if (WE_CV) CA_VALID[WADR_CV] <= DAT_CV;
266
 
267
// +++++++++++++++++++++++++  Tag Set 0  +++++++++++++++++++++
268
 
269
always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];
270
 
271
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];
272
 
273
// +++++++++++++++++++++++++  Tag Set 1  +++++++++++++++++++++
274
 
275
always @(posedge BCLK) TAG1 <= TAGSET_1[TAGA];
276
 
277
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];
278
 
279
// +++++++++++++++++++++++++  Data Set 0  ++++++++++++++++++++
280
 
281
always @(posedge BCLK)
282
        begin
283
                SET_DAT0[31:24] <= DATA0_D[VADR[11:2]];
284
                SET_DAT0[23:16] <= DATA0_C[VADR[11:2]];
285
                SET_DAT0[15:8]  <= DATA0_B[VADR[11:2]];
286
                SET_DAT0[7:0]    <= DATA0_A[VADR[11:2]];
287
        end
288
 
289
always @(posedge MCLK)
290
        if (WRSET0)
291
                begin
292
                        if (BE_SET[3]) DATA0_D[A_SET] <= DAT_SET[31:24];
293
                        if (BE_SET[2]) DATA0_C[A_SET] <= DAT_SET[23:16];
294
                        if (BE_SET[1]) DATA0_B[A_SET] <= DAT_SET[15:8];
295
                        if (BE_SET[0]) DATA0_A[A_SET] <= DAT_SET[7:0];
296
                end
297
 
298
// +++++++++++++++++++++++++  Data Set 1  ++++++++++++++++++++
299
 
300
always @(posedge BCLK)
301
        begin
302
                SET_DAT1[31:24] <= DATA1_D[VADR[11:2]];
303
                SET_DAT1[23:16] <= DATA1_C[VADR[11:2]];
304
                SET_DAT1[15:8]  <= DATA1_B[VADR[11:2]];
305
                SET_DAT1[7:0]    <= DATA1_A[VADR[11:2]];
306
        end
307
 
308
always @(posedge MCLK)
309
        if (WRSET1)
310
                begin
311
                        if (BE_SET[3]) DATA1_D[A_SET] <= DAT_SET[31:24];
312
                        if (BE_SET[2]) DATA1_C[A_SET] <= DAT_SET[23:16];
313
                        if (BE_SET[1]) DATA1_B[A_SET] <= DAT_SET[15:8];
314
                        if (BE_SET[0]) DATA1_A[A_SET] <= DAT_SET[7:0];
315
                end
316
 
317
DCACHE_SM       DC_SM(
318
        .BCLK(BCLK),
319
        .BRESET(BRESET),
320
        .VIRTUELL(VIRTUELL),
321
        .IO_SPACE(IO_SPACE),
322
        .MDONE(MDONE),
323
        .MMU_HIT(MMU_HIT),
324
        .CA_HIT(CA_HIT),
325
        .READ(READ),
326
        .WRITE(WRITE),
327
        .ZTEST(ZTEST),
328
        .RMW(RMW),
329 12 ns32kum
        .QWATWO(QWATWO),
330 9 ns32kum
        .USE_CA(USE_CA),
331
        .PTB_WR(PTB_WR),
332
        .PTB_SEL(PTB_SEL),
333
        .SEL_PTB1(SEL_PTB1),
334
        .IO_READY(IO_READY),
335
        .USER(USER),
336
        .PROTECT(ACC_STAT[3]),
337
        .PROT_ERROR(PROT_ERROR),
338
        .ENWR(ENWR),
339
        .WB_ACC(WB_ACC),
340
        .ADR_EQU(ADR_EQU),
341
        .IC_PREQ(IC_PREQ),
342
        .CAPDAT(CAPDAT[31:0]),
343
        .CPU_OUT(DP_Q[59:44]),
344
        .FILLRAM(FILLRAM),
345
        .IC_VA(IC_VA),
346
        .ICTODC(ICTODC),
347
        .VADR_R(VADR_R[31:12]),
348
        .NEW_PTB(NEW_PTB),
349
        .PTB_ONE(PTB_ONE),
350
        .DRAM_ACC(DRAM_ACC),
351
        .DRAM_WR(DRAM_WR),
352
        .IO_ACC(IO_ACC),
353
        .IO_RD(IO_RD),
354
        .IO_WR(IO_WR),
355
        .PTE_STAT(PTE_STAT),
356
        .ABORT(ACC_STAT[1]),
357
        .WR_MRAM(WR_MRAM),
358
        .CUPDATE(CUPDATE),
359
        .AUX_DAT(AUX_DAT),
360
        .PTE_MUX(PTE_MUX),
361
        .ACC_OK(ACC_STAT[0]),
362
        .ABO_LEVEL1(ACC_STAT[2]),
363
        .IACC_STAT(IACC_STAT),
364
        .KOMUX(KOMUX),
365
        .KDET(KDET),
366
        .HIT_ALL(HIT_ALL),
367
        .DMA_MUX(DMA_MUX),
368
        .HLDA(HLDA),
369
        .RWVAL(RWVAL[1:0]),
370
        .RWVFLAG(RWVFLAG),
371
        .IC_SIGS(IC_SIGS),
372
        .MMU_DIN(MMU_DIN),
373
        .PD_MUX(PD_MUX),
374
        .PKEEP(PKEEP),
375
        .PTE_ADR(PTE_ADR),
376
        .PTE_DAT(PTE_DAT));
377
 
378
CA_MATCH        DCA_COMPARE(
379
        .INVAL_L(CINVAL[0]),
380
        .CI(CI),
381
        .MMU_HIT(MMU_HIT),
382
        .WRITE(WRITE),
383
        .KDET(KDET),
384
        .ADDR(ADDR),
385
        .CFG(CFG),
386
        .ENDRAM(ENDRAM),
387
        .CVALID(CVALID),
388
        .TAG0(TAG0),
389
        .TAG1(TAG1),
390
        .CA_HIT(CA_HIT),
391
        .CA_SET(CA_SET),
392
        .WB_ACC(WB_ACC),
393
        .USE_CA(USE_CA),
394
        .IOSEL(RADR[31:28]),
395
        .IO_SPACE(IO_SPACE),
396
        .KILL(KILL),
397
        .DC_ILO(RWVAL[2]),
398
        .UPDATE(UPDATE_C));
399
 
400
DCA_CONTROL     DCA_CTRL(
401
        .BCLK(BCLK),
402
        .MCLK(MCLK),
403
        .BRESET(BRESET),
404
        .CA_SET(CA_SET),
405
        .HIT_ALL(HIT_ALL),
406
        .UPDATE(UPDATE_C),
407
        .VADR_R(ADDR[11:7]),
408
        .DRAM_ACC(DRAM_ACC),
409
        .CUPDATE(CUPDATE),
410
        .KILL(KILL),
411
        .WRITE(WRITE),
412
        .WRCFG(WRCFG),
413
        .WCTRL(WCTRL[1:0]),
414
        .INVAL_A(CINVAL[1]),
415
        .DAT_CV(DAT_CV),
416
        .WADR_CV(WADR_CV),
417
        .WE_CV(WE_CV),
418
        .INIT_CA_RUN(INIT_CA_RUN),
419
        .WRCRAM0(WRCRAM0),
420
        .WRCRAM1(WRCRAM1),
421
        .WRSET0(WRSET0),
422
        .WRSET1(WRSET1));
423
 
424
MMU_MATCH       MMU_COMPARE(
425
        .USER(USER),
426
        .WRITE(WRITE),
427
        .READ(READ),
428
        .RMW(RMW),
429
        .IVAR(IVAR),
430
        .MCR_FLAGS(MCR_FLAGS[2:0]),
431
        .MMU_VA(MMU_Q[35:20]),
432
        .MVALID(MVALID),
433
        .VADR_R(VADR_R[31:12]),
434
        .MMU_HIT(MMU_HIT),
435
        .PROT_ERROR(PROT_ERROR),
436
        .VIRTUELL(VIRTUELL),
437
        .CI(CI),
438
        .SEL_PTB1(SEL_PTB1),
439
        .UPDATE(UPDATE_M));
440
 
441
MMU_UP  MMU_CTRL(
442
        .BCLK(BCLK),
443
        .BRESET(BRESET),
444
        .NEW_PTB(NEW_PTB),
445
        .IVAR(IVAR[1]),
446
        .PTB1(PTB_ONE),
447
        .WR_MRAM(WR_MRAM),
448
        .MVALID(MVALID),
449
        .UPDATE(UPDATE_M),
450
        .VADR(VADR[19:16]),
451
        .VADR_R(VADR_R[19:16]),
452
        .WE_MV(WEMV),
453
        .NEW_PTB_RUN(NEW_PTB_RUN),
454
        .DAT_MV(DAT_MV),
455
        .RADR_MV(RADR_MV),
456
        .WADR_MV(WADR_MV));
457
 
458
// +++++++++++++++++++++++++  MMU Valid  +++++++++++++++++++++
459
 
460
always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];
461
 
462
always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;
463
 
464
// +++++++++++++++++++++++++  MMU Tags  ++++++++++++++++++++++
465
 
466
always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];
467
 
468
always @(negedge BCLK) if (WR_MRAM) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
469
 
470
RD_ALIGNER      RD_ALI(
471
        .BCLK(BCLK),
472
        .ACC_OK(ACC_STAT[0]),
473
        .REG_OUT(REG_OUT),
474
        .PACKET(PACKET),
475
        .RDDATA(LAST_DAT),
476
        .SIZE(SIZE),
477
        .CA_HIT(CA_HIT),
478
        .DP_DI(DP_DI),
479
        .AUX_QW(AUX_QW));
480
 
481
WR_ALIGNER      WR_ALI(
482
        .DP_Q(DP_Q),
483
        .PACKET(PACKET),
484
        .SIZE(SIZE),
485
        .ENBYTE(ENBYTE),
486
        .WRDATA(WRDATA));
487
 
488
DEBUG_AE DBGAE(
489
        .DBG_IN(DBG_IN),
490
        .READ(READ),
491
        .WRITE(WRITE),
492
        .USER(USER),
493
        .VIRTUELL(VIRTUELL),
494
        .ACC_OK(ACC_STAT[0]),
495
        .VADR_R(VADR_R[31:2]),
496
        .MMU_Q(MMU_Q[19:0]),
497
        .ENBYTE(ENBYTE),
498
        .DBG_HIT(DBG_HIT));
499
 
500
endmodule

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